EP0743586B1 - Integrated circuit in which some components have to work with the same operating characteristic - Google Patents

Description

The present invention relates to integrated circuits in which some or all of the components or groups of functional components must work in the same conditions to ensure the proper functioning of the circuit in general.

When in an integrated circuit such as an MOS circuit, two components, for example two transistors, are located close to each other, it is relatively easy to give them the same operating conditions, for example the same curve characteristic of the drain current I _D as a function of the gate voltage V _g .

On the other hand, when the components are distant one on the other in the circuit, or a fortiori, when many components have to work in the same conditions, the parameters of the components will then be dependent on their topographic distance in the circuit, which can practically not be manufactured with the necessary uniformity. Besides other factors, such as temperature differences from place to place the other of a circuit, can induce a non-uniformity of component operating parameters.

A technique currently used to impose identical operating characteristics to transistors distant from an integrated circuit consists of their impose a parameter (for example a current) and we set a quantity determining the characteristic (for example the grid voltage). This method has the disadvantage that the control current cannot be used simultaneously by the two transistors and then you have to order alternately. Therefore the transistors do not are available to perform their function assigned in the circuit only when they are not in regulatory regime. In addition, the number of transistors that we can thus work under the same conditions is necessarily limited, because otherwise the frequency with which control current is distributed sequentially will become too high vis-à-vis that of the useful signal to treat.

This known method therefore has drawbacks some.

The invention aims to provide an integrated circuit comprising means for imposing on a plurality of its components or groups of components the same characteristic of operation, this circuit being devoid of disadvantages of the prior art briefly described above.

• des moyens formant un générateur de référence central destiné à élaborer au moins une information de consigne qui détermine la caractéristique de fonctionnement devant être commune à tous les composants fonctionnels du circuit;
• des moyens pour distribuer l'information de consigne parmi une pluralité d'unités du circuit comprenant chacune au moins un desdits composants fonctionnels;
• chacune desdites unités comprenant des moyens locaux d'ajustement connectés pour recevoir ladite information de consigne et pour élaborer une valeur d'ajustement;
• des moyens de correction dans chaque unité pour ajuster la caractéristique de fonctionnement d'un dispositif prévu dans lesdits moyens locaux d'ajustement, en fonction de ladite valeur d'ajustement, ledit dispositif étant placé à proximité du ou des composant(s) fonctionnel(s) et configuré de telle sorte que la caractéristique de fonctionnement qui lui est ainsi imposée, s'impose également au(x)dit(s) composant(s) fonctionnel(s);
• des moyens de correction dans chaque unité pour ajuster la caractéristique de fonctionnement de son ou ses composant(s) fonctionnel(s) en fonction de ladite valeur d'ajustement.

The subject of the invention is therefore an integrated circuit characterized in that it comprises:

• means forming a central reference generator intended to generate at least setpoint information which determines the operating characteristic to be common to all the functional components of the circuit;
• means for distributing the setpoint information among a plurality of circuit units each comprising at least one of said functional components;
• each of said units comprising local adjustment means connected to receive said setpoint information and to develop an adjustment value;
• correction means in each unit for adjusting the operating characteristic of a device provided in said local adjustment means, as a function of said adjustment value, said device being placed near the functional component (s) ( s) and configured in such a way that the operating characteristic which is thus imposed on it, is also imposed on the said functional component (s);
• correction means in each unit for adjusting the operating characteristic of its functional component (s) as a function of said adjustment value.

• la figure 1 est un schéma très simplifié d'un circuit intégré pour mettre en évidence les caractéristiques essentielles de l'invention; et
• les figures 2 à 4 montrent trois exemples d'application de l'invention.

Other characteristics and advantages of the invention will become apparent during the description which follows, given solely by way of example and made with reference to the appended drawings in which:

• Figure 1 is a very simplified diagram of an integrated circuit to highlight the essential characteristics of the invention; and
• Figures 2 to 4 show three examples of application of the invention.

In FIG. 1, a general diagram is shown very simplified of an integrated circuit comprising a system according to the invention.

The integrated circuit symbolized by rectangle 1, has a plurality of functional units 2-1 to 2-n distributed on the integrated circuit and which one supposes that they must all work with the same characteristic of operation.

In this context, it should be noted that by integrated circuit any functional assembly which may include one or more chips, the functional units being able to be components or groups of components of any kind such as transistors, diodes, groups of transistors, diode groups, circuit parts composed of assemblies of such components etc. Through elsewhere, although Figure 1 shows a distribution of its functional units, this is not a limiting element of the concept of the invention, these units can be installed in the circuit only in according to the specific needs and tasks that the integrated circuit must accomplish.

According to the invention, the integrated circuit includes a central setpoint generator 3 located at a location suitable for this circuit and intended to develop a signal setpoint according to which the characteristic of functioning of the functional units will be developed. This generator has n outputs connected to as many lines 4-1 to 4-n which are respectively connected to cells adjustment local 5-1 to 5-n. These cells are respectively associated with functional units 2-1 to 2-n by being placed near their respective unit.

The setpoint information generated in the generator central 3 can be applied simultaneously to cells adjustment 5-1 to 5-n, but according to a characteristic particular of the invention, it can also be sent sequentially to these cells, in which case the central generator 3 includes a sequencer 6 shown in dotted in the rectangle which symbolizes the generator instruction 3. This variant of the invention is especially useful when the setpoint information cannot be used without be altered by several adjustment cells at the same time.

It should be noted that in an integrated circuit comprising a system according to the invention, the functional units remain operational at all times, even if the information only reaches their cell sequentially associated adjustment.

We will now describe several examples application of the concept according to the invention.

Concerning a first of these examples, we will note that often, due to certain technological hazards, threshold voltages of the transistors of an MOS integrated circuit are not the same throughout the circuit. The first example described therefore aims to impose on all the transistors of the circuit the same so-called threshold voltage "related". In this first example, we assume that the characteristic to be imposed on the transistors of the circuit (which are the functional units here) is this apparent threshold voltage. The adjustment of the tensions of threshold of all the transistors at the same value, allows simplified exchange of analog information between different parts of the integrated circuit, this information thus being interpreted in the same way all over the circuit.

We know that an n-type MOS transistor operating in strong inversion lets through a drain current I _D which has the following relation: I D = k (( V G - V YOUR ) 2 in which I _D is the drain current of the transistor, V _G its gate voltage and V _TA its apparent threshold voltage as long as V _G >> V _TA , that is to say when the transistor works in strong inversion .

We also know that the apparent threshold voltage V _TA of a MOS transistor is defined by the following relation: V YOUR = V T + nV S - ( not -1) V W in which V _T is the "physical" threshold voltage of the transistor, V _S its source voltage, V _W the box voltage and n the coupling coefficient defined as follows: not = 1+ VS D VS i

In equation (3), C _D is the depletion capacity of the transistor and C _i its oxide capacity.

Note that we can write the same relations, mutatis mutandis, for a p-type transistor.

It follows from relation (2) above, that the apparent threshold voltage V _TA of all the transistors of the circuit can be determined by adjusting the box voltage V _W.

In the first example of application of the invention described, this property is used to adjust the threshold voltage of all the useful transistors of the integrated circuit and for this purpose we use the circuit that goes now be described with reference to Figure 2.

For the sake of simplification, this figure does not represent that the setpoint generator 3, as well as a single transistor useful 2-n with its associated local 5-n adjustment cell.

The setpoint generator 3 shown in FIG. 2 is intended for n-type transistors. It comprises two transistors MG1 and MG2, the sources of which are connected to a negative supply conductor of voltage V _GM . Their drains are connected to their respective grids, and to the drains of two respective transistors MG3 and MG4 mounted in current mirror. The boxes of the transistors MG1 and MG2 are connected to a supply terminal V _GW . The gates of the transistors MG3 and MG4 are connected to a bias voltage terminal V _GI , while their sources are connected to a positive supply voltage V _GP .

As the transistors MG1 to MG4 are placed very close each other on the integrated circuit, their voltages apparent thresholds are identical two by two.

Furthermore, the transistors having a determined width ratio, they conduct currents I _MG3 and I _MG4 having this ratio: K m = I MG 4 I MG 3

The transistors MG1 and MG2 will conduct currents I _MG3 and I _MG4 which determine the gate voltages V _G1 and V _G2 respectively. Indeed, it follows from equations (1) and (2) above that these tensions are linked in a regime of strong inversion by the relation: K M = V G 1 - V T - nV S + ( not -1) V W V G 2 - V T - nV S + ( not -1) V W 2

Thus, the voltages V _G1 and V _G2 can constitute setpoint information which can be used in the local adjustment cell 5-n to determine, for the useful transistor 2-n which is associated with it, an apparent threshold voltage V Identical _TA using the box voltage V _W as an adjustment parameter, the actual threshold voltages of all the useful transistors being able to be different from one cell to another.

The local adjustment cell 5-n comprises a current mirror formed by the transistors MC3 and MC4 whose widths are in a ratio K _M. This is relatively easy to achieve even if the distance separating the setpoint generator 3 from this local cell is relatively large.

The sources of these transistors MC3 and MC4 are connected to a supply voltage V _UP , while their drains are respectively connected to the drains of two transistors MC1 and MC2, the sources of which are connected to a voltage V _UM . The gate of transistor MC3 is connected to its drain. The gates of the transistors MC1 and MC2 are connected respectively to the voltages V _G1 and V _G2 coming from the setpoint generator 3.

The common point of the transistors MC2 and MC4 is connected at the input of an amplifier A and at a terminal of a capacitor C. The output of amplifier A is connected to the boxes of transistors MC1, MC2 and MU.

In this 5-n adjustment cell, the transistors MC1 and MC2 operate in strong inversion and generate respective currents determined by relation (1) above. The current mirror formed by the transistors MC3 and MC4 makes a copy of the current generated by the transistor MC1 by multiplying it by the constant K _M. In adjustment mode, the capacitor C integrates the difference between the current passing through the transistor MC4 and the current passing through MC2. The amplifier transmits the corresponding value on the wells of the transistors MC1 and MC2 and also on that of the useful transistor MU. The regime stabilizes when the difference in these currents is zero. Under these conditions, the transistor MU has an apparent threshold voltage which is identical to that of the transistors MG1 and MG2 of the reference generator.

So by associating with each useful transistor or each group of useful transistors located nearby from each other an adjustment cell such as the cell 5-n, we can give them the same threshold voltage whose value is imposed by the central generator of instruction 3.

Note that in this first example application of the invention, all useful transistors 2-1 to 2-n can work continuously and are not disturbed by the adjustment of the tension of their box.

In a second example of application of the invention, it is assumed that it is desirable to operate a certain number of transistors of an integrated circuit on the same work point despite the disparities in their characteristic curves I _drain / V _grid according to the locations of the transistors in the integrated circuit.

In FIG. 3, a central reference generator 3A has been shown which, in this case, produces a reference voltage V _ref and a reference current I _{ref as a} reference. As it is a question here of transmitting a current setpoint, it is necessary to distribute this reference current I _ref sequentially.

The setpoint generator 3A comprises a voltage source ST which is connected to the gate of a transistor MG5 and to an output of the generator delivering the reference voltage V _ref . The drain of transistor MG5 is connected to a current mirror formed by transistors MG6 and MG7, the latter delivering the reference current I _ref .

The local adjustment cell 5A-n comprises a transistor MC5 whose gate receives the voltage V _ref . Its drain is connected to two switches S1 and S2 controlled by the sequencer 6. The switch S1 receives the reference current I _ref from the reference generator 3A. Switch S2 is connected to the common point of an AC capacitor and an AA amplifier. The output of the latter is connected to the wells of the transistors MC5 and MU (2A-n).

When the cell 5A-n is in the adjustment phase, these switches S1 and S2 then being closed by the sequencer 6, the current I _ref can reach the capacitor AC and the input of the amplifier AA. The voltage on the capacitor AC stabilizes when the current flowing through the transistor MC5 is equal to the reference current I _ref . The switches S1 and S2 can then be opened again, the capacitor CA memorizing the adjustment voltage at the input of the amplifier AA. The reference current I _ref can then be sent to another local adjustment cell of the integrated circuit.

So we see that, in this case too, the transistor useful can continue to function whether it is in operation adjustment or not.

The third example of application of the invention is shown in Figure 4. Here, the useful components do not are not transistors, but diodes or photodiodes, the latter being, for example, part a network of detectors or the like. It can then be important that all these diodes have the same current of flight. However, we know that the leakage current of a diode is strongly dependent on temperature.

The central reference generator 3B generates, for example by means of the assembly shown in FIG. 3 at 3A, a reference current I _ref which is distributed to the local adjustment cells such as cell 5B-n, by means of the sequencer 6 .

The local adjustment cell 5B-n comprises a diode P1 which is connected to the switches S1 and S2, these being closed in adjustment mode. Switch S2 is also connected to the common point of a capacitor CB and the input of an amplifier AB. The output of the latter is connected to a heat dissipation resistor RT placed near the diode P1 and the useful diode P2 (2B-n). A current I _C is therefore sent as an adjustment value in this dissipating resistor RT. Diode P2 (and possibly other diodes located nearby) will thus receive (have) a caloric intake which determines the same leakage current for all the diodes.

The current flows through the dissipating resistor RT as long as the current in the diode P1 is not equal to the reference current I _ref . The sequencer 6 makes it possible to serve other similar heating assemblies distributed in the array of photodiodes.

It should be noted that if the diodes P1 and P2 are identical (they are located close to each other) and if only the photodiode P2 is exposed to light, this assembly also makes it possible to control the "black" current of the photodiode P2.

In addition, the local adjustment units must be thermally isolated from each other.

It should be noted that in this case also, the CB capacitor acts as memory and retains the setpoint between two addresses made by the sequencer 6.

Claims (12)

1. An integrated circuit which comprises:

   means forming a central reference generator (3, 3A, 3B) intended to generate at least one setpoint item (V_G1, V_G2; I_ref, V_ref; I_ref) which determines the operating characteristic required to be common to at least a plurality of functional components of the circuit;

   means (4-1 to 4-n; 6) for distributing the setpoint item among at least a plurality of units of the circuit, each unit comprising at least one of said functional components (2-n; 2A-n; 2B-n);

   each of said units comprising local adjustment means (5-n; 5A-n; 5B-n) connected to receive said setpoint item (V_G1, V_G2; I_ref, V_ref; I_ref) and to generate an adjustment value (V_W, I_C);

   correction means (C, A; CA, AA; CB, AB) in each unit in order to adjust the operating characteristic of a device (MC1, MC2; MC5; P1), provided for in said local adjustment means (5-n; 5A-n; 5B-n), as a function of said adjustment value, said device being placed in proximity to the functional component(s) and configured in such a way that the operating characteristic which is thus imposed on it is also imposed on the functional component(s) (2-n; 2A-n; 2B-n).
2. The integrated circuit as claimed in claim 1, including MOS transistors, wherein said operating characteristic is the apparent threshold voltage (V_TA) of at least some of its MOS transistors (2-1 to 2-n; Figure 2).
3. The integrated circuit as claimed in claim 1, including MOS transistors, wherein said operating characteristic is a predetermined working point on the drain current/gate voltage curve of at least some of these MOS transistors (2A-n; Figure 3).
4. The integrated circuit as claimed in claim 2, including diodes or photodiodes, wherein said operating characteristic is the leakage current of said diodes (P2; Figure 4).
5. The integrated circuit as claimed in either one of claims 2 and 3 taken together, wherein said adjustment value is the well voltage (V_W) of at least some of said MOS transistors (2-1 to 2-n).
6. The integrated circuit as claimed in claims 2 and 5 taken together, wherein said central reference generator (3) includes means (MG2, MG4) for establishing a first ratio of two currents (K_M) which represents the value of said desired apparent threshold voltage (V_TA) and means (MG1, MG2) for converting, as a function of a predetermined well voltage value (V_GW), this first ratio of currents into a pair of voltages (VG1, VG2) forming said setpoint item, and wherein said local adjustment means (5-1 to 5-n) comprise means (MC3, MC4) for locally establishing a second ratio of currents and means (MC1, MC2, C, A) for producing, as a function of said setpoint item, a signal for modifying the well voltage (V_UW) of said functional component or components (2-1 to 2-n) associated with the relevant local adjustment means (5-1 to 5-n), in order to adjust said second ratio of currents to said first ratio of currents.
7. The integrated circuit as claimed in claim 6, wherein

   said central reference generator (3) includes a current mirror formed from two MOS transistors (MG3, MG4) whose widths have said first ratio of currents and two other MOS transistors (MC1, MC2) mounted respectively in series with the transistors of the current mirror and whose well voltage (V_GW) exhibits said predetermined well voltage value, said two other transistors (MG1, MG2) being arranged in order to operate under strong inversion and to yield said setpoint item (V_G1, V_G2) on their gates, and wherein

   said local adjustment means (5-1 to 5-n) comprise a setup identical to that of said central reference generator (3), the junction point between one (MC4) of the transistors of their current mirror and said corresponding other transistor (MC2) being linked up to an amplifier (A) which yields said adjustment value (V_UW), the output of this amplifier being linked to the wells of said other transistors (MC1, MC2) of these local adjustment means and to that of the functional component (MU) associated with these means.
8. The integrated circuit as claimed in claims 3 and 5 taken together, wherein said central reference generator (3A) includes a voltage source (ST) delivering a reference voltage (V_ref) and a current source (MG5, MG6 and MG7) delivering a reference current (I_ref), wherein said local adjustment means (5A-n) comprise a transistor (MC5) connected in order to receive said reference voltage on its gate, and an amplifier (AA) connected in order to amplify the difference between said reference current and the current flowing through this transistor (MC5), the output of said amplifier (AA) being connected to the well of the latter and that of said functional component (MU) in order to supply them with said adjustment value (V_W).
9. The integrated circuit as claimed in claim 8, wherein it comprises a sequencer (6) for dispatching said reference current (I_ref) in turn to said local adjustment means, and wherein said local adjustment means comprise memory means (CA) in order to preserve said adjustment value (V_W) between two dispatches of said reference current to these means.
10. The integrated circuit as claimed in claim 4, wherein said adjustment value is the temperature (T) of said circuit.
11. The integrated circuit as claimed in claim 10, wherein said central reference generator (3B) comprises a reference current source (I_ref), and wherein said local adjustment means comprise a reference diode (P1), as well as an amplifier (AB) in order to amplify the difference between the reference current and the current flowing in said diode (P1), the output of said amplifier (AB) being connected to a heat dissipater component (RT) placed near said diode (P1) and near the diode (P2) which forms said functional component.
12. The integrated circuit as claimed in claim 11, wherein it includes a sequencer (6) in order to dispatch said reference current (I_ref) in turn to said local adjustment means (5B-n).

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