EP0743586B1 - Integrierte Schaltung in der einige Bauelemente mit dem selben Betriebsverhalten arbeiten sollen - Google Patents

Integrierte Schaltung in der einige Bauelemente mit dem selben Betriebsverhalten arbeiten sollen Download PDF

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Publication number
EP0743586B1
EP0743586B1 EP96401074A EP96401074A EP0743586B1 EP 0743586 B1 EP0743586 B1 EP 0743586B1 EP 96401074 A EP96401074 A EP 96401074A EP 96401074 A EP96401074 A EP 96401074A EP 0743586 B1 EP0743586 B1 EP 0743586B1
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EP
European Patent Office
Prior art keywords
integrated circuit
ref
current
transistors
voltage
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP96401074A
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English (en)
French (fr)
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EP0743586A1 (de
Inventor
Michel Alain Chevroulet
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Centre Suisse dElectronique et Microtechnique SA CSEM
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Centre Suisse dElectronique et Microtechnique SA CSEM
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
    • G05F3/242—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/262—Current mirrors using field-effect transistors only

Definitions

  • the present invention relates to integrated circuits in which some or all of the components or groups of functional components must work in the same conditions to ensure the proper functioning of the circuit in general.
  • a technique currently used to impose identical operating characteristics to transistors distant from an integrated circuit consists of their impose a parameter (for example a current) and we set a quantity determining the characteristic (for example the grid voltage).
  • This method has the disadvantage that the control current cannot be used simultaneously by the two transistors and then you have to order alternately. Therefore the transistors do not are available to perform their function assigned in the circuit only when they are not in regulatory regime.
  • the number of transistors that we can thus work under the same conditions is necessarily limited, because otherwise the frequency with which control current is distributed sequentially will become too high vis-à-vis that of the useful signal to treat.
  • the invention aims to provide an integrated circuit comprising means for imposing on a plurality of its components or groups of components the same characteristic of operation, this circuit being devoid of disadvantages of the prior art briefly described above.
  • FIG. 1 a general diagram is shown very simplified of an integrated circuit comprising a system according to the invention.
  • the integrated circuit symbolized by rectangle 1 has a plurality of functional units 2-1 to 2-n distributed on the integrated circuit and which one supposes that they must all work with the same characteristic of operation.
  • any functional assembly which may include one or more chips, the functional units being able to be components or groups of components of any kind such as transistors, diodes, groups of transistors, diode groups, circuit parts composed of assemblies of such components etc.
  • Figure 1 shows a distribution of its functional units, this is not a limiting element of the concept of the invention, these units can be installed in the circuit only in according to the specific needs and tasks that the integrated circuit must accomplish.
  • the integrated circuit includes a central setpoint generator 3 located at a location suitable for this circuit and intended to develop a signal setpoint according to which the characteristic of functioning of the functional units will be developed.
  • This generator has n outputs connected to as many lines 4-1 to 4-n which are respectively connected to cells adjustment local 5-1 to 5-n. These cells are respectively associated with functional units 2-1 to 2-n by being placed near their respective unit.
  • the setpoint information generated in the generator central 3 can be applied simultaneously to cells adjustment 5-1 to 5-n, but according to a characteristic particular of the invention, it can also be sent sequentially to these cells, in which case the central generator 3 includes a sequencer 6 shown in dotted in the rectangle which symbolizes the generator instruction 3.
  • This variant of the invention is especially useful when the setpoint information cannot be used without be altered by several adjustment cells at the same time.
  • threshold voltages of the transistors of an MOS integrated circuit are not the same throughout the circuit.
  • the first example described therefore aims to impose on all the transistors of the circuit the same so-called threshold voltage "related".
  • the characteristic to be imposed on the transistors of the circuit is this apparent threshold voltage.
  • the adjustment of the tensions of threshold of all the transistors at the same value allows simplified exchange of analog information between different parts of the integrated circuit, this information thus being interpreted in the same way all over the circuit.
  • I D k (( V G - V YOUR ) 2 in which I D is the drain current of the transistor, V G its gate voltage and V TA its apparent threshold voltage as long as V G >> V TA , that is to say when the transistor works in strong inversion .
  • C D is the depletion capacity of the transistor and C i its oxide capacity.
  • this figure does not represent that the setpoint generator 3, as well as a single transistor useful 2-n with its associated local 5-n adjustment cell.
  • the setpoint generator 3 shown in FIG. 2 is intended for n-type transistors. It comprises two transistors MG1 and MG2, the sources of which are connected to a negative supply conductor of voltage V GM . Their drains are connected to their respective grids, and to the drains of two respective transistors MG3 and MG4 mounted in current mirror. The boxes of the transistors MG1 and MG2 are connected to a supply terminal V GW . The gates of the transistors MG3 and MG4 are connected to a bias voltage terminal V GI , while their sources are connected to a positive supply voltage V GP .
  • the voltages V G1 and V G2 can constitute setpoint information which can be used in the local adjustment cell 5-n to determine, for the useful transistor 2-n which is associated with it, an apparent threshold voltage V Identical TA using the box voltage V W as an adjustment parameter, the actual threshold voltages of all the useful transistors being able to be different from one cell to another.
  • the local adjustment cell 5-n comprises a current mirror formed by the transistors MC3 and MC4 whose widths are in a ratio K M. This is relatively easy to achieve even if the distance separating the setpoint generator 3 from this local cell is relatively large.
  • the sources of these transistors MC3 and MC4 are connected to a supply voltage V UP , while their drains are respectively connected to the drains of two transistors MC1 and MC2, the sources of which are connected to a voltage V UM .
  • the gate of transistor MC3 is connected to its drain.
  • the gates of the transistors MC1 and MC2 are connected respectively to the voltages V G1 and V G2 coming from the setpoint generator 3.
  • the common point of the transistors MC2 and MC4 is connected at the input of an amplifier A and at a terminal of a capacitor C.
  • the output of amplifier A is connected to the boxes of transistors MC1, MC2 and MU.
  • the transistors MC1 and MC2 operate in strong inversion and generate respective currents determined by relation (1) above.
  • the current mirror formed by the transistors MC3 and MC4 makes a copy of the current generated by the transistor MC1 by multiplying it by the constant K M.
  • the capacitor C integrates the difference between the current passing through the transistor MC4 and the current passing through MC2.
  • the amplifier transmits the corresponding value on the wells of the transistors MC1 and MC2 and also on that of the useful transistor MU. The regime stabilizes when the difference in these currents is zero. Under these conditions, the transistor MU has an apparent threshold voltage which is identical to that of the transistors MG1 and MG2 of the reference generator.
  • FIG. 3 a central reference generator 3A has been shown which, in this case, produces a reference voltage V ref and a reference current I ref as a reference. As it is a question here of transmitting a current setpoint, it is necessary to distribute this reference current I ref sequentially.
  • the setpoint generator 3A comprises a voltage source ST which is connected to the gate of a transistor MG5 and to an output of the generator delivering the reference voltage V ref .
  • the drain of transistor MG5 is connected to a current mirror formed by transistors MG6 and MG7, the latter delivering the reference current I ref .
  • the local adjustment cell 5A-n comprises a transistor MC5 whose gate receives the voltage V ref . Its drain is connected to two switches S1 and S2 controlled by the sequencer 6.
  • the switch S1 receives the reference current I ref from the reference generator 3A.
  • Switch S2 is connected to the common point of an AC capacitor and an AA amplifier. The output of the latter is connected to the wells of the transistors MC5 and MU (2A-n).
  • the transistor useful can continue to function whether it is in operation adjustment or not.
  • the useful components do not are not transistors, but diodes or photodiodes, the latter being, for example, part a network of detectors or the like. It can then be important that all these diodes have the same current of flight. However, we know that the leakage current of a diode is strongly dependent on temperature.
  • the central reference generator 3B generates, for example by means of the assembly shown in FIG. 3 at 3A, a reference current I ref which is distributed to the local adjustment cells such as cell 5B-n, by means of the sequencer 6 .
  • the local adjustment cell 5B-n comprises a diode P1 which is connected to the switches S1 and S2, these being closed in adjustment mode.
  • Switch S2 is also connected to the common point of a capacitor CB and the input of an amplifier AB.
  • the output of the latter is connected to a heat dissipation resistor RT placed near the diode P1 and the useful diode P2 (2B-n).
  • a current I C is therefore sent as an adjustment value in this dissipating resistor RT.
  • Diode P2 (and possibly other diodes located nearby) will thus receive (have) a caloric intake which determines the same leakage current for all the diodes.
  • the current flows through the dissipating resistor RT as long as the current in the diode P1 is not equal to the reference current I ref .
  • the sequencer 6 makes it possible to serve other similar heating assemblies distributed in the array of photodiodes.
  • the local adjustment units must be thermally isolated from each other.
  • the CB capacitor acts as memory and retains the setpoint between two addresses made by the sequencer 6.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Semiconductor Integrated Circuits (AREA)

Claims (12)

  1. Integrierte Schaltung, dadurch gekennzeichnet, daß sie aufweist:
    Mittel, die einen zentralen Referenzgenerator (3, 3A, 3B) bilden, der dazu dient, mindestens eine Sollwertinformation (VG1, VG2; Iref, Vref; Iref) zu ermitteln, die die Betriebseigenschaft bestimmt, welche mindestens einer Anzahl von Bauelementen der Schaltung gemeinsam werden soll;
    Mittel (4-1 bis 4-n; 6) zum Verteilen der Sollwertinformation unter mindestens einer Anzahl von Einheiten der Schaltung, die jeweils mindestens eines der besagten Bauelemente (2-n; 2A-n; 2B-n) aufweisen;
    wobei jede der Einheiten lokale Justiermittel (5-n; 5A-n; 5B-n) aufweist, die so angeschlossen sind, daß sie die Sollwertinformation (VG1, VG2; Iref, Vref; Iref) empfangen und einen Justierwert (VW, IC) ermitteln;
    Korrekturmittel (C, A; CA, AA; Cb, AB) in jeder Einheit zum Justieren der Betriebseigenschaft einer in den lokalen Justiermitteln (5-n; 5A-n; 5B-n) vorgesehenen Vorrichtung (MC1, MC2; MC5; P1) in Abhängigkeit von dem Justierwert, wobei diese Vorrichtung in der Nähe des Bauelementes oder der Bauelemente angeordnet und so ausgelegt ist, daß die Betriebseigenschaft, die ihr auf diese Weise aufgeprägt wird, in der gleichen Weise dem Bauelement bzw. den Bauelementen (2-n; 2A-n; 2B-n) aufgeprägt wird.
  2. Integrierte Schaltung nach Anspruch 1 mit MOS-Transistoren, dadurch gekennzeichnet, daß die Betriebseigenschaft die scheinbare Schwellwertspannung (VTA) mindestens einiger bestimmter ihrer MOS-Transistoren (2-1 bis 2-n; Figur 2) ist.
  3. Integrierte Schaltung nach Anspruch 1 mit MOS-Transistoren, dadurch gekennzeichnet, daß die Betriebseigenschaft ein vorgegebener Arbeitspunkt der Kurve des/der Drainstrom/Gatespannung mindestens einiger bestimmter dieser MOS-Transistoren (2A-n; Figur 3) ist.
  4. Integrierte Schaltung nach Anspruch 2 mit Dioden oder Photodioden, dadurch gekennzeichnet, daß die Betriebseigenschaft der Leckstrom der Dioden (P2; Figur 4) ist.
  5. Integrierte Schaltung nach einem der Ansprüche 2 und 3, zusammengenommen, dadurch gekennzeichnet, daß der Justierwert die Topfspannung (VW) mindestens einiger bestimmter der MOS-Transistoren (2-1 bis 2-n) ist.
  6. Integrierte Schaltung nach den Ansprüchen 2 und 5, zusammengenommen, dadurch gekennzeichnet, daß der zentrale Referenzgenerator (3) aufweist: Mittel (MG2, MG4) zum Erstellen eines ersten Verhältnisses zweier Ströme (KM), das den Wert der erwünschten scheinbaren Schwellwertspannung (VTA) darstellt, und Mittel (MG1, MG2) zum Umwandeln dieses ersten Stromverhältnisses in ein die Sollwertinformation bildendes Spannungspaar (VG1, VG2) in Abhängigkeit von einem vorgegebenen Topfspannungswert (VGW), und daß die lokalen Justiermittel (5-1 bis 5-n) aufweisen: Mittel (MC3, MC4) zum lokalen Erstellen eines zweiten Stromverhältnisses und Mittel (MC1, MC2, C, A) zum Erzeugen, in Abhängigkeit von der Sollwertinformation, eines Signals zum Modifizieren der Topfspannung (VUW) des Bauelementes oder der Bauelemente (2-1 bis 2-n), die den betrachteten lokalen Justiermitteln (5-1 bis 5-n) zugeordnet sind, um das zweite Stromverhältnis an das erste Stromverhältnis anzupassen.
  7. Integrierte Schaltung nach Anspruch 6, dadurch gekennzeichnet, daß
    der zentrale Referenzgenerator (3) einen Stromspiegel enthält, der von zwei MOS-Transistoren, deren Betriebsbereich das erste Stromverhältnis umfaßt, und zwei weiteren MOS-Transistoren (MC1, MC2) gebildet wird, die mit den Transistoren des Stromspiegel in Reihe geschaltet sind und deren Topfspannung (VGW) den vorgegebenen Topfspannungswert bildet, wobei die beiden weiteren Transistoren (MG1, MG2) so ausgebildet sind, daß sie mit starker Inversion arbeiten und die Sollwertinformation (VG1, VG2) an ihren Gates abgeben, und daß
    die lokalen Justiermittel (5-1 bis 5-n) einen Aufbau haben, der mit dem des zentralen Referenzgenerators (3) identisch ist, wobei der Knotenpunkt zwischen dem einen (MC4) der Transistoren ihres Stromspiegels und dem entsprechenden weiteren Transistor (MC2) an einem Verstärker (A) angeschlossen ist, der den Justierwert (VUW) liefert, wobei der Ausgang dieses Verstärkers an den Basen der weiteren Transistoren (MC1, MC2) dieser lokalen Justiermittel und an derjenigen des diesen Mitteln zugeordneten Bauelementes (MU) angeschlossen ist.
  8. Integrierte Schaltung nach Anspruch 3 und 5, zusammengenommen, dadurch gekennzeichnet, daß der zentrale Referenzgenerator (3A) eine Spannungsquelle (ST), die eine Referenzspannung (Vref) abgibt, und eine Stromquelle (MG5, MG6 und MG7), die einen Referenzstrom (Iref) abgibt, aufweist, und daß die lokalen Justiermitte (5A-n) aufweisen: einen Transistor (MC5), der so angeschlossen ist, daß er die Referenzspannung an seinem Gate empfängt, und einen Verstärker (AA), der so angeschlossen ist, daß er die Differenz zwischen dem Referenzstrom und dem diesen Transistor (MC5) durchfließenden Strom verstärkt, wobei der Ausgang des Verstärkers (AA) an dem Topf des letzteren und an der des besagten Bauelementes (MU) angeschlossen ist, um an sie den Justierwert (VW) abzugeben.
  9. Integrierte Schaltung nach Anspruch 8, dadurch gekennzeichnet, daß sie eine Folgesteuerung (6) aufweist, um den Referenzstrom (Iref) nacheinander den lokalen Justiermitteln zuzuführen, und daß die lokalen Justiermittel Speichermittel (CA) zum Speichern des Justierwertes (VW) zwischen zwei Abgaben des Referenzstromes an diese Mittel aufweisen.
  10. Integrierte Schaltung nach Anspruch 4, dadurch gekennzeichnet, daß der Justierwert die Temperatur (T) der Schaltung ist.
  11. Integrierte Schaltung nach Anspruch 10, dadurch gekennzeichnet, daß der zentrale Referenzgenerator (3B) eine Referenzstromquelle (Iref) aufweist und daß die lokalen Justiermittel eine Referenzdiode (P1) sowie einen Verstärker (AB) zum Verstärken der Differenz zwischen dem Referenzstrom und dem in dieser Diode (P1) fließenden Strom aufweisen, wobei der Ausgang (AB) an einem Wärmeableitelement (RT) angeschlossen ist, das in der Nähe der besagten Diode (P1) und der das Bauelement bildenden Diode (P2) angeordnet ist.
  12. Integrierte Schaltung nach Anspruch 11, dadurch gekennzeichnet, daß sie eine Folgeschaltung (6) zum aufeinanderfolgenden Zuführen des Referenzstromes (Iref) zu den lokalen Justiermitteln (5B-n) aufweist.
EP96401074A 1995-05-17 1996-05-15 Integrierte Schaltung in der einige Bauelemente mit dem selben Betriebsverhalten arbeiten sollen Expired - Lifetime EP0743586B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR9505920A FR2734378B1 (fr) 1995-05-17 1995-05-17 Circuit integre dans lequel certains composants fonctionnels sont amenes a travailler avec une meme caracteristique de fonctionnement
FR9505920 1995-05-17

Publications (2)

Publication Number Publication Date
EP0743586A1 EP0743586A1 (de) 1996-11-20
EP0743586B1 true EP0743586B1 (de) 2000-08-02

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US (1) US5739718A (de)
EP (1) EP0743586B1 (de)
DE (1) DE69609563D1 (de)
FR (1) FR2734378B1 (de)

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JP3635768B2 (ja) * 1996-03-05 2005-04-06 ヤマハ株式会社 半導体集積回路
JPH10135756A (ja) * 1996-10-31 1998-05-22 Mitsumi Electric Co Ltd 回路体における回路特性の調整方法
US20040217934A1 (en) * 2003-04-30 2004-11-04 Jin-Seok Yang Driving circuit of flat panel display device
US6972989B2 (en) * 2003-10-10 2005-12-06 Infincon Technologies Ag Reference current distribution in MRAM devices
FR2957161B1 (fr) * 2010-03-02 2012-11-16 St Microelectronics Rousset Circuit interne de tension d'alimentation d'un circuit integre

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NL8001558A (nl) * 1980-03-17 1981-10-16 Philips Nv Stroomstabilisator opgebouwd met veldeffekttransistor van het verrijkingstype.
US4471292A (en) * 1982-11-10 1984-09-11 Texas Instruments Incorporated MOS Current mirror with high impedance output
US4814644A (en) * 1985-01-29 1989-03-21 K. Ushiku & Co. Basic circuitry particularly for construction of multivalued logic systems
DE68921020T2 (de) * 1988-05-20 1995-06-29 Mitsubishi Electric Corp Integrierte MOS-Schaltung zum Steuern von lichtermittierenden Dioden.
NL9001018A (nl) * 1990-04-27 1991-11-18 Philips Nv Referentiegenerator.
US5117130A (en) * 1990-06-01 1992-05-26 At&T Bell Laboratories Integrated circuits which compensate for local conditions
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US5461338A (en) * 1992-04-17 1995-10-24 Nec Corporation Semiconductor integrated circuit incorporated with substrate bias control circuit
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GB9320991D0 (en) * 1993-10-12 1993-12-01 Philips Electronics Uk Ltd A circuit for providing a current source
FR2717918B1 (fr) * 1994-03-25 1996-05-24 Suisse Electronique Microtech Circuit pour contrôler les tensions entre caisson et sources des transistors mos et système d'asservissement du rapport entre les courants dynamique et statique d'un circuit logique mos.

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FR2734378A1 (fr) 1996-11-22
EP0743586A1 (de) 1996-11-20
FR2734378B1 (fr) 1997-07-04
US5739718A (en) 1998-04-14
DE69609563D1 (de) 2000-09-07

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