EP0687967A1 - Temperature stable current source - Google Patents

Abstract

In order to make the current (I0) insensitive to temperature, a first and a second MOS transistors (N0, N1) supplied by a current mirror (1) have their sources connected to ground (Vss), the drain (a ) and the gate of the first transistor (N0) being connected to the gate (b) of the second transistor (N1) via a resistor (R). The quotient of the dimensional ratios of the transistors (N0, N1) is equal to the coefficient (β) of the current mirror (1) and the transistors (N0, N1) are doped so that the threshold of the second transistor (N1) is greater than that of the first (N0) .Application in particular to ramp generators for the programming of EEPROM cells.

Description

The invention lies in the field of electronic circuits using field effect transistors with insulated gates to produce current sources. These circuits use the so-called "MOS" technology and generally are in the form or form part of integrated circuits. The invention relates more precisely to current sources of this type which are designed to exhibit a certain immunity to temperature variations.

In general, current sources find many applications in electronics. They are used in particular for the production of calibrated ramp signal generators. For this, the current source supplies a capacitor whose voltage provides the ramp signal.

The ramp generators are for example used for programming or erasing memory cells constituting the electrically erasable programmable memories (EEPROM).

A known arrangement in MOS technology for producing a current source consists in using two current mirrors using respectively p-channel MOS transistors (PMOS) and n (NMOS), the NMOS transistors having different threshold values (see diagram of figure 1). It can be shown that the currents flowing in the branches of this circuit are approximately proportional to the mobility of the NMOS transistors and to the square of the difference from their threshold values. It follows that the currents are in fact very dependent on the temperature because the mobility as well as the square of the difference of the threshold values vary very strongly according to the temperature.

The problem of temperature stabilization of electronic circuits in general is known per se but usually leads to a complication of the circuits and an increase in their consumption.

Also, the invention aims to provide a simple and effective solution to this problem in the case of current sources.

For this purpose, the invention relates to a current source characterized in that it comprises a current mirror intended to supply a first current proportional to a second current in a given ratio, a first and a second transistors with effect of fields with isolated gates whose sources are connected to a first common potential, the drain and the gate of the first transistor being connected to the gate of the second transistor by means of a resistor, in that said second current supplies the channel directly of said second transistor, in that said first current supplies the channel of said first transistor via said resistor, in that said first and second transistors are doped so that the conduction threshold of the second transistor is higher than that of the first transistor and in that the dimensional ratio of a transistor being defined as the ratio of the width to the length of its gate, the first and second transistors are dimensioned so that the dimensional ratio of the first transistor is proportional to that of the second transistor in said given ratio.

This structure has the effect of imposing on the terminals of the resistor a potential difference equal to the difference of the threshold values of the first and second transistors. The current is therefore proportional to this difference and no longer to its square. In addition, the difference in threshold values is not very dependent on temperature variations. As a result, the current will also be little dependent on these variations.

Furthermore, the calculation shows that the difference in threshold values is approximately proportional to the absolute temperature. We also know that a resistance produced by diffusion with low doping is also proportional to the absolute temperature. Also, according to an additional characteristic of the invention which is particularly advantageous in the case of an integrated embodiment, the resistance is produced by diffusion or implantation of impurities in the substrate of the integrated circuit with a sufficiently low doping so that the value of the resistance varies linearly with temperature.

The choice of a lightly doped diffused resistance does not however make it possible to produce a resistance which is not very bulky and has a very high value, which implies that the current flowing therein cannot be as low as one would like. Also, in order to compensate for this constraint, the ratio between the first and the second current will advantageously be chosen greater than unity.

According to a particular embodiment of the invention, the current source is characterized in that said first and second transistors are n-channel MOS transistors and in that said current mirror is produced by means of third and fourth MOS transistors p channel having their gates connected together and their sources connected to a second potential greater than said first potential, said third transistor being mounted as a diode, said third and fourth transistors being provided to supply said first and second currents respectively in said given ratio.

According to another aspect, the dimensional ratio of the third transistor will be chosen proportional to that of the fourth transistor in said given ratio.

In order to provide the previous assembly with a certain tolerance for fluctuations in supply voltages, the invention further provides that said current mirror comprises a component having a high dynamic resistance compared to the value of said resistance, said component being connected. between the drain of the third transistor and the gate of the second transistor.

According to a particularly advantageous embodiment, said component is a fifth n-channel MOS transistor, the drain of which is connected to the drain of said third transistor, the source of which is connected to the gate of the second transistor and the gate of which is connected to the drain of the second transistor.

In addition to its role of absorbing fluctuations in supply voltages, the fifth transistor mounted in the manner indicated has the advantageous property of ensuring the state of saturation of the second transistor, independently of the supply voltage.

• La figure 1 représente le schéma d'une source de courant selon l'état de la technique.
• La figure 2 représente le schéma de la source de courant selon l'invention.
• La figure 3 représente un mode de réalisation préférentiel de l'invention.
• La figure 4 représente une variante du schéma de la figure 3.
• La figure 5 représente le montage dual du schéma de la figure 3.

Other aspects of embodiment and advantages of the invention will appear in the following description with reference to the figures.

• FIG. 1 represents the diagram of a current source according to the state of the art.
• FIG. 2 represents the diagram of the current source according to the invention.
• FIG. 3 represents a preferred embodiment of the invention.
• FIG. 4 represents a variant of the diagram of FIG. 3.
• FIG. 5 represents the dual assembly of the diagram of FIG. 3.

FIG. 1 represents a known diagram of a current source. It consists of a current mirror 1 formed by two p-channel MOS transistors PM0 and PM1 respectively supplying the currents J0 and J1 to the n-channel MOS transistors NM0 and NM1, the sources of which are connected to a common potential Vss which can be for example the mass of the circuit and the gates of which are connected together. One of the NM1 transistors is mounted as a diode and is doped so as to have a higher threshold than the second NM0 transistor. The NM0 transistor will be for example a native transistor, that is to say whose channel has the same p-type doping as the substrate, having a threshold of about 0.2 volts while the NM1 transistor is enriched by implantation. boron in the substrate so as to give it a threshold of about 0.8 volts.

To supply a load Z at constant current, a second current mirror can be formed by means of a fourth transistor NM2 whose source is connected to the potential Vss and whose gate is connected to the drain of the transistor NM1. The load Z is placed between the drain of the transistor NM2 and the potential Vdd greater than Vss.

The circuit transistors are all polarized so as to operate in saturated mode. The dimensional ratios of the transistors PM0 and PM1 impose the ratio β = J0 / J1 of the currents J0 and J1 flowing respectively in these transistors. Likewise, the dimensional ratios of the transistors NM1 and NM2 of the second current mirror fix the ratio J1 / J2, where J2 is the current flowing in the load Z.

où VT0 et VT1 sont respectivement les valeurs de seuil des transistors NM0 et NM1, k étant un coefficient dépendant des mobilités des transistors du montage.We can show that we have as a first approximation: $$\text{J1 = k (VT1-VT0) ²}$$

where VT0 and VT1 are respectively the threshold values of the transistors NM0 and NM1, k being a coefficient dependent on the mobilities of the transistors of the circuit.

As these mobilities as well as the term (VT1-VT0) ² depend appreciably on the temperature, the current which results from it will also be strongly dependent.

FIG. 2 represents the diagram of a current source in accordance with the invention. The source comprises a current mirror 1 of ratio β providing the currents I0 and I1 according to the relation I0 = βI1. The current I1 feeds the drain d of an N-channel MOS transistor N1 whose source is connected to the potential Vss. The current I0 feeds the drain a of another N-channel MOS transistor N0 via a resistor R. The transistor N0 is mounted as a diode and therefore has its gate connected to its drain a. The gate of the transistor N1 is connected to the connection point b of the resistor R to the current mirror 1. As for the assembly of FIG. 1, the load Z is placed in series with another n-channel MOS transistor N3 whose gate is connected to the drain a of transistor N0 so as to form a current mirror.

The transistors N0 and N1 are doped differently so that the threshold VT1 of the transistor N1 is higher than that VT0 of the transistor N0. The transistor N0 is for example a native transistor and the transistor N1 is said to be "enriched" thanks to additional p-type doping of the channel.

$$\text{I1 = k1(W1/L1)(Vb-VT1) ²}$$

où :

• k1 et k2 dépendent de la mobilité des électrons et de la capacité des grilles par unité de surface,
• W0/L0 et W1/L1 sont les rapports dimensionnels (rapport de la largeur à la longueur) des grilles des transistors N0 et N1,
• Va et Vb sont les potentiels de grille des transistors N0 et N1.

Assuming that transistor N1 is polarized in saturated regime, we can write as a first approximation: $$\text{I0 = k0 (W0 / L0) (Va-VT0) ²}$$

$$\text{I1 = k1 (W1 / L1) (Vb-VT1) ²}$$

or :

• k1 and k2 depend on the mobility of the electrons and the capacity of the grids per unit area,
• W0 / L0 and W1 / L1 are the dimensional ratios (ratio of the width to the length) of the gates of the transistors N0 and N1,
• Va and Vb are the gate potentials of transistors N0 and N1.

As k1 and k2 are practically independent of doping, we have k1 = k2.

on en déduit : $$\text{Vb-Va = VT1-VT0 = R.I0}$$

As on the other hand I0 = βI1, if we size the transistors N0 and N1 so as to have: $$\text{W0 / L0 = β (W1 / L1)}$$

we can deduce : $$\text{Vb-Va = VT1-VT0 = R.I0}$$

Thus, the voltage across the resistor R is equal to the difference of the threshold values VT1 and VT0 transistors N1 and N0. The current I0 therefore depends on this difference and on the value of the resistance R but no longer depends on the mobilities.

où :
   K = constante de Planck
   T = température absolue
   q = charge de l'électron
   ln = logarithme népérien
   Ni = dopage intrinsèque
   N = dopage du substrat
   ε = coefficient de capacité du silicium
   Cox = capacité de grille par unité de surfaceIn order to assess the dependence of the current on temperature variations, it is necessary to calculate the threshold values VT1 and VT0 as well as their difference in a particular case. The threshold value VT of an NMOS transistor is given by the equation: $${\text{VT = (2KT / q) ln (N / Ni) + [4εNKT.ln (N / Ni)]}}^{\text{½}}\text{(1 / Cox)}$$

or :
K = Planck constant
T = absolute temperature
q = electron charge
ln = natural logarithm
Ni = intrinsic doping
N = doping of the substrate
ε = capacity coefficient of silicon
Beetle = grid capacity per unit area

avec :
A = (2K/q)ln(Ne/Nnat)
B=(4εK)^½[[Ne.ln(Ne/Ni)]^½-[Nnat.ln(Nnat/ni)]^½](1/Cox)With N = Ne for transistor N1 and N = Nnat for transistor N0, we deduce: $${\text{VT1-VT0 = AT + BT}}^{\text{½}}\text{,}$$

with:
A = (2K / q) ln (Ne / Nnat)
B = (4εK) ^½ [[Ne.ln (Ne / Ni)] ^½ - [Nnat.ln (Nnat / ni)] ^½ ] (1 / Cox)

With conventional technology, we will have for example:
Ne = 10²³ / m³
Nnat = 10²¹ / m³
Ni = 1.45 10¹⁶ / m³
Beetle = 2.7 10⁻³ F / m²,
we then obtain:
A = 1.58 10⁻³ V / K
B = 2.8 10⁻¹⁷ V / (K) ^½

It can be seen that VT1-VT0 is practically proportional to the absolute temperature T and is not very sensitive to its variations.

avec :
l = longueur de la résistance
S = section de la résistance
N = dopage
Dn = coefficient de diffusion.Resistor R can be made of polysilicon and will therefore have the property of being little dependent on temperature and variations in the parameters of the manufacturing process. However, it has the disadvantage of requiring a large surface. Another solution consists in using a diffused resistance obtained by diffusion or implantation of n-type impurities in the p-type substrate. In the case of a weak doping and for a given temperature range, the value of a diffused resistance is given by the relation: $$\text{R = (lK / SqN.Dn) T}$$

with:
l = resistance length
S = resistance section
N = doping
Dn = diffusion coefficient.

It can then be seen that the value of the resistance R is practically proportional to the absolute temperature T. As the voltage applied to its terminals is itself proportional to the absolute temperature, the current I0 is therefore practically independent of the temperature.

Of course, this result remains valid provided that the transistor N1 operates in saturated mode and if the transistor N0 is conductive, which will always be the case if the supply potential Vdd is sufficiently high compared to the threshold voltages of these transistors and if the static impedance of current mirror 1 is not very high.

The circuit of FIG. 3 shows in detail a possible and particularly simple embodiment of the current mirror 1. The mirror 1 is produced by means of two p-channel MOS transistors P0, P1 having their gates connected together and their sources connected to a supply potential Vdd greater than the potential Vss. The transistor P0 is mounted as a diode thanks to the connection between its drain c and its gate.

où W'0 et W'1 sont les largeurs effectives de grille respectivement des transistors P0 et P1 et L'0 et L'1 leurs longueurs effectives de grille.The ratio of the currents I0 / I1 flowing in these transistors is imposed by the quotient of their dimensional ratio. We will therefore have: $$\text{β = (W'0 / L'0) / (W'1 / L'1)}$$

where W'0 and W'1 are the effective gate widths of the transistors P0 and P1 and L'0 and L'1 respectively their effective gate lengths.

For β to be independent of the voltages applied to the transistors, it is desirable however that the depleted areas at the ends of the gates are negligible compared to the lengths of the gates. This condition will be satisfied by choosing gate lengths greater than approximately 4 µm.

This result will of course only be obtained on condition that the supply voltage Vdd is sufficient for the transistor P1 to operate in saturated state and that the voltage across the terminals of the transistors P0 is greater in absolute value than its threshold value.

In order to make the circuit less sensitive to variations in supply voltage, there is provided a third n channel MOS transistor N2 having its drain connected to the drain c of the transistor P0, its source connected to the gate of the transistor N1 and its gate connected to the drain of transistor N1. The transistor N2 thus arranged has the effect of ensuring the operation in saturated state of the transistor N1. Furthermore, if the supply potential Vdd is sufficiently high relative to the voltage drops of the drain-source paths of the transistors, the transistors N2 and P1 are biased in saturated state. The transistor N2 in saturated state then has a high dynamic impedance which has the effect of absorbing voltage variations feed. The circuit is therefore both stable in temperature and in supply voltage.

Advantageously, a lightly doped transistor, for example a native transistor, will be chosen for N2, so that it has a low threshold voltage, thus facilitating its polarization in saturated conditions.

In practice, the saturation condition of all the transistors is that the supply voltage is greater than the sum of the threshold voltages of the transistors which make up each branch of the circuit.

Furthermore, the transistors P0, P1 as well as N2 will preferably be dimensioned so as to have the lowest possible static impedance in order to allow correct operation for low values of the supply voltage.

The precise choice of the parameters of the circuit will of course depend on the envisaged application. It should however be noted that the choice of a slightly doped and not very large diffused resistance does not allow a very low current I0 (for example of 30 µA for R = 20 kΩ with VT1 = 0.8 volt and VT0 = 0.2 volts). It will therefore be advantageous to choose β greater than 1 (for example equal to 10) so as to reduce consumption in the right branch of the assembly.

The invention cannot be limited to the particular embodiment which has just been described. Many variants are in fact within the reach of those skilled in the art. So as shown in the figure 4, the transistor P1 can be mounted as a diode in place of the transistor P0. Similarly, the circuit of FIG. 3 can be transformed into its dual circuit as shown in FIG. 5. Finally, the transistor N2 could be replaced by a component of another type having a high dynamic impedance.

Claims (9)

Current source characterized in that it comprises a current mirror (1) designed to supply a first current (I0) proportional to a second current (I1) in a given ratio (β), first and second effect transistors fields with isolated gates (N0, N1) whose sources are connected to a first common potential (Vss), the drain and the gate (a) of the first transistor (N0) being connected to the gate (b) of the second transistor ( N1) by means of a resistor (R), in that said second current (I1) directly feeds the channel of said second transistor (N1), in that said first current (I0) feeds the channel of said first transistor ( N0) by means of said resistor (R), in that said first and second transistors (N0, N1) are doped so that the conduction threshold (VT1) of the second transistor (N1) is greater than that (VT0) of the first transistor (N0) and in that, the dimensional ratio of a transistor being defined i as the ratio of the width to the length of its gate, the first and second transistors (N0, N1) are dimensioned so that the dimensional ratio of the first transistor (N0) is proportional to that of the second transistor (N1) in said given ratio (β). Current source according to claim 1, characterized in that it forms part of an integrated circuit and in that said resistance (R) is produced by diffusion or implantation of impurities in the substrate of the integrated circuit with sufficiently doping low so that the value of said resistance (R) varies linearly as a function of temperature. Current source according to claim 2, characterized in that said given ratio (β) is greater than unity. Current source according to one of Claims 1 to 3, characterized in that the said first and second transistors (N0, N1) are n-channel MOS transistors and in that the said current mirror (1) is produced by means of third and fourth p-channel MOS transistors (P0, P1) having their gates connected to each other and their sources connected to a second potential (Vdd) greater than said first potential (Vss), said third transistor (P0) being mounted as a diode, said said third and fourth transistors (P0, P1) being provided to respectively supply said first and second currents (I0, I1) in said given ratio (β). Current source according to claim 4, characterized in that the dimensional ratio of said third transistor (P0) is proportional to that of the fourth transistor (P1) in said given ratio (β). Current source according to claim 4 or 5, characterized in that said current mirror (1) comprises a component (N2) having a high dynamic resistance compared to the value of said resistance (R), said component (N2) being connected between the drain (c) of the third transistor (P0) and the gate (b) of the second transistor (N1). Current source according to claim 6, characterized in that said component (N2) is a fifth n-channel MOS transistor, the drain of which is connected to the drain (c) of said third transistor (P0), the source of which is connected to the gate (b) of the second transistor (N1) and the gate of which is connected to the drain (d) of the second transistor (N1). Current source according to claim 7, characterized in that said fifth transistor (N2) is designed to have a threshold value (VT2) lower than that (VT1) of the second transistor (N1). Current source according to one of claims 4 to 8, characterized in that said third and fourth transistors (P0, P1) each have a gate length at least equal to 4 µm.

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