EP0686940A1 - Bildverarbeitungssystem - Google Patents

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Publication number
EP0686940A1
EP0686940A1 EP95108978A EP95108978A EP0686940A1 EP 0686940 A1 EP0686940 A1 EP 0686940A1 EP 95108978 A EP95108978 A EP 95108978A EP 95108978 A EP95108978 A EP 95108978A EP 0686940 A1 EP0686940 A1 EP 0686940A1
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EP
European Patent Office
Prior art keywords
component
discrete cosine
cosine transform
transform coefficients
image
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EP95108978A
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English (en)
French (fr)
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EP0686940B1 (de
Inventor
Masanori Kurata
Ryusuke 16 Toshiba Higashi-Terao Dai 2 Murakami
Yusei Itaya
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Toshiba Corp
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Toshiba Corp
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T3/00—Geometric image transformations in the plane of the image
    • G06T3/40—Scaling of whole images or parts thereof, e.g. expanding or contracting
    • G06T3/4084—Scaling of whole images or parts thereof, e.g. expanding or contracting in the transform domain, e.g. fast Fourier transform [FFT] domain scaling

Definitions

  • the present invention relates to an image processing system, and more specifically to an image processing system provided with a video effect processing function in addition to an image compressing function for executing discrete cosine transform or to an image decompressing function for executing inverse discrete cosine transform.
  • Fig. 1 is a block diagram showing an example of the image processing system which can execute the video effect processing for an analog video signal.
  • an image signal outputted from an image reproduce section 31 is converted into digital image signals through an analog/digital converter 32, and then inputted to a video effect processing section 33.
  • a RAM (Random Access Memory) 34 stores various processing data required to execute the video effect processing for the digital image signals in the form of tables.
  • the video effect processing section 33 retrieves necessary processing data corresponding to the inputted digital image signals from the RAM 34 and transforms the digital image signals on the basis of the retrieved processing data to execute the video effect processing (i.e., mosaic-image-processing, monochromatic-image-processing, thermographic-image-processing, etc.).
  • the processed image signals are converted again into an analog signal through a digital/analog converter 35, and then displayed on a display unit 36.
  • Fig. 2 is a block diagram showing another example of the image processing system which can execute the video effect processing for digital video signals (as used in a personal computer, for instance).
  • digital image signals outputted from an image reproduce section 41 are inputted to a video effect processing section 42.
  • a RAM (Random Access Memory) 43 stores various processing data required to execute the effect processing for the digital image signals in the form of tables. Therefore, the video effect processing section 42 retrieves necessary processing data corresponding to the inputted digital image signals from the RAM 43, and executes the video effect processing for the digital image signals on the basis of the retrieved data, in the same way as with the case of the image processing system shown in Fig. 1.
  • the processed digital image signals are converted again into an analog signal through a digital/analog converter 44, and then displayed on a display unit 45.
  • an image processing system which can execute various video effect processing may be required more and more in addition to the mosaic image processing, monochromatic image processing, etc.
  • the conventional image processing system is constructed so as to execute a plurality of video effect processing, since the amount of the processing data required to transform image signals further increases, the circuit scale increases extraordinarily.
  • an image processing system for compacting the circuit scale is disclosed in Japanese Published Unexamined (Kokai) Patent Application No. 4-315371.
  • some additional image processing such as edge emphasis or smoothing processing is provided for an image compressing system for executing the discrete cosine transform or for an image decompressing system for executing the inverse discrete cosine transform.
  • the quantization coefficients are modified in such a way that predetermined image processing can be executed whenever the discrete cosine transform coefficients outputted by the image compressing system are quantized or whenever the discrete cosine transform coefficients inputted to the image decompressing system are quantized inversely.
  • a memory for storing the processing data is not needed, with the result that it is possible to reduce the circuit scale to that extent.
  • the present invention provides an image processing system having an inverse quantizing section for inversely quantizing inputted discrete cosine transform coefficients, an inverse discrete cosine transforming section for inversely discrete cosine transforming obtained inversely quantized discrete cosine transform coefficients and a digital-to-analog converting section for converting obtained inverse discrete cosine transform coefficients, comprising: dc component processing means for multiplying a dc component of the inversely quantized discrete cosine transform coefficients by a constant h other than zero; and ac component processing means for replacing an ac component of the inversely quantized discrete cosine transform coefficients with zero, wherein the inversely quantized discrete cosine transform coefficients outputted from the dc and ac component processing means and thus processed by mosaic-image-processing are inputted to the inverse discrete cosine transforming section.
  • the present invention provides an image processing system having an inverse quantizing section for inversely quantizing inputted discrete cosine transform coefficients, an inverse discrete cosine transforming section for inversely discrete cosine transforming obtained inversely quantized discrete cosine transform coefficients and a digital-to-analog converting section for converting obtained inverse discrete cosine transform coefficients, comprising: luminance dc component processing means for multiplying a dc component D y of a luminance block Y of the inversely quantized discrete cosine transform coefficients by a constant i other than zero; luminance ac component processing means for multiplying an ac component A y of the luminance block Y by a constant I other than zero; chrominance dc component processing means for replacing dc components D Cb and D Cr of chrominance blocks Cb and Cr of the inversely quantized discrete cosine transform coefficients with constants j and k
  • the present invention provides an image processing method comprising the steps of: inversely quantizing inputted discrete cosine transform coefficients; multiplying a dc component of obtained inversely quantized discrete cosine transform coefficients by a constant h other than zero and replacing an ac component of the inversely quantized discrete cosine transform coefficients with zero, thus applying mosaic-image-processing to the inversely quantized discrete cosine transform coefficients; inversely discrete cosine transforming the inversely quantized discrete cosine transform coefficients thus applied the mosaic-image-processing; and converting obtained inverse discrete cosine transform coefficients to analog signals.
  • the present invention provides an image processing method comprising the steps of: inversely quantizing inputted discrete cosine transform coefficients; multiplying a dc component D y of a luminance block Y of obtained inversely quantized discrete cosine transform coefficients by a constant i other than zero, multiplying an ac component A y of the luminance block Y by a constant I other than zero, replacing dc components D cb and D cr of chrominance blocks C b and C r of the inversely quantized discrete cosine transform coefficients with constants j and k and replacing ac components A cb and A cr of the chrominance blocks C b and C r with constants J and K, thus applying monochromatic-image-processing to the inversely quantized discrete cosine transform coefficients; inversely discrete cosine transforming the inversely quantized discrete cosine transform coefficients thus applied the monochromatic-image-processing; and converting obtained inverse discrete cos
  • Fig. 3 is a schematic block diagram showing the structure of the image processing system according to the present invention.
  • discrete cosine transform image information that is, discrete cosine transform coefficients are outputted from an image reproduce section 11.
  • the output signals of the image reproduce section 11 are inversely quantized by an IQ (inverse quantize) section 12.
  • the inversely quantized signals are supplied to a video effect processing section 13 that executes the video effect processing (mosaic-image-processing, monochromatic-image-processing, or thermographic-image-processing, etc.) selected on the basis of a select signal (not shown).
  • the output signals of the video effect processing section 13 are transformed inversely by an IDCT (inverse discrete cosine transform) section 14, and further motion-compensated for by an MC (motion compensate) section 15.
  • the output of the MC section 15 is converted into an analog signal by a digital/analog converter 16, and then displayed on a display unit 17.
  • the discrete cosine transform coefficients are composed of three coefficients of a luminance coefficient Y, and two chrominance coefficients Cb and Cr.
  • the inverse discrete cosine transform is executed for these three sorts of coefficients Y, Cb and Cr for each block unit of 8 x 8 pixels.
  • a block composed of luminance coefficients Y is referred to as a luminance block Y
  • a block composed of chrominance coefficients Cb is referred to as a chrominance block Cb
  • a block composed of chrominance coefficients Cr is referred to as a chrominance block Cr, respectively.
  • the luminance block Y has a single-unit of dc component D y and 63-units of ac components A y .
  • the chrominance difference block Cb or Cr has a single-unit of dc component D Cb or D Cr and 63-units of ac components A Cb or A Cr , respectively.
  • the video effect processing section 13 will be described in more detail hereinbelow.
  • the respective dc components D y , D Cb and D Cr of the respective blocks Y, Cb and Cr for forming the discrete cosine transform coefficients are multiplied by h (a constant other than zero) to form the dc components D y ', D Cb ' and D Cr ' of the output signals.
  • the respective ac components A y , A Cb and A Cr of the respective blocks Y, Cb and Cr are replaced with zero to form the ac components A y ', A Cb ' and A Cr ' of the output signals.
  • the above-mentioned arithmetic processing can be obtained by executing the following matrix operations (4) and (5): where h ⁇ 0
  • D1 and A1 denote dummy variables, respectively. These dummy variables are not outputted to the IDCT section 14.
  • the reason why these dummy variables are used is that a matrix of four-rows and four-columns is used as the determinant. Further, the reason why the matrix of four-rows and four-columns is used as the determinant is that a four-row four-column determinant is required to be used in the thermographic-image-processing (as described later). If considered is only the mosaic-image-processing, it is available to use a matrix of at least three-rows and three-columns.
  • Figs. 4 and 5 show examples of the circuit (hardware) constructions for executing the arithmetic processing as expressed by the formulae (4) and (5).
  • dc components D y , D cb and D cr are inputted in sequence through an input A of a selector 131. These dc components are also inputted in sequence to a multiplier 132 and multiplied by h (a constant other than zero), and then inputted to an input B of the selector 131.
  • the input B of the selector 131 is selected under control of a select signal Se, so that dc components D y ', D cb ' and D cr ' are outputted as the results of multiplying the dc components D y , D cb and D cr by the constant h.
  • the selector 131 selects the input A, so that the dc components D y , D cb and D cr are outputted as they are.
  • ac components A y , A Cb and A Cr are inputted in sequence through an input A of a selector 133, and zero is inputted through an input B thereof.
  • the input B of the selector 133 is selected under control of a select signal Se, so that zero is outputted as the output signals A y ', A Cb ' and A Cr '.
  • the selector 133 selects the input A, so that the ac components A y , A Cb and A Cr are outputted as they are.
  • Signal processing as described with respect to Figs. 4 and 5 are simultaneously conducted under control of the select signal Se.
  • the dc component D y of the luminance block Y for forming the discrete cosine transform coefficients is multiplied by i (a constant other than zero) to form the dc component D y ' of the luminance block Y' of the output signals.
  • the ac component A y of the luminance block Y is multiplied by I (a constant other than zero) to form the ac component A y ' of the luminance block Y' of the output signals.
  • the respective dc components D Cb and D Cr of the respective chrominance blocks Cb and Cr are replaced with j and k (a constant, respectively), respectively to form the dc components D Cb ' and D Cr ' of the chrominance blocks Cb' and Cr' of the output signals, and further the respective ac components A Cb and A Cr of the respective chrominance blocks Cb and Cr are replaced with J and K (a constant, respectively), respectively to form the ac components A Cb ' and A Cr ' of the chrominance blocks Cb' and Cr' of the output signals.
  • D2 and A2 denote dummy variables, respectively. These dummy variables are not outputted to the IDCT section 14.
  • the reason why these dummy variables are used is that a matrix of four-rows and four-columns is used as the determinant. Further, the reason why the matrix of four-rows and four-columns is used as the determinant is that a four-row four-column determinant is required to be used in the thermographic-image-processing (as described later). If considered is only the monochromatic-image-processing, it is available to use a matrix of at least three-rows and three-columns.
  • the circuit configuration same as shown in Fig. 4 can be applied to a circuit for obtaining the dc component D y ' of the luminance block Y' of the output signals by multiplying the dc component D y of the luminance block Y by i (a constant other than zero), and a circuit for obtaining the ac component A y ' of the luminance block Y' of the output signals by multiplying the ac component A y of the luminance block Y by I (a constant other than zero).
  • the dc component D y (ac component A y ) may be inputted to the input A of the selector 131 and the multiplier 132, and further the constant i (I) to the multiplier 132.
  • circuit configuration same as shown in Fig. 5 can be applied to a circuit for obtaining the dc components D cb ' and D cr ' of the chrominance block Cb' and Cr' of the output signals by replacing, respectively, the dc components D cb and D cr of the chrominance blocks Cb and Cr with j and k (a constant, respectively) and a circuit for obtaining the ac components A cb ' and A cr ' of the chrominance block Cb' and Cr' of the output signals by replacing, respectively, the ac components A cb and A cr of the chrominance blocks Cb and Cr with J and K (a constant, respectively).
  • Fig. 5 the circuit configuration same as shown in Fig. 5 can be applied to a circuit for obtaining the dc components D cb ' and D cr ' of the chrominance block Cb' and Cr' of the output signals by replacing, respectively, the dc components D cb and D cr of the chrominance
  • the input B of the selector 133 is grounded for inputting zero, however, a constant other than zero may be inputted.
  • the dc component D cb of the chrominance block Cb and the constant j may be inputted to the inputs A and B of the selector 133, respectively.
  • thermographic-image-processing by the video effect processing section 13 will be explained hereinbelow.
  • D3 and A3 denote dummy variables, respectively. These dummy variables are not outputted to the IDCT section 14. The reason why these dummy variables are used is to execute the operations by use of a simple determinant.
  • the dc component D y and the constant m are inputted to a multiplier 134.
  • the output dc component mD y of the multiplier 134 is inputted to an adder 135 that adds the constant n to the dc component mD y to produce the dc component D Cb '.
  • This dc component is inputted to an input B of a selector 136.
  • Inputted to an input A of the selector 136 is the dc component D Cb of the chrominance block Cb.
  • the dc component D y and the constant s are respectively inputted to inputs A and B of a selector 137.
  • the selectors 136 and 137 both select the input B under the control of select signals Se1 and Se2.
  • thermographic-image-processing is not conducted, under the control of the select signal Se1, the dc components D Cb of the chrominance block Cb is outputted as it is.
  • the video effect processing can be executed by operating the discrete cosine transform coefficients, it is unnecessary to store a great amount of processing data required for the respective image processing in a memory unit in the form of tables. As a result, it is possible to reduce an increase in the circuit scale required when the video effect processing function is additionally provided for the ordinary image processing system.
  • the video effect processing function can be added to the conventional image processing system, without modifying the system construction largely, it is possible to realize the image processing system relatively easily at a low cost.
  • the image processing system according to the present invention has been explained on the basis of the image processing system for executing the mosaic-, monochromatic-and thermographic-image-processing, it is of course possible to apply the image processing system according to the present invention to the case where only a part of these image processings is adopted or where another processing is used in common with the above-mentioned image processing.
  • the image processing system according to the present invention is applied to the image processing system for decompressing image signals
  • the video effect processing is executed by the video effect processing section of the present invention.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Color Television Systems (AREA)
EP95108978A 1994-06-09 1995-06-09 Bildverarbeitungssysteme und -verfahren Expired - Lifetime EP0686940B1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP12783994 1994-06-09
JP12783994 1994-06-09
JP127839/94 1994-06-09

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EP0686940A1 true EP0686940A1 (de) 1995-12-13
EP0686940B1 EP0686940B1 (de) 2000-08-30

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1847956A1 (de) * 2005-02-07 2007-10-24 NEC Corporation Bildbearbeitungsvorrichtung

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3260284B2 (ja) * 1996-08-29 2002-02-25 旭光学工業株式会社 画像圧縮装置および画像伸張装置
US5987184A (en) * 1996-09-30 1999-11-16 Kweon; Ji-Heon Device for coding/decoding image information
US5974184A (en) * 1997-03-07 1999-10-26 General Instrument Corporation Intra-macroblock DC and AC coefficient prediction for interlaced digital video
US6434280B1 (en) * 1997-11-10 2002-08-13 Gentech Corporation System and method for generating super-resolution-enhanced mosaic images
US6115076A (en) * 1999-04-20 2000-09-05 C-Cube Semiconductor Ii, Inc. Compressed video recording device with non-destructive effects addition
WO2004036925A2 (en) * 2002-10-16 2004-04-29 Hitron Usa Non-intrusive sensor and method
US7609882B2 (en) * 2005-05-25 2009-10-27 Himax Technologies Limited Image compression and decompression method capable of encoding and decoding pixel data based on a color conversion method

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04315371A (ja) 1991-04-15 1992-11-06 Canon Inc 画像処理方法及び装置
JPH05167920A (ja) * 1991-12-19 1993-07-02 Mitsubishi Electric Corp 画像拡大装置及び画像信号記録再生装置
JPH05284361A (ja) * 1992-03-31 1993-10-29 Nec Home Electron Ltd 画像再生装置
WO1995015538A1 (en) * 1993-11-30 1995-06-08 Polaroid Corporation Coding methods and apparatus for scaling and filtering images using discrete cosine transforms

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04315371A (ja) 1991-04-15 1992-11-06 Canon Inc 画像処理方法及び装置
JPH05167920A (ja) * 1991-12-19 1993-07-02 Mitsubishi Electric Corp 画像拡大装置及び画像信号記録再生装置
JPH05284361A (ja) * 1992-03-31 1993-10-29 Nec Home Electron Ltd 画像再生装置
WO1995015538A1 (en) * 1993-11-30 1995-06-08 Polaroid Corporation Coding methods and apparatus for scaling and filtering images using discrete cosine transforms

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 17, no. 575 (E - 1449) 20 October 1993 (1993-10-20) *
PATENT ABSTRACTS OF JAPAN vol. 18, no. 69 (E - 1502) 4 February 1994 (1994-02-04) *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1847956A1 (de) * 2005-02-07 2007-10-24 NEC Corporation Bildbearbeitungsvorrichtung
EP1847956A4 (de) * 2005-02-07 2013-01-09 Nec Corp Bildbearbeitungsvorrichtung

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DE69518583D1 (de) 2000-10-05
US5802210A (en) 1998-09-01
DE69518583T2 (de) 2001-04-26
EP0686940B1 (de) 2000-08-30

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