EP0682305A1 - Circuit device for generating a reference current - Google Patents

Circuit device for generating a reference current Download PDF

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Publication number
EP0682305A1
EP0682305A1 EP95106997A EP95106997A EP0682305A1 EP 0682305 A1 EP0682305 A1 EP 0682305A1 EP 95106997 A EP95106997 A EP 95106997A EP 95106997 A EP95106997 A EP 95106997A EP 0682305 A1 EP0682305 A1 EP 0682305A1
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EP
European Patent Office
Prior art keywords
transistor
transistors
circuit arrangement
resistor
supply voltage
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EP95106997A
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German (de)
French (fr)
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EP0682305B1 (en
Inventor
Werner Dipl.-Ing. Veit
Stefan Dipl.-Ing. Beyer
Bruno Dipl.-Ing. Scheckel
Jean Dipl.-Ing. Wilwert
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Siemens AG
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Siemens AG
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/265—Current mirrors using bipolar transistors only

Definitions

  • the invention relates to a circuit arrangement for generating a reference current.
  • a reference current generated in CMOS technology would therefore be subject to tolerances and unsuitable for e.g. a downstream PLL circuit.
  • the object of the present invention is to produce a circuit arrangement for generating a constant, adjustable reference current for a CMOS circuit arrangement.
  • the reference current for a CMOS circuit arrangement is generated on a bipolar chip on which e.g. the oscillator to be controlled is also located.
  • 1 denotes an input terminal to which a reference voltage can be supplied.
  • the input terminal 1 is connected to the base terminal of an npn transistor 8.
  • the emitter of the npn transistor 8 is connected to ground via an external connection terminal 3 and an externally connectable resistor 26.
  • the collector of transistor 8 is connected on the one hand to the base of a pnp transistor 9 and to the collectors of two pnp transistors 4 and 6.
  • the collector of transistor 9 is connected to ground.
  • the emitters of transistors 4 and 6 are each connected to a supply voltage terminal 2 via resistors 5 and 7.
  • the supply voltage terminal 2 is also connected via a resistor 10 to the emitter of the transistor 9.
  • 6 pnp output transistors 12, 14, 16, 18, 20, 22 are provided in the exemplary embodiment, the base connections of which are each connected to one another and to the base connections of transistors 4 and 6 and to the emitter of transistor 9.
  • the supply voltage terminal 2 is connected via a resistor 11, 13, 15, 17, 19, 21 to the emitters of the transistors 12, 14, 16, 18, 20, 22.
  • the collectors of the transistors 12, 14, 16, 18, 20, 22 are connected to one another and to an output terminal 25.
  • the output terminal 25 is connected to ground via two transistors 23, 24 connected in series as a diode.
  • a reference voltage is given to the base of transistor 8, which is derived from a high-precision constant current generated in a band gap, for example.
  • the desired reference current is set using the external resistor 26. In the example shown, this current is through the current mirror, which consists of the transistors 4, 6, 9, 12, 14, 16, 18, 20, 22 and the resistors 5, 7, 10, 11, 13, 15, 17, 19, 21 is mirrored by a factor of 3 and is available at the output terminal 25 for a subsequent CMOS circuit arrangement.
  • this reference current is independent of the supply voltage.
  • the tolerance of the external resistor 26 defines the corresponding spread of the reference current.
  • the temperature dependency of the current is minimal, since the corresponding bias circuit in bipolar technology is very well temperature-compensated.
  • the transistors 23 and 24 connected as diodes allow the reference current to flow to ground if the output terminal 25 is not connected or a downstream CMOS circuit is in a so-called standby mode.
  • the number of transistors connected in parallel in the input circuit of the current mirror, in the example shown, transistors 4 and 6, and the number of transistors in the output circuit, in the example shown, the six transistors 12, 14, 16, 18, 20, 22 can be chosen as desired and is determined by the level of the desired output current.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Control Of Electrical Variables (AREA)

Abstract

Die erfindungsgemäße integrierte Schaltungsanordnung zur Erzeugung eines Referenzstroms in Bipolartechnologie weist einen ersten Transistor (8) vom ersten Leitungstyp auf, dessen Steueranschluß mit einer Referenzspannung beaufschlagt wird und dessen Laststrecke über einen extern anschließbaren Widerstand (26) mit einem Bezugspotential verbindbar ist. Des weiteren ist eine Stromspiegelanordnung (4..22) vorgesehen, die eingangsseitig zwischen Laststrecke des Transistors (8) und einer Versorgungsspannungsquelle (2) geschaltet ist und an deren Ausgang (25) der Referenzstrom abgegriffen werden kann. <IMAGE>The integrated circuit arrangement according to the invention for generating a reference current in bipolar technology has a first transistor (8) of the first conductivity type, the control connection of which is supplied with a reference voltage and the load path of which can be connected to a reference potential via an externally connectable resistor (26). Furthermore, a current mirror arrangement (4..22) is provided which is connected on the input side between the load path of the transistor (8) and a supply voltage source (2) and at whose output (25) the reference current can be tapped. <IMAGE>

Description

Die Erfindung betrifft eine Schaltungsanordnung zur Erzeugung eines Referenzstroms.The invention relates to a circuit arrangement for generating a reference current.

Für eine genau definierte Einschwingzeit bei gegebener Außenbeschaltung benötigt z.B. ein PLL-Baustein einen exakten, temperaturunabhängigen Referenzstrom. Im Falle einer verwendeten PLL in CMOS-Technologie ist eine Erzeugung dieses Referenzstroms auf dem PLL-Baustein mit zu hohen Toleranzen verbunden, da der entsprechende CMOS-Prozeß nicht besonders "analogfähig" ist.For a precisely defined settling time for a given external circuit, e.g. a PLL block an exact, temperature-independent reference current. In the case of a PLL used in CMOS technology, generation of this reference current on the PLL module is associated with tolerances which are too high, since the corresponding CMOS process is not particularly "analog capable".

Ein in CMOS-Technologie erzeugter Referenzstrom wäre somit mit Toleranzen beaufschlagt und ungeeignet für z.B. eine nachgeschaltete PLL-Schaltung.A reference current generated in CMOS technology would therefore be subject to tolerances and unsuitable for e.g. a downstream PLL circuit.

Aufgabe der vorliegenden Erfindung ist es eine Schaltungsanordnung zur Erzeugung eines konstanten einstellbaren Referenzstroms für eine CMOS-Schaltungsanordnung zu erzeugen.The object of the present invention is to produce a circuit arrangement for generating a constant, adjustable reference current for a CMOS circuit arrangement.

Diese Aufgabe wird durch den kennzeichnenden Teil des Anspruchs 1 gelöst. Weiterbildungen sind Kennzeichen der Unteransprüche.This object is solved by the characterizing part of claim 1. Further training is characteristic of the subclaims.

Zur Lösung des obengenannten Problems wird erfindungsgemäß der Referenzstrom für eine CMOS-Schaltungsanordnung auf einem Bipolarbaustein erzeugt, auf dem sich z.B. auch der zu regelnde Oszillator befindet.To solve the above-mentioned problem, the reference current for a CMOS circuit arrangement is generated on a bipolar chip on which e.g. the oscillator to be controlled is also located.

Die Erfindung wird nachfolgend anhand des in der einzigen Figur dargestellten Ausführungsbeispiels näher erläutert.The invention is explained in more detail below with reference to the embodiment shown in the single figure.

In der Figur ist mit 1 eine Eingangsklemme bezeichnet, der eine Referenzspannung zuführbar ist. Die Eingangsklemme 1 ist mit dem Basisanschluß eines npn-Transistors 8 verbunden. Der Emitter des npn-Transistors 8 ist über eine externe Anschlußklemme 3 sowie einen extern anschließbaren Widerstand 26 mit Masse verbunden. Der Kollektor des Transistors 8 ist zum einen mit der Basis eines pnp-Transistors 9 sowie den Kollektoren zweier pnp-Transistoren 4 und 6 verbunden. Der Kollektor des Transistors 9 ist mit Masse verschaltet. Die Emitter der Transistoren 4 und 6 sind jeweils über Widerstände 5 und 7 mit einer Versorgungsspannungsklemme 2 verschaltet. Die Versorgungsspannungsklemme 2 ist des weiteren über einen Widerstand 10 mit dem Emitter des Transistors 9 verbunden.In the figure, 1 denotes an input terminal to which a reference voltage can be supplied. The input terminal 1 is connected to the base terminal of an npn transistor 8. The emitter of the npn transistor 8 is connected to ground via an external connection terminal 3 and an externally connectable resistor 26. The collector of transistor 8 is connected on the one hand to the base of a pnp transistor 9 and to the collectors of two pnp transistors 4 and 6. The collector of transistor 9 is connected to ground. The emitters of transistors 4 and 6 are each connected to a supply voltage terminal 2 via resistors 5 and 7. The supply voltage terminal 2 is also connected via a resistor 10 to the emitter of the transistor 9.

Des weiteren sind im Ausführungsbeispiel 6 pnp-Ausgangstransistoren 12, 14, 16, 18, 20, 22 vorgesehen, deren Basisanschlüsse jeweils miteinander und mit den Basisanschlüssen der Transistoren 4 und 6 sowie mit dem Emitter des Transistors 9 verbunden sind. Die Versorgungsspannungsklemme 2 ist über jeweils einen Widerstand 11, 13, 15, 17, 19, 21 mit den Emittern der Transistoren 12, 14, 16, 18, 20, 22 verschaltet. Die Kollektoren der Transistoren 12, 14, 16, 18, 20, 22 sind miteinander und mit einer Ausgangsklemme 25 verschaltet.Furthermore, 6 pnp output transistors 12, 14, 16, 18, 20, 22 are provided in the exemplary embodiment, the base connections of which are each connected to one another and to the base connections of transistors 4 and 6 and to the emitter of transistor 9. The supply voltage terminal 2 is connected via a resistor 11, 13, 15, 17, 19, 21 to the emitters of the transistors 12, 14, 16, 18, 20, 22. The collectors of the transistors 12, 14, 16, 18, 20, 22 are connected to one another and to an output terminal 25.

Schließlich ist die Ausgangsklemme 25 über zwei in Reihe als Diode geschaltete Transistoren 23, 24 mit Masse verbunden.Finally, the output terminal 25 is connected to ground via two transistors 23, 24 connected in series as a diode.

Auf die Basis des Transistors 8 wird eine Referenzspannung gegeben, die sich aus einem in z.B. einer Bandgap erzeugten hochgenauen Konstantstrom ableitet. Mit Hilfe des externen Widerstands 26 wird der gewünschte Referenzstrom eingestellt. Im dargestellten Beispiel wird dieser Strom durch den Stromspiegel, welcher aus den Transistoren 4, 6, 9, 12, 14, 16, 18, 20, 22 und den Widerständen 5, 7, 10, 11, 13, 15, 17, 19, 21 besteht um den Faktor 3 gespiegelt und steht an der Ausgangsklemme 25 für eine nachfolgende CMOS-Schaltungsanordnung zur Verfügung.A reference voltage is given to the base of transistor 8, which is derived from a high-precision constant current generated in a band gap, for example. The desired reference current is set using the external resistor 26. In the example shown, this current is through the current mirror, which consists of the transistors 4, 6, 9, 12, 14, 16, 18, 20, 22 and the resistors 5, 7, 10, 11, 13, 15, 17, 19, 21 is mirrored by a factor of 3 and is available at the output terminal 25 for a subsequent CMOS circuit arrangement.

Aufgrund der Schaltungsanordnung ist dieser Referenzstrom unabhängig von der Versorgungsspannung. Die Toleranz des externen Widerstands 26 legt die entsprechende Streuung des Referenzstroms fest. Die Temperaturabhängigkeit des Stroms ist minimal, da die entsprechende Biasschaltung in Bipolartechnologie sehr gut temperaturkompensiert ist.Due to the circuit arrangement, this reference current is independent of the supply voltage. The tolerance of the external resistor 26 defines the corresponding spread of the reference current. The temperature dependency of the current is minimal, since the corresponding bias circuit in bipolar technology is very well temperature-compensated.

Die als Diode geschalteten Transistoren 23, und 24 ermöglichen ein Abfliessen des Referenzstroms nach Masse, wenn der Ausgangsanschluß 25 unbeschaltet ist oder eine nachgeschaltete CMOS-Schaltung sich in einem sogenannten Standby-Modus befindet.The transistors 23 and 24 connected as diodes allow the reference current to flow to ground if the output terminal 25 is not connected or a downstream CMOS circuit is in a so-called standby mode.

Die Anzahl der parallel geschalteten Transistoren im Eingangskreis des Stromspiegels, im dargestellen Beispiel die Transistoren 4 und 6, sowie die Anzahl der Transistoren im Ausgangskreis, im dargestellten Beispiel die sechs Transistoren 12, 14, 16, 18, 20, 22 kann beliebig gewählt werden und wird durch die Höhe des gewünschten Ausgangsstroms festgelegt.The number of transistors connected in parallel in the input circuit of the current mirror, in the example shown, transistors 4 and 6, and the number of transistors in the output circuit, in the example shown, the six transistors 12, 14, 16, 18, 20, 22 can be chosen as desired and is determined by the level of the desired output current.

Claims (4)

Integrierte Schaltungsanordnung zur Erzeugung eines Referenzstroms in Bipolartechnologie,
gekennzeichnet durch - einen ersten Transistor (8) vom ersten Leitungstyp, dessen Steueranschluß mit einer Referenzspannung beaufschlagt wird und dessen Laststrecke über einen extern anschließbaren Widerstand (26) mit einem Bezugspotential verbindbar ist, - einer Stromspiegelanordnung (4..22), die eingangsseitig zwischen Laststrecke des Transistors (8) und einer Versorgungsspannungsquelle (2) geschaltet ist und an deren Ausgang (25) der Referenzstrom abgegriffen werden kann. Integrated circuit arrangement for generating a reference current in bipolar technology,
marked by a first transistor (8) of the first conductivity type, the control connection of which is supplied with a reference voltage and the load path of which can be connected to a reference potential via an externally connectable resistor (26), - A current mirror arrangement (4..22) which is connected on the input side between the load path of the transistor (8) and a supply voltage source (2) and at whose output (25) the reference current can be tapped. Schaltungsanordnung nach Anspruch 1,
dadurch gekennzeichnet, daß der Stromspiegel - n Transistoren (n≧1) vom anderen Leitungstyp enthält, deren Laststrecken einerseits mit der Laststrecke des ersten Transistors (8) und dem Steueranschluß eines zweiten Transistors (9) vom anderen Leitungstyp gekoppelt sind und andererseits über jeweils einen Widerstand (5, 7) mit dem Versorgungsspannungsanschluß (2) verbunden sind, - m Transistoren (12, 14, 18, 20, 22); m≧1 vom anderen Leitungstyp, deren Laststrecken einerseits miteinander und mit einer Ausgangsklemme (25) verbunden sind, und andererseits über jeweils einen Widerstand (11, 13, 15, 17, 19, 21) mit der Versorugungsspannungklemme (2) verbunden sind, wobei die Steueranschlüsse der n und m Transistoren (4, 6, 12, 14, 16, 18, 20, 22) miteinander und über einen Widerstand (10) mit der Versorgungsspannungsklemme sowie über die Laststrecke des zweiten Transistors (9) mit dem Bezugspotential verbunden sind. Circuit arrangement according to claim 1,
characterized in that the current mirror - Contains n transistors (n ≧ 1) of the other conductivity type, the load paths of which are coupled on the one hand to the load path of the first transistor (8) and the control terminal of a second transistor (9) of the other conductivity type and on the other hand each via a resistor (5, 7) are connected to the supply voltage connection (2), - m transistors (12, 14, 18, 20, 22); m ≧ 1 of the other line type, the load paths of which are connected on the one hand to one another and to an output terminal (25), and on the other hand are each connected to the supply voltage terminal (2) via a resistor (11, 13, 15, 17, 19, 21), whereby the control connections of the n and m transistors (4, 6, 12, 14, 16, 18, 20, 22) are connected to one another and to the supply voltage terminal via a resistor (10) and to the reference potential via the load path of the second transistor (9) . Schaltungsanordnung nach einem der vorhergehenden Ansprüche,
dadurch gekennzeichnet, daß zwei Dioden (23, 24) vorgesehen sind, die zwischen Ausgang und Bezugspotential in Flußrichtung geschaltet sind.Circuit arrangement according to one of the preceding claims,
characterized in that two diodes (23, 24) are provided which are connected between the output and the reference potential in the flow direction. Schaltungsanordnung nach einem der vorhergehenden Ansprüche,
dadurch gekennzeichnet, daß die Referenzspannung durch eine Bandgap erzeugt wird.Circuit arrangement according to one of the preceding claims,
characterized in that the reference voltage is generated by a band gap.
EP95106997A 1994-05-11 1995-05-09 Circuit device for generating a reference current Expired - Lifetime EP0682305B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE4416711A DE4416711C1 (en) 1994-05-11 1994-05-11 Solid state circuit for generating reference current
DE4416711 1994-05-11

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EP0682305A1 true EP0682305A1 (en) 1995-11-15
EP0682305B1 EP0682305B1 (en) 2000-08-02

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US5990725A (en) * 1997-06-30 1999-11-23 Maxim Integrated Products, Inc. Temperature measurement with interleaved bi-level current on a diode and bi-level current source therefor
DE10038321A1 (en) * 2000-08-05 2002-02-14 Philips Corp Intellectual Pty Adaptation circuit for audio and video signals
US6552614B1 (en) * 2000-11-08 2003-04-22 Texas Instruments Incorporated Broadband cable modem amplifier with programmable bias current
US7733076B1 (en) * 2004-01-08 2010-06-08 Marvell International Ltd. Dual reference current generation using a single external reference resistor

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Also Published As

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EP0682305B1 (en) 2000-08-02
DE59508604D1 (en) 2000-09-07
US5663674A (en) 1997-09-02
DE4416711C1 (en) 1995-08-03

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