EP0057351A2 - Circuit for delay normalisation of interconnected semiconductor circuits - Google Patents

Abstract

In this circuit, which is provided as a control circuit on each semiconductor chip and contains a phase comparison circuit in which the frequency of an externally supplied pulse train characterizing the setpoint of the signal delay is compared with the frequency of a controllable oscillator located on the semiconductor chip, an additional circuit is provided. It is connected to the phase comparison circuit and has three outputs to indicate whether the frequency of the controllable oscillator is less than, equal to or greater than that of the externally supplied pulse train. The additional circuit is made up of three logic elements. The outputs of the two logic elements, which indicate that the frequency of the controllable oscillator is higher or lower than that of the externally supplied pulse train, are connected to the third logic element, which indicates frequency equality. The logic gates are implemented as NOR gates.

Description

The invention relates to a circuit for .Adjusting the signal delay times of interconnected semiconductor chips with respect to a desired value, which is characterized by the frequency of an externally supplied pulse train and is achieved by means of a control circuit provided on each semiconductor chip by changing the electrical power supplied to the semiconductor chip. For this purpose, the control circuit contains a controllable oscillator and a phase comparison circuit in which the frequency of the controllable oscillator is compared with that of the first pulse train supplied and, in the event of a deviation, is readjusted until synchronization.

The current method of circuit design is to design logic circuits and regular arrangements out of them that operate at a certain power level. There are numerous teachings in the art to maintain a certain power level or current level within a logic gate. In particular, in the technology of current transfer switches, additional circuits are provided on a semiconductor chip in order to minimize the change in the current level within the logic gate, while the temperature, the supply voltages and also the influences of the manufacturing process vary from lot to lot. Fig. 1 shows a typical signal delay versus power curve with an arrow showing current design practice - choosing a power level, maintaining that power level and accepting the resulting signal delay. The design attempts to minimize changes in operational behavior under a number of conditions. The signal delay curve of a gate as a function of power in Figure 1 can move in any direction and even change its slope. At the same time, the control circuit for the power loss has its own faults. on. This results in a wide spread of the switching FI 980 030 logic gate speeds.

Figure 2 shows a curve of gate signal delay as a function of power dissipation and serves to illustrate the preferred design method according to the invention. The switching speed or signal delay of the logic gate is selected and the power loss within the circuit is set so that this switching speed is achieved. This is accomplished by designing circuits on the semiconductor chip that are sensitive to the performance characteristics of the logic circuits or matrix arrays on the chip that are applicable during balancing operations. This special circuit (controller for the signal delay) generates a signal which indicates the behavior of the semiconductor chip (switching speed as a function of the power), which is compared with a periodic reference or clock signal used for the entire system. The comparison generates a signal which regulates the electrical power supplied to the logic and / or matrix circuits on the semiconductor chip and thus the operating behavior. (Namely, the point on the curve indicating the gate signal delay as a function of power, which corresponds to a set gate signal delay). By supplying the reference signal to all of the semiconductor chips in the system, all of these chips have the same relative performance, i. H. the same gate signal delay or switching speed. Since a continuous comparison is made between the reference signal and the signal generated on the semiconductor chip, many variables that influence the operational behavior, such as e.g. B. the power supply, temperature changes, fluctuations in the manufacture of the individual chips, etc. minimized or eliminated.

From US patent Re 29 619 a digital-to-analog converter is known, the output circuit of which is a set of switches Has transistors, which are arranged as current generators. The currents through the switching transistors are kept constant by means of a circuit which adjusts the supply voltage accordingly and contains a separate reference transistor which corresponds to one of the switching transistors and is connected to the same voltage supply lines as the switching transistors. The control circuit for the supply voltage contains an operational amplifier, which senses the collector current of the reference transistor and adjusts the supply voltage so that the collector current remains constant. This automatic adjustment of the supply voltage also keeps the current through the switching transistors constant.

U.S. Patent 3,602,799 discloses a highly stable and fast switching, direct current power source for generating an accurate reference voltage for use in other devices such as very fast analog-to-digital converters. A continuous, constant load current is selectively switched between two current paths, one of which contains an output load at which the reference voltage is generated. A digitally controlled, very fast operating driver circuit with a differential amplifier configuration controls the flow of the constant current either through one of two Schottky diodes. The diodes serve as electronic switches of the constant current source, which contains an operational amplifier arranged in a feedback loop, which contains a Darlington transistor configuration and is controlled by an externally supplied input reference voltage and an error signal caused by the flow of the load current over a temperature compensated resistance is generated.

U.S. Patent 3,743,850 describes an integrated power supply circuit in which operating point setting currents for a monolithic integrated circuit are obtained from a regulated reference current source that supplies current through first and second series connected diodes to establish points of reference potential. Some of the current source transistors connected to this regulated current source have their base-emitter paths connected to the first diode, and the emitter current of these current source transistors is collected and added to the regulated voltage source current and flows through the second diode. This second diode, through which a larger regulated current flows, is used to serve as a reference for other current source transistors with much larger currents, without it being necessary to set a high area ratio for the emitter areas of these current source transistors.

A monolithically integrable constant current source for transistors is known from US Pat. No. 3,754,181, which are connected to one another as current-stabilizing elements. In order to reduce the sensitivity to fluctuations in the supply voltage in a monolithically integrated constant current source with a number of transistors, the control transistor is replaced by an amplifier. Only a fraction of the sum of the base currents of the current source transistors is fed to the input of the amplifier. The number of current source transistors is also not limited by the current amplification factor, as is the case when a control transistor is used.

A current takeover circuit is described in U.S. Patent 3,758,791. It consists of a pair of transistors in which one transistor serves as a reference element and the other as an input element. The circuit contains further two series circuits consisting of a resistance element and a diode, each connected between the respective collectors of the two transistors, the polarity of the diodes being opposite to one another, so that the emitter currents of the transistors are automatically regulated to maintain a predetermined value, thereby reducing the direct current level the output voltages of the current take-over circuit are kept constant in relation to temperature-related fluctuations in the transistor parameters.

A semiconductor logic circuit is known from US Pat. No. 3,778,646, which operates in current mode and contains at least one transistor with a grounded emitter, via which an operating voltage source is connected to the logic circuit. The output of the logic circuit is fed back to the transistor with a grounded emitter via a feedback circuit. As a result, the fluctuation at the output of the logic circuit can be kept to a minimum even if the load on the logic circuit is changed.

US Pat. No. 3,794,861 discloses the circuit of a reference voltage generator which is particularly suitable for constant current circuits which have a low temperature and a low voltage sensitivity. The circuit consists of a sub-circuit for the reference voltage, which has a low voltage sensitivity and a relatively high temperature sensitivity, and an additional feedback circuit for feeding back a compensating temperature sensitivity in order to obtain a low overall sensitivity. The temperature sensitivity of the reference voltage generator is mainly based on the temperature sensitivity of the voltage drop across a base-emitter diode, which is selectively controlled or can essentially be canceled by a suitable selection of resistors in the feedback circuit, so that a temperature-sensitive component is fed back. The feedback signal is dependent on the difference in voltage drops in the base-emitter diodes of two transistors that conduct currents of different sizes and is amplified in a similar manner in order to actually allow the sensitivity of the reference voltage generator to be removed.

From US Pat. No. 3,803,471 a control circuit for pulse width modulation is known which has a circuit breaker which does not require an external device for current equalization. The circuit has a series of power transistors connected in parallel, whose transmission ratio for the current in the forward direction abruptly decreases as the collector current increases, and whose base voltage is supplied by a switching regulator which outputs a constant current and which has a series of parallel-connected are connected to the output terminals of the controller and are switched on by pulses of variable width in order to derive current from the power transistors and thereby switch the circuit breaker on and off. The output of the regulator is coupled to the base of each power transistor via a diode, the forward voltage drop of which supports the division of the base current and prevents multiple transistor failures.

US Pat. No. 3,808,468 describes a field effect bootstrap amplifier whose precharge gate has a relatively high gate voltage and a relatively low drain voltage provided by a common supply source. The gate voltage is derived from periodic pulses, which from a free-running FET multivibrator located on the semiconductor chip and a voltage multiplier circuit are generated which are fed by said supply source. The pulse width of the periodic pulses changes as an inverse function of the slope of the field-effect transistors located on the semiconductor chip and as a direct function of their threshold voltage. The pulse width controls the charging time of an additional capacitor in the voltage multiplier circuit, whereby the amplitude of the additional voltage is a direct function of the pulse width. The additional voltage is fed to the gate of the FET bootstrap amplifier.

A digital-to-analog converter is known from US Pat. No. 3,978,473, which contains a switching module designed as an integrated circuit with four switching transistors and associated control circuit. The emitter areas of the switching transistors are binary weighted to ensure the same current densities. A fifth transistor serves as a reference transistor for adjusting the supply voltage, which is necessary in order to maintain a constant current through the switching transistors. To construct a digital-to-analog converter that has a high bit resolution, a number of such "four" switching modules can be combined, e.g. B. in a circuit board assembly that includes a thin film resistor module that has binary weighted resistors on a glass substrate to adjust the current levels for the switching transistors.

U.S. Patent 4,004,164 discloses a current source for use on a semiconductor chip with field effect transistors to compensate for changes in the voltage source for the substrate voltage. When analog circuits, alone or in combination with digital logic circuits, are on a semiconductor chip, they are usually sensitive to bias disturbances affecting the sub strat of the semiconductor chip is supplied. Achieving a uniform output of an analog circuit due to a change in the input voltage has previously required the use of precision voltage sources outside of the semiconductor chip. Such expensive precision voltage sources can be eliminated, and normal variable power supplies (+ 15%) can be used by providing an on-chip compensation current source that is integrated with other circuits to provide stable reference voltage levels on the semiconductor chip for use by the analog circuits .

The compensation circuit contains two field effect transistors of the depletion type, which are connected in series between a voltage source with a higher voltage and the substrate voltage, the field effect transistor, which is connected to the higher voltage, having its gate connected to the common node of the two transistors and in Saturation is located while the gate of the field effect transistor connected to the lower voltage is connected to ground potential and this transistor operates in the linear range of the characteristic. The gate of an enhancement type field effect transistor is connected to the common node of the two depletion type field effect transistors and its source electrode to the negative pole of the substrate voltage source. Through a suitable selection of the parameters, a current flows through this circuit, which changes in reverse to the changes in the substrate bias in order to give a compensated current source for the other analog circuits. As examples, circuits for a stabilized reference voltage source, a current control circuit for a differential amplifier and a combined circuit are shown. U.S. Patent 4,029,974 discloses a digital-to-analog converter formed from a series of current source transistors arranged to carry different current levels in accordance with a predetermined weight pattern, ie a binary weight pattern. In the converter, a number of current source transistors of the same size carry the different current levels and therefore work at different current densities with different base-emitter voltages, depending on the temperature drift. Stable emitter voltages that provide accurate levels of the weighted current are generated by resistors between the bases of successive current source transistors and a current source to produce a voltage across the resistors between the bases that changes linearly with the absolute temperature, corresponding to that Difference between the base-emitter voltages of successive current source transistors.

The circuit for generating a current which changes linearly with the absolute temperature is formed from first and second transistors which are forced to carry the same current at different current densities in order to generate different base-emitter voltages and by means such as an emitter resistor which is connected to the difference in base-emitter voltages is responsive to produce a current that corresponds to the difference in base-emitter voltages and changes linearly with temperature;

An interface circuit is known from US Pat. No. 4,100,431 for connecting a part of an integrated circuit, which is designed as integrated injection logic ( _I ² _L ), to a linear part of the integrated circuit. The circuit transfers both logic information and 1 2 L reference current levels from the I ² L circuit to the linear circuit at relatively high voltage levels are present in the linear circuit. One embodiment uses a cascode arrangement with a transistor, two diodes and a resistor. Another embodiment takes advantage of the similar properties of a pair of transistors operating in forward and reverse operation to perform the function with only one transistor.

U.S. Patent 4,145,621 discloses a transistor logic circuit which includes a constant current source in the form of a current mirror circuit connected to a combination of a logic gate made of switching transistors, the arrangement being such that the switching transistors do not saturate.

In U.S. Patent 4,160,934, the current is stabilized by a semiconductor light emitting diode which is supplied by a field effect transistor switch insulated gate, by a current control circuit which ^g serving as a comparator Rückkopplun snetzwerk includes that the voltage at the node between the mentioned switch and the series connection of a ballast resistor and the light-emitting diode stabilized.

From US Pat. No. 4,172,992 it is known to operate a pair of transistors with different current densities in order to generate a differential base-emitter potential. This potential serves as a reference in a negative feedback stabilization circuit that delivers a current that is regulated by the potential. The circuit can also regulate currents flowing in a number of additional current sources and sinks associated therewith.

The basic I ² L structure and circuitry is disclosed in U.S. Patent 3,736,477.

• (1) "Current Source Generator" von G. Keller et al., Vol. 12, No. 11, April 1970, Seite 2031;
• (2) "Precision Integrated Current Source" von A. Cabiedes et al., Vol. 13, No. 6, November 1970, Seite 1699;
• (3) "Voltage Reference Buffer" von J.A. Dorler et al., Vol. 14, No. 7, Dezember 1971, Seite 2095;
• (4) "Adjustable Underfrequency-Overfrequency Limiting Circuit" von W. B. Nunnery, Vol. 15, No. 6, November 1972, Seiten 1927-9;
• (5) "Reference Voltage Generator and OFF-Chip Driver For Current Switch Circuit" von A. Brunin, Vol. 21, No. 1, Juni 1978, Seiten 219-20; und
• (6) "Gated Current Source" von J. W. Spencer Jr., Vol. 21, No. 7, Dezember 1978, Seiten 2719-20.

With regard to the state of the art, reference is made to the following further publications from the IBM Technical Disclosure Bulletin:

• (1) "Current Source Generator" by G. Keller et al., Vol. 12, No. April 11, 1970, page 2031;
• (2) "Precision Integrated Current Source" by A. Cabiedes et al., Vol. 13, No. 6, November 1970, page 1699;
• (3) "Voltage Reference Buffer" by JA Dorler et al., Vol. 14, No. 7, December 1971, page 2095;
• (4) "Adjustable Underfrequency-Overfrequency Limiting Circuit" by WB Nunnery, Vol. 15, No. 6, November 1972, pages 1927-9;
• (5) "Reference Voltage Generator and OFF-Chip Driver For Current Switch Circuit" by A. Brunin, Vol. 21, No. 1, June 1978, pages 219-20; and
• (6) "Gated Current Source" by JW Spencer Jr., Vol. 21, No. 7, December 1978, pages 2719-20.

Furthermore, with regard to the prior art, the

• (1) "Integrated Injection Logic Shaping Up As Strong Bipolar Challenge to MOS", Electronic Design 15. März 1974, Seiten 28 und 30 und
• (2) "_I ² _L Puts _It All Together For 10-bit A-D Converter Chip" von Paul Brokaw, Electronics, 13.April 1978, S. 99-105.
• (3) "Delay Regulation A Performance Concept", von E. Berndlmaier, J.A. Dorler, J.M. Mosley u. S.D. Weitzel, Proceedings of the IEE International Conference on Circuits and Computers, ICCC80, Vol. 2, herausgegeben v. N.B. Guy Rabbat, Okt. 1980.

the following publications:

• (1) "Integrated Injection Logic Shaping Up As Strong Bipolar Challenge to MOS", Electronic Design March 15, 1974, pages 28 and 30 and
• (2) " _I ² _L Puts _I t All Together For 10-bit AD Converter Chip" by Paul Brokaw, Electronics, April 13, 1978, pp. 99-105.
• (3) "Delay Regulation A Performance Concept" by E. Berndlmaier, JA Dorler, JM Mosley u. SD Weitzel, Proceedings of the IEE International Conference on Circuits and Computers, ICCC80, Vol. 2, edited by NB Guy Rabbat, Oct. 1980.

The invention, as characterized in the claims solves the problem of a circuit of the ^above-g e-called type such that they respect also provides an indication of the relative signal delay of a semiconductor chip of a desired value. As a result, semiconductor chips can be divided into different categories with regard to their relative signal delay and used accordingly.

• Fig. 1 eine Kurve, die die Gatter-Signalverzögerung als Funktion der dem Gatter zugeführten elektrischen Leistung darstellt. Die Kurve der Fig. 1 gibt den Zustand nach dem Stand der Technik wieder, bei dem die Leistung festgelegt oder gewählt wird und die Schaltgeschwindigkeit oder die Signalverzögerung der Schaltung der ihr zugeführten Leistung entspricht;
• Fig. 2 eine Kurve, die die Gatter-Signalverzögerung als Funktion der Leistung für eine logische Schaltung angibt. Die Kurve nach Fig. 2 ist gemäß der Erfindung dargestellt, nach der die Gatter-Signalverzögerung (oder Schaltgeschwindigkeit) jeder aus einer Reihe von logischen Schaltungen auf einem Halbleiterchip (oder auf Halbleiterchips) fest vorgegeben ist oder beim Schaltungsentwurf festgelegt wurde, und die den logischen Schaltungen zugeführte elektrische Leistung (Strom oder Spannung) entspricht der gewählten oder fest vorgegebenen Schaltgeschwindigkeit;
• Fig. 3 ein Blockdiagramm gemäß der Erfindung. Eine Reihe von Halbleiterchips 1 bis n mit monolithisch integrierten Schaltungen sind dargestellt. Jedes Halbleiterchip enthält einen Regler für die Signalverzögerung und eine Reihe mit ihm verbundener logischer Schaltkreise. In der Zeichnung sind nur drei logische Schaltkreise dargestellt. Die logischen Schaltkreise sind als Blöcke dargestellt, die die Legende "Fig. 10" tragen. Ebenso sind die Verbindungen zwischen den logischen Schaltkreisen auf jedem Halbleiterchip und zwischen den Halbleiterchips, da sie für das Verständnis der Erfindung nicht notwendig sind, nicht dargestellt. Den Fachleuten ist bekannt, daß jedes der Halbleiterchips Hunderte von miteinander verbundenen logischen Schaltkreisen enthalten kann. Auch ist die Erfindung nicht beschränkt auf logische Schaltkreise der in Fig. 10 dargestellten Art (Stromübernahmeschalter oder emittergekoppelte Logikschaltkreise). Aus der nachfolgenden genaueren Beschreibung ist für den Durchschnittsfachmann ersichtlich, daß die Erfindung angewandt werden kann bei der Transistor-Transistor-Logik (T²L), der Dioden-Transistor-Logik (DTL), der integrierten Injektionslogik (I²L) und anderen Technologiefamilien als auch bei Matrixanordnungen. Aus der Fig. 3 ist zu ersehen, daß der Regler 4 für die Signalverzögerung jedes Halbleiterchips das gleiche Taktsignal empfängt. Jeder dieser Regler für die Signalverzögerung erzeugt intern auf dem Halbleiterchip ein diskretes bestimmtes Bezugssignal, das in Zusammenarbeit mit dem Taktsignal den Regler für die Signalverzögerung veranlaßt, ein eindeutiges Signal VCS zu liefern. Beispielsweise liefert der Regler für die Signalverzögerung des Halbleiterchips 1 (Fig. 3) das Signal VCS1, wogegen der Regler für die Signalverzögerung des Halbleiterchips 2 das Signal VCS2 (nicht dargestellt) liefert und der Regler für die Signalverzögerung des Halbleiterchips n liefert das Signal VCSn. Weiter weisen die Größen der Signale VCS1, VCS2, VCSn nicht notwendigerweise eine feste Beziehung zueinander auf. Die Größe oder die Werte jedes der Potentiale VCS1, VCS2, ... bis VCSn diktiert ein Punkt auf der Kurve, die die Gatter-Signalverzögerung als Funktion der Leistung wiedergibt, die diesem Halbleiterchip zugeordnet ist und für die ^ge-wünschte Schaltgeschwindigkeit sorgt;
• Fig. 4 das Blockdiagramm eines erfindungsgemäßen Reglers für die Signalverzögerung (Vorrichtung zur Leistungsregelung). Aus Fig. 3 ist ersichtlich, daß jedes Halbleiterchip einen Regler für die Signalverzögerung enthält. Die Schaltung des Reglers für die Signalverzögerung kann für jedes Halbleiterchip die gleiche sein. Jeder der Blöcke in Fig. 4 schließt eine Legende und eine Figurenzahl ein. Beispielsweise weist der Phasenkomparatorblock die Legende "0 Vergleichsschaltung" und "(Fig. 5)" auf, wogegen der spannungsgesteuerte Oszillator die Legende trägt "SGO (RLF)" und "(Fig. 8)". Diese Legenden bedeuten, daß die logische Schaltung der Vergleichsschaltung in Fig. 5 dargestellt ist und die logische Schaltung des spannungsgesteuerten Oszillators in Fig. 8. In dem Ausführungsbeispiel der Erfindung enthält der Regler für die Signalverzögerung eine "0 Vergleichsschaltung (Fig.5)", ein "Tiefpaßfilter (Fig.6)", eine "Pufferschaltung oder einen Leistungsverstärker (Fig.7)", einen "spannungsgesteuerten Oszillator RLF (Fig.8)" und eine "Pegelverschiebungsschaltung (Fig.9)", die so miteinander verbunden sind, wie das in Fig.4 dargestellt ist. Anstelle des spannungsgesteuerten Oszillators kann auch ein stromgesteuerter Oszillator verwendet werden;
• Fig. 4A idealisierte Kurvenverläufe und Potentialpegel, die in Verbindung mit der Erklärung der Wirkungsweise des Reglers für die Signalverzögerung (Fig.4) zu betrachten sind;
• Fig. 4B idealisierte Kurvenverläufe und Potentialpegel, die in Verbindung mit der Erklärung der Wirkungsweise der Phasenvergleichsschaltung und der Wechselstrom-Meßschaltung (Fig.5) zu betrachten sind für das Beispiels eines pegelverschobenen Signals des spannungsgesteuerten Oszillators, das eine niedrigere Frequenz als die Taktfrequenz besitzt;
• Fig. 4C idealisierte Kurvenverläufe und Potentialpegel, die in Verbindung mit der Erklärung der Wirkungsweise der Phasenvergleichsschaltung und der Wechselstrom-Meßschaltung (Fig.5) zu betrachten sind für ein Beispiel eines pegelverschobenen Signals des spannungsgesteuerten Oszillators, das eine höhere Frequenz als die Taktfrequenz aufweist;
• Fig. 4D idealisierte Kurvenverläufe und Potentialpegel, die in Verbindung mit der Erklärung der Wirkungsweise der Phasenvergleichsschaltung und der Wechselstrom-Meßschaltung (Fig. 5) für das Beispiel eines pegelverschobenen Signals des spannungsgesteuerten Oszillators zu betrachten sind, das die gleiche Frequenz wie die Taktfrequenz besitzt;
• Fig. 5 ein logisches Blockdiagramm einer handelsüblichen Phasenvergleichsschaltung, die gemäß der Erfindung in dem Regler für die Signalverzögerung (Fig.4) benutzt werden kann. Ferner sind drei Verknüpfungsglieder dargestellt, die als Wechselstrom-Meßschaltung verwendet werden. Die Eingangssignale für die Wechselstrom-Meßschaltung, die die Signale HOCH, NIEDRIG und GLEICH liefert, stammen von der Phasenvergleichsschaltung;
• Fig. 6 eine Tiefpaß-Filterschaltung, die gemäß der Erfindung in dem Regler für die Signalverzögerung (Fig. 4) verwendet werden kann;
• Fig. 7 eine Pufferschaltung, die gemäß der Erfindung in dem Regler für die Signalverzögerung (Fig.4) verwendet werden kann. Es sei bemerkt, daß die Pufferschaltung die Funktion eines Leistungsverstärkers erfüllt und auch so bezeichnet werden kann;
• Fig. 8 einen spannungsgesteuerten Oszillator (RLF), der gemäß der Erfindung in dem Regler für die Signalverzögerung (Fig. 4) verwendet werden kann. Es sei bemerkt, daß der spannungsgesteuerte Oszillator vorzugsweise eine Reihe von logischen Schaltkreisen verwendet, bei denen die Gatter-Signalverzögerung (oder Schaltgeschwindigkeit) durch den Regler für die Signalverzögerung geregelt werden soll. Bei dem hier offenbarten Ausführungsbeispiel der Erfindung ist der logische Schaltkreis, dessen Gatter-Signalverzögerung (oder Schaltgeschwindigkeit) geregelt werden soll, ein Stromübernahmeschalter (emittergekoppelter Logikschaltkreis) wie er in Fig. 10 dargestellt ist. Der spannungsgesteuerte Oszillator kann die Form einer Umlaufschleife annehmen, wie das in Fig. 8 dargestellt ist, in der die Gesamtanzahl der Inverterstufen ungerade ist;
• Fig. 9 eine Pegelverschiebungsschaltung, die gemäß der Erfindung in dem Regler für die Signalverzögerung (Fig. 4) verwendet werden kann;
• Fig. 10 einen als Stromübernahmeschalter ausgeführten Logikschaltkreis (emittergekoppelte Logik), dessen Gatter-Signalverzögerung (oder Schaltgeschwindigkeit) gemäß der Erfindung durch den Regler für die Signalverzögerung geregelt wird;
• Fig. 11 einen Bezugsspannungsgenerator zur Lieferung einer Bezugsspannung VREF, der von der Pegelverschiebungsschaltung nach Fig. 9 und dem internen Gatterschaltkreis nach Fig. 12 benutzt werden kann;
• Fig. 12 einen internen Gatterschaltkreis der Stromübernahme-Schaltkreisfamilie (oder emittergekoppelten Logik) , der in der Phasenvergleichsschaltung nach Fig. 5 verwendet werden kann;
• Fig. 13 das Blockschaltbild eines spannungsgesteuerten Oszillators (SGO) für die erfindungsgemäße Verwendung in der Leistungsregelvorrichtung eines Systems, in dem die Schaltkreise, deren Signalverzögerung zu regeln oder zu optimieren ist, der technologischen Schaltkreisfamilie der Transistor-Transistor-Logik angehören (, die in Fig. 14 dargestellt ist);
• Fig. 14 einen Schaltkreis in Transistor-Transistor-Logik, dessen Signalverzögerung gemäß der Erfindung geregelt oder optimiert wird durch Verwendung einer Vorrichtung zur Leistungssteuerung, die den spannungsgesteuerten Oszillator nach Fig. 13 enthält;
• Fig. 15 ein Blockschaltbild eines spannungsgesteuerten Oszillators zur erfindungsgemäßen Verwendung der Vorrichtung zur Leistungssteuerung eines Systems, dessen Schaltkreise, deren Signalverzögerung zu regeln oder zu optimieren ist, der Schaltkreisfamilie angehören, die als integrierte Injektionslogik (_I ²L) bezeichnet wird und in den Fign. 16 oder 17 dargestellt ist;
• Fig. 16 einen I²L-Schaltkreis, dessen Gatter-Signalverzögerung gemäß der Erfindung geregelt oder optimiert werden soll durch Verwendung einer Vorrichtung zur Leistungskontrolle, die den spannungsgesteuerten Oszillator nach Fig. 15 einschließt;
• Fig. 17 einen zweiter I2h-Schaltkreis, dessen Gatter-Signalverzögerung gemäß der Erfindung geregelt oder optimiert werden soll durch Verwendung einer Vorrichtung zur Leistungssteuerung, die den spannungsgesteuerten Oszillator nach Fig. 15 einschließt;
• Fig. 18 ein Blockdiagramm eines spannungsgesteuerten Oszillators zur erfindungsgemäßen Verwendung in der Vorrichtung zur Leistungssteuerung eines Systems, in dem die Schaltkreise, deren Signalverzögerung zu regeln oder zu optimieren ist, der Schaltkreisfamilie aus Feldeffekttransistoren angehören (von der ein Mitglied in Fig. 19 dargestellt ist) ;
• Fig. 19 einen Feldeffektttransistor-Schaltkreis, dessen Gatter-Signalverzögerung gemäß der Erfindung geregelt oder optimiert werden kann durch Verwendung einer Vorrichtung zur Leistungssteuerung, die den spannungsgesteuerten Oszillator nach Fig. 18 einschließt.'

The invention is explained in more detail below in conjunction with the drawings, in which:

• Fig. 1 is a graph showing the gate signal delay as a function of the electrical power supplied to the gate. The curve of FIG. 1 shows the state according to the prior art, in which the power is fixed or selected and the switching speed or the signal delay of the circuit corresponds to the power supplied to it;
• Fig. 2 is a graph indicating the gate signal delay as a function of power for a logic circuit. The curve of Fig. 2 is shown in accordance with the invention, according to which the gate signal delay (or switching speed) each of a series of logic circuits on egg a semiconductor chip (or on semiconductor chips) is predefined or was specified in the circuit design, and the electrical power (current or voltage) supplied to the logic circuits corresponds to the selected or predefined switching speed;
• Fig. 3 is a block diagram according to the invention. A number of semiconductor chips 1 to n with monolithically integrated circuits are shown. Each semiconductor chip contains a controller for signal delay and a number of logic circuits connected to it. Only three logic circuits are shown in the drawing. The logic circuits are shown as blocks bearing the legend "Fig. 10". Likewise, the connections between the logic circuits on each semiconductor chip and between the semiconductor chips are not shown since they are not necessary for an understanding of the invention. It is known to those skilled in the art that each of the semiconductor chips can include hundreds of interconnected logic circuits. The invention is also not limited to logic circuits of the type shown in FIG. 10 (current takeover switches or emitter-coupled logic circuits). It will be apparent to those of ordinary skill in the art from the following detailed description that the invention can be applied to transistor-transistor logic (T ² L), diode-transistor logic (DTL), integrated injection logic (I ² L) and others Technology families as well as matrix arrangements. From Fig. 3 it can be seen that the controller 4 for the signal delay each Semiconductor chips receives the same clock signal. Each of these controllers for the signal delay internally generates a discrete specific reference signal on the semiconductor chip which, in cooperation with the clock signal, causes the controller for the signal delay to deliver a unique signal VCS. For example, the controller for the signal delay of the semiconductor chip 1 (FIG. 3) supplies the signal VCS1, whereas the controller for the signal delay of the semiconductor chip 2 supplies the signal VCS2 (not shown) and the controller for the signal delay of the semiconductor chip n supplies the signal VCSn. Furthermore, the sizes of the signals VCS1, VCS2, VCSn do not necessarily have a fixed relationship to one another. The size or the values of each of the potentials VCS1, VCS2, ... up VCSN dictates a point on the curve, which represents the gate signal delay as a function of power that is associated with this semiconductor chip and provides desired e-for ^g switching speed;
• Fig. 4 shows the block diagram of a controller according to the invention for the signal delay (device for power control). From Fig. 3 it can be seen that each semiconductor chip contains a regulator for the signal delay. The circuit of the signal delay controller can be the same for each semiconductor chip. Each of the blocks in Fig. 4 includes a legend and a figure number. For example, the phase comparator block has the legend "0 comparison circuit" and "(FIG. 5)", whereas the voltage-controlled oscillator bears the legend "SGO (RLF)" and "(FIG. 8)". These legends mean that the lo 5 and the logic circuit of the voltage-controlled oscillator in FIG. 8. In the exemplary embodiment of the invention, the controller for the signal delay contains a "0 comparison circuit (FIG. 5)", a "low-pass filter (FIG. 6) ", a" buffer circuit or a power amplifier (FIG. 7) ", a" voltage controlled oscillator RLF (FIG. 8) "and a" level shift circuit (FIG. 9) ", which are connected to one another as shown in FIG. 4 is shown. Instead of the voltage-controlled oscillator, a current-controlled oscillator can also be used;
• 4A idealized waveforms and potential levels, which are to be considered in connection with the explanation of the mode of operation of the controller for the signal delay (FIG. 4);
• 4B idealized waveforms and potential levels, which are to be considered in connection with the explanation of the mode of operation of the phase comparison circuit and the AC measuring circuit (FIG. 5) for the example of a level-shifted signal of the voltage-controlled oscillator which has a lower frequency than the clock frequency;
• 4C idealized waveforms and potential levels, which are to be considered in connection with the explanation of the operation of the phase comparison circuit and the AC measuring circuit (FIG. 5) for an example of a level-shifted signal the voltage controlled oscillator which has a higher frequency than the clock frequency;
• Fig. 4D idealized waveforms and potential levels, which are to be considered in connection with the explanation of the operation of the phase comparison circuit and the AC measuring circuit (Fig. 5) for the example of a level-shifted signal of the voltage-controlled oscillator, which has the same frequency as the clock frequency;
• Fig. 5 is a logic block diagram of a commercially available phase comparison circuit which can be used in the controller for the signal delay (Fig. 4) according to the invention. Furthermore, three logic elements are shown, which are used as an AC measuring circuit. The input signals to the AC measurement circuit which provides the HIGH, LOW and EQUAL signals come from the phase comparison circuit;
• Fig. 6 shows a low pass filter circuit which can be used according to the invention in the signal delay regulator (Fig. 4);
• Fig. 7 shows a buffer circuit which can be used according to the invention in the controller for the signal delay (Fig.4). It should be noted that the buffer circuit fulfills the function of a power amplifier and can also be called this;
• Fig. 8 shows a voltage controlled oscillator (RLF) which can be used according to the invention in the controller for the signal delay (Fig. 4). It should be noted that the voltage controlled oscillator preferably uses a number of logic circuits in which the gate signal delay (or switching speed) is to be controlled by the signal delay controller. In the embodiment of the invention disclosed here, the logic circuit whose gate signal delay (or switching speed) is to be controlled is a current takeover switch (emitter-coupled logic circuit) as shown in FIG. 10. The voltage controlled oscillator may take the form of a circular loop, as shown in Fig. 8, in which the total number of inverter stages is odd;
• Fig. 9 shows a level shift circuit which can be used in the signal delay controller (Fig. 4) according to the invention;
• 10 shows a logic circuit (emitter-coupled logic) designed as a current takeover switch, the gate signal delay (or switching speed) of which is regulated according to the invention by the controller for the signal delay;
• FIG. 11 shows a reference voltage generator for supplying a reference voltage VREF, which can be used by the level shift circuit according to FIG. 9 and the internal gate circuit according to FIG. 12;
• FIG. 12 shows an internal gate circuit of the current take-over circuit family (or emitter-coupled logic) which can be used in the phase comparison circuit according to FIG. 5;
• 13 shows the block diagram of a voltage-controlled oscillator (SGO) for use according to the invention in the power control device of a system in which the circuits, the signal delay of which is to be regulated or optimized, belong to the technological circuit family of transistor-transistor logic (which are shown in FIG 14 is shown);
• 14 shows a circuit in transistor-transistor logic, the signal delay of which is regulated or optimized according to the invention by using a device for power control which contains the voltage-controlled oscillator according to FIG. 13;
• 15 is a block diagram of a voltage controlled oscillator for the inventive use of the device for power control of a system, the circuits whose signal delay is to be regulated or optimized belong to the circuit family which is referred to as integrated injection logic ( _I ² L) and is shown in FIGS. 16 or 17 is shown;
• FIG. 16 shows an I ² L circuit whose gate signal delay is to be regulated or optimized according to the invention by using a device for power control, which includes the voltage-controlled oscillator according to FIG. 15;
• FIG. 17 shows a second I2h circuit, the gate signal delay of which is to be regulated or optimized according to the invention by using a device for power control, which includes the voltage-controlled oscillator according to FIG. 15;
• 18 shows a block diagram of a voltage-controlled oscillator for use according to the invention in the device for controlling the power of a system in which the circuits, the signal delay of which is to be regulated or optimized, belong to the circuit family of field-effect transistors (a member of which is shown in FIG. 19). ;
• 19 shows a field effect transistor circuit whose gate signal delay can be regulated or optimized according to the invention by using a device for power control, which includes the voltage controlled oscillator according to FIG.

Fig. 1 shows a typical curve of the signal delay of a logic gate as a function of the electrical power supplied, which all logic families have. Current practice is to operate a logic gate at a certain power level. This is evidenced by the many publications of circuits designed to maintain a certain power level or current setting in the logic gate circuit. However, the thought of trying to maintain a certain power or current setting leads to various problems. The first problem relates to the manufacture of the Semiconductor devices. During the normal course of semiconductor device manufacturing, there are minor disruptions to the manufacturing process. These slight deviations influence the position of the curve, which represents the dependence of the switching speed as a function of the power, as shown in FIG. 1. As the curve changes, the gate signal delay changes. The second problem is the auxiliary circuitry designed to maintain a certain level of power or current in the logic circuit. These circuits are also subject to variations in the manufacturing process and at the same time are sensitive to changes in supply voltages and temperature changes in the system. The end result is a logic gate, the performance of which is regulated within narrow limits, but whose signal delay can vary considerably.

Fig. 2 shows the method according to the invention. The gate signal delay is controlled while the logic gate power is allowed to vary so that when the switching speed curve changes depending on the power due to the manufacturing process, temperature or power supply, the gate signal delay remains constant while performance varies.

Figure 3 illustrates the implementation of the invention at the system level. The system can consist of n semiconductor chips. There is a control circuit for the signal delay on each semiconductor chip, which regulates the power supplied to the remaining gates on the semiconductor chip. In this example, the logic gates shown in Fig. 10 are used, which are implemented in the technology of the current transfer switch. The VCS signal is used to control the power in the logic gate by regulating the Regulate the voltage of the power source. The clock signal shown in FIG. 3 reaches the control circuit for the signal delay of each of the n semiconductor chips. Each clock signal contains the information regarding the switching speed or the timing for the control circuit for signal delay. The control circuit compares this clock signal with a signal provided by a circuit which senses the switching speed and which is located on the semiconductor chip and then regulates the power in the logic gates on the semiconductor chip so that the same switching speed is obtained as that prescribed by the clock signal. In this way, the switching speed from semiconductor chip to semiconductor chip is the same, while the power supplied varies from semiconductor chip to semiconductor chip. Since all semiconductor chips in the system have logic gates with the same switching speed, the system designer no longer needs to provide semiconductor chips with a lower and higher switching speed for a specific gate path. All semiconductor chips have the same gate signal delay. It should be noted that the system clock is preferably used as the clock signal. However, it can be seen from the more detailed description below that the clock signal supplied to the controller for the signal delay can also be different from the system clock.

Fig. 4 shows an embodiment for the control of the signal delay. The controller for the signal delay consists of the phase comparison circuit, the low-pass filter, the buffer circuit, the voltage-controlled oscillator and the level shift circuit. The phase comparison circuit compares the clock signal supplied to the semiconductor chip from the outside with the level-shifted signal of the voltage-controlled oscillator. The output signals U and D generate a signal that has a pulse width that is directly proportional to the phase difference of the input clock signal and the level-shifted signal of the voltage controlled oscillator. This pulse width sensitive signal has the same frequency as the input clock signal. The signals U and D reach the low-pass filter, which removes the carrier frequency of the input clock signal from this signal. The output signal VCS 'is a DC voltage which is proportional to the pulse width of the input signal for the low-pass filter. The signal VCS 'arrives at the buffer circuit. The buffer circuit is an amplifier with a gain factor of 1. It has a high-resistance input for the signal VCS 'of the low-pass filter. The buffer circuit also has a low impedance output to feed the VCS signal to the other gates on the semiconductor chip and the circuit of the voltage controlled oscillator. The VCS signal regulates the performance of the logic gates on the semiconductor chip. In this particular embodiment (see Fig. 10), the signal VCS regulates the current through the current source of the logic gate. With increasing signal VCS, the power in the circuit increases, whereas with decreasing signal VCS, the power in the circuit decreases. The voltage controlled oscillator generates a signal RLF, the frequency of which is proportional to the input signal VCS. The circuit of the voltage-controlled oscillator should have the same dependency of the switching speed on the power as the logic gates in the rest of the semiconductor chip. Therefore, when the signal VCS changes the signal delay of the logic gate, the frequency of the voltage controlled oscillator also changes. The output signal RLF is a periodic logic signal. The output signal VR is the logical threshold above which the signal RLF changes. These two signals go to the level shift circuit which produces an output signal, the level shifted signal of the voltage controlled oscillator which has the same logic level as the input clock signal and the same frequency as the signal RLF. It can be seen that this arrangement of phase comparison circuit, low pass filter, buffer circuit, voltage controlled oscillator and level shift circuit represents a phase locked loop. By using this phase locked loop, the voltage controlled oscillator tends to synchronize with the input clock signal. This mode of operation of the phase locked loop tends to fluctuate in the manufacturing process, temperature changes and changes in the voltage supply within the capability of the voltage controlled oscillator _. to synchronize with the clock signal, not to be affected. Once the voltage controlled oscillator was synchronized, the power on the remaining logic gates on the semiconductor chip was changed so that the gate signal delay is now controlled by the frequency of the input clock signal. It can be seen that the input clock signal now supplied to all semiconductor chips at the system level controls the gate signal delay on each individual semiconductor chip, regardless of the power that the logic gate consumes or the temperature of the semiconductor chip or the process fluctuations occur from lot to lot in the manufacture of the semiconductor chips.

The phase comparison circuit also generates signals B, C, U and D, which in conjunction with signals U and D provide an indication of whether the frequency of the signal supplied by the voltage controlled oscillator is equal to the clock frequency. This display is used to determine whether the semiconductor chip has the AC performance that is dictated by the clock. The AC measurement circuit generates three signals - HIGH, LOW and EQUAL. The signal "HIGH" indicates that the Fre frequency of the voltage-controlled oscillator is higher than the clock frequency. The "LOW" signal indicates that the frequency of the voltage controlled oscillator is lower than the clock frequency. The "SAME" signal indicates that the frequency of the voltage controlled oscillator is equal to the clock frequency.

It can also be seen that the phase comparison circuit, the low pass filter, the buffer circuit and the level shift circuit do not have to be on the semiconductor chip itself. The important circuitry that must be on the semiconductor chip is the voltage controlled oscillator, which senses the switching speed or gate signal delay that is present on the semiconductor chip. The other four logic circuit blocks (FIGS. 5, 6, 7 and 9) can be present on another semiconductor chip outside the semiconductor chip or can also be composed of discrete components. However, the voltage controlled oscillator must be on the same semiconductor chip as the logic gates to be controlled.

Fig. 5 shows a logic block diagram of the phase comparison circuit and the AC measurement circuit. The phase comparison circuit can be a commercially available one. In this example, the logic gates are composed of the circuits of FIG. 12. The function of this logic circuit is to compare the phase of the two input signals, the system clock supplied externally to the semiconductor chip and the level-shifted signal of the voltage-controlled oscillator, and to generate a logic signal at the outputs U and D which has the same frequency as the input signals and has a pulse width that is proportional to the phase difference of the two input signals.

The logic elements used in the AC measuring circuit are also composed of the circuits according to FIG. 12. The function of this circuit is to determine whether the frequency of the voltage controlled oscillator signal is equal to, greater than or less than that of the clock signal. This is accomplished by using different clock signals within the phase comparison circuit to determine whether the condition of equality or inequality exists.

5 that the "LOW" signal is generated by the NOR operation of the U, D and C signals. It can also be seen from FIG. 5 that the "FAST" signal is generated by the NOR operation of the U, D and B signals. As can be seen from Fig. 5, the "EQUAL" signal is generated by NOR linking the HIGH and LOW signals.

Fig. 6 shows the circuit diagram of the low-pass filter. The two input signals U and D are added and filtered to remove the carrier frequency. The output signal VCS 'is a direct current signal. The cut-off frequency of the low-pass filter is chosen so that the ripple of the signal VCS 'is minimal and at the same time the stability of the phase-locked loop is maintained.

11 shows a reference voltage generator. The voltage is generated by the components TA, TB, TC and TD. The component TE is used to supply the reference voltage BREF to the other circuits. The reference voltage of this circuit serves as a logic threshold for the logic gates of Fig. 12 and for the phase comparison circuit of Fig. 5. The reference voltage VREF is also used by the level shift circuit of Fig. 9. This voltage serves as the reference voltage for the logic signals.

Fig. 8 shows the circuit of the voltage controlled oscillator. It consists of N logic gates, which are shown individually in FIG. 10 and are connected to one another in a loop arrangement, the output of gate 1 leading to the input of gate 2 and this continuing until gate N, the output of which on the input of gate 1 is returned. This circuit oscillates at a frequency which is dependent on the gate signal delay of the N elements. The actual gate signal delay of each element is controlled by the VCS signal. It can be seen that the VCS signal changes the performance of each gate. Any change in the gate signal delay results in a change in the frequency of the RLF signal. As the VCS signal increases, the frequency of the RLF signal also increases, and as the VCS signal decreases, the frequency of the RLF signal also decreases. The output signal of this circuit passes to RLF Pegelverschiebun ^g sschal- processing. The VR signal is the logic reference signal of the gates in this loop.

Fig. 9 shows the level shift circuit. Their purpose is to change the logic level of the RLF signal so that signals are obtained which are compatible with the clock signal shown in Fig. 4A generated outside the semiconductor chip. The signal RLF changes between the voltage levels above the signal VR and below this signal. The elements TA, TB, TC and TD form a logic gate configuration in which the current through the element TC flows either through the element TA or through the element TB, depending on the input voltage RLF. The signal VREF, which is derived from the circuit of FIG. 11, serves two functions. The first function is to generate a reference current for the current source elements TC and TD. This reference current is generated using elements G, TF and E and the elements TC and D supplied to the current source using a current mirror configuration, the connection between TF and TC.

The second function of voltage VREF is to clamp the level-shifted output signal of the voltage controlled oscillator using diodes J and H so that the output signal is either above the voltage VREF by the voltage drop across a diode or the voltage drop across a diode below this voltage . The mode of operation of the circuit according to FIG. 9 is controlled by the input signal RLF. When the voltage of the input signal is above the voltage VR, the current through element TC flows through element TA. The current through element K flows through element J, which generates a voltage for the level-shifted signal of the voltage-controlled oscillator that is greater than the signal VREF by the voltage drop across the diode. When signal RLF is below voltage VR, current flows through element TC through element TB, causing all of the current through element K to flow through element TB, and current from signal VREF is drawn through element H. This produces a low level signal which is below the voltage VREF by the voltage drop across a diode at the output for the level shifted signal of the voltage controlled oscillator. It can be seen that the operation of this circuit consists in shifting the reference voltage of the logic input signal RLF to the value of the reference voltage VREF. The output signal has the same frequency as the signal RLF, but has a different logic level.

Fig. 12 shows the circuit diagram of an internal gate used in the phase comparison circuit of Fig. 5. The operation of this gate is similar to that of a gate ters, which is carried out in power transfer technology. The reference voltage VREF is generated by the circuit of FIG. 11. The output voltages are clamped levels that are either above or below the signal VREF by the voltage drop across a diode. The circuit of Figure 12 is shown with only two input transistors TA and TB, but other additional transistors can be connected in the same way to form a three or four input logic gate. A voltage at input 1 or at input 2, which is above the input reference voltage VREF, conducts the current through this transistor and pulls the output potential 0 by the voltage drop across a diode below the voltage VREF. The output voltage 0 is higher than the voltage VREF by the voltage drop across a diode. If the voltages at inputs 1 and 2 are both less than the voltage VREF, the current flows through the element TC and pulls the signal at the output 0 of the diode below the value VREF. The output signals in the circuit are clamped by diodes to provide the correct voltages to control the remainder of the phase control circuit shown in FIG. 4.

FIG. 10 is the circuit diagram of a typical logic gate used in both the voltage controlled oscillator (FIG. 8) and the logic gates in the rest of the semiconductor chip, as indicated in FIG. 4. The elements TD and E form a current source which is controlled by a signal VCS. The signal VCS therefore directly controls the power within the logic gate and thus its switching speed. The logic gate is shown with two inputs, transistors TA and TB, but additional transistors can be provided for further inputs, which are connected in the same way. The exits φ and 0 are on via diodes the VR signal is clamped so that the output voltages are either above or below the VR signal by the voltage drop across a diode. The input voltages 1 and 2 of the circuit are either above or below the signal VR, so that when either the input signal 1 or the input signal 2 is above the voltage VR, the current flows through the element TD through the conductive transistor. The output voltage 0 is then around the voltage drop across a diode below the voltage VR. If neither the input voltage 1 nor the input voltage 2 are above the voltage VR, then the output voltage 0 is one diode voltage drop above the voltage VR. Similarly, when both input signals 1 and 2 are below voltage VR, the current through element TD flows through element TC so that signal 0 is below the voltage VR by one diode voltage drop. If both inputs 1 and 2 have the high potential, then the output voltage φ is lower than the voltage VR by a diode voltage drop. The VR signal is applied to all of the logic gates on the semiconductor chip controlled by the signal delay regulator, including those logic gates of the voltage controlled oscillator of Fig. 8, so that all of these logic gates use the same threshold voltage.

The circuit of Fig. 7 is a buffer circuit. It represents a high input impedance for the signal VCS 'and a low output impedance for the signal VCS, so that this signal can be routed to all logic gates over the entire semiconductor chip, as shown in FIG. 4. The circuit is a differential amplifier, which has a gain factor of 1. The elements TA, TB and D form the differential input stage of the circuit. The input signal VCS 'is compared to the signal at node 1 using elements TA, TB and D chen. The elements TE, TF, G, TH, J and K provide the necessary signal conditions so that the signal at node 1 is identical to the input signal VCS '. The TM and N elements provide additional output buffering and voltage shifting to provide a VCS signal which is applied to the logic gates and the voltage controlled oscillator as shown in FIG.

FIG. 4A shows a series of waveforms and potential levels which are to be considered in connection with the explanation of the mode of operation of the controller for the signal delay according to FIG. 4. 4 are the waveform W1 (clock) and the waveform W2 (level-shifted signal of the voltage-controlled oscillator). As shown in Fig. 4A, each of these waveforms has a part of each pulse period in which the voltage waveform is larger than the voltage VREF and a part in which the level is lower than the voltage VREF. 4A also shows that the curves W1 and W2 have the same periodicity or pulse repetition frequency. However, the waveform W1 of the clock pulses in phase leads the level-shifted waveform W2 of the voltage-controlled oscillator. The output signal U of the phase comparison circuit is a level which is constant over time and is denoted by L1 in FIG. 4A. Note that the size of L1 is larger than that of VREF. 4A that the output signal D is the curve shape W3. The curve shape W3 is a periodic pulse train that has a pulse repetition frequency that is equal to that of the curve shape W1. It can also be seen that the duration of the pulses in the curve W3 is the same or directly proportional to the phase difference between the curves W1 and W1. As can be seen from Fig. 4A, the signal VCS 'is on constant DC voltage level L2 over time. The magnitude L2 of the signal VCS 'is a function of the average potential of the signals U (L1) and D (curve shape W3) and the pulse duration of the curve shape W3. As can be seen from the earlier explanation of the function of the buffer circuit (FIG. 7), the signal VCS has a size L3 which is below the size L2 of the signal VCS 'by the base emitter voltage of a transistor. From Fig. 4A it also appears that the size L2 of the signal VCS 'by an increase, for. B. Δ, above the magnitude of the voltage VREF, and that the signal VCS, whose level has been shifted by a DC voltage of 0.8 to 1 volt, is also by the increase A above the voltage VREF - 0.8 volts. The curve W4 represents a periodic pulse train that corresponds to the signal RLF of FIGS. 4 and 8 corresponds. The magnitude of the voltage VR is also shown. It can be seen from FIG. 4A that the curve shape W2 (level-shifted signal of the voltage-controlled oscillator) and the curve shape W4 (RLF) correspond to one another in terms of the periodicity and the pulse duration. As is apparent from Fig. 4, the waveform W4 (RLF) with the _P e-gelverschiebungsschaltung (FIG. 9) moved and becomes the level-shifted signal of the voltage controlled oscillator, which is the output signal of the level shift circuit of FIG. 4.

The figures 4B, -4C and 4D show a "series of waveforms and potential levels to be considered in conjunction with the explanation of the operation of the phase comparison circuit and the AC measurement circuit of Fig. 5. These three figures (4B, 4C and 4D) show the Curves and potential levels for the conditions that the frequency of the voltage controlled oscillator is lower, higher or equal to the clock frequency.

Fig. 4B shows a series of waveforms and potential levels, which in connection with the explanation of the effect 5, the phase comparison circuit and the AC measuring circuit according to FIG. 5 are to be considered for the example that the frequency of the voltage-controlled oscillator is lower than the clock frequency. 5 are the waveforms W5 (clock) and W6 (level-shifted signal of the voltage-controlled oscillator). As can be seen from FIG. 4B, the curve W5 has a smaller periodicity than the curve W6, therefore the curve W6 has a lower frequency than the curve W5. It can be seen from FIG. 4B that the signal U is the curve shape W7. The curve W7 is a periodic pulse train that was generated from the curves W5 and W6. It should be noted that the transition of the curve W7 from a level below the voltage VREF to an above level corresponds to the transition of the curve W5 from a level below the voltage VREF to an above level. The transition of the curve W7 from a level above the voltage VREF to an underlying level corresponds to the transition of the curve W6 from a level below the voltage VREF to an above level. 4B that the signal B is the curve W8 and the signal C is the curve W9. The curves W8 and W9 are generated from the curves W5 and W6. The curves W8 and W9 have periodicities and pulse durations which depend on the logical levels of the curves W5 and W6 and on their level changes. From Fig. 4B it can be seen that the signal D is a DC level which is denoted by L4. 4B that the HIGH signal is a DC level,

which is labeled L5. 4 that the signal LOW is represented by the curve W10 and the signal EQUAL by the curve W11. From the earlier explanation of the AC measurement circuit, it is known that the level L5 corresponding to the HIGH signal is the result of the NOR operation of the waveforms W7 and W8 and the level L4. From the same explanation, it is known that the curve W10 corresponding to the LOW signal is the result of the NOR operation of the curve W9, the inversion of the curve W7 and the inversion of the level L4. From the same explanation of the AC measuring circuit it is known that the curve W11, which corresponds to the signal EQUAL, is the result of the NOR operation of the curve profiles W10 and the level L5.

Fig. 4C shows a series of waveforms and potential levels, which are to be considered in connection with the explanation of the operation of the phase comparison circuit and the AC measuring circuit according to Fig. 5 for the example in which the frequency of the voltage-controlled oscillator is higher than the clock frequency. 5 are the waveforms W12 (clock) and W13 (level-shifted signal of the voltage-controlled oscillator). As 4C apparent from the Fig., The waveform W12 has a longer periodicity than the curve W13, hence the curve has W13 a higher frequency 12 as the curve from Fig. 4 _C can be seen that the signal D of the curve W16 is. This curve shape is a periodic pulse train that results from the curve shapes W12 and W13 is generated. It should be noted that the transition of curve shape 16 from a level below voltage VREF to a higher level corresponds to the transition of curve shape W12 from a level below voltage VREF to a higher level. A transition in the curve W16 from a level above the voltage VREF to a level below this voltage corresponds to the transition of the curve profile W13 from a level below the voltage VREF to a level above this voltage. It can be seen from FIG. 4C that signal B is curve shape W14 and signal C is curve shape W15. The curves W14 and W15 are generated from the curves W12 and W13. The curves W14 and W15 have periodicities and pulse durations which depend on the logical levels of the curves W12 and W13 and on the changes in these levels. It can be seen from FIG. 4C that the signal U is a DC level, which is denoted by L6. It can be seen from Fig. 4C that the HIGH signal is a curve represented by W17. It can also be seen from this figure that the LOW signal is represented by the level L7 and the EQUAL signal is represented by the curve shape W18. As can be seen from the earlier explanation of the AC measuring circuit, the curve W17, which corresponds to the signal HIGH, is the result of a NOR operation of the curves W16 and W14 and the level L6. The level L7, which corresponds to the signal LOW, is the result of a NOR operation of the curve shape W15, the inverted curve shape W16 and the inverted level L6. The curve shape W18, which corresponds to the signal SAME, is the result of the NOR operation of the curve shape W17 and the level L7. _'

Fig. 4D shows a series of waveforms and potential levels, which are to be considered in connection with the explanation of the operation of the phase comparison circuit and the AC measuring circuit according to Fig. 5 in the event that the frequency of the voltage controlled oscillator is equal to the clock frequency. The input signals for the phase comparison circuit according to FIG. 5 are the curve profile W19 (clock) and the curve profile 20 (level-shifted signal of the voltage-controlled oscillator). As FIG. 4D shows, the curve W19 has the same periodicity as the curve W20, therefore the curve W20 has the same frequency as the curve w19. FIG. 4D shows that the signal U is the curve shape W21 that was generated from the curve shapes W19 and W20. It should be noted that in the case of the curve shape W21, a transition from a level below the voltage VREF to an overlying level corresponds to a transition of the curve shape W19 from a level below the voltage VREF to an overlying level. In the case of the curve W21, the transition from a level above the voltage VREF to an underlying level corresponds to the transition of the curve profile W20 from a level below the voltage VREF to an overlying level. It can be seen from FIG. 4D that signal B is curve shape W22 and signal C is curve shape W23. The curves W22 and W23 are generated from the curves W19 and W20. The curves W22 and W23 have periodicities and pulse durations which depend on the logical levels of the curves W19 and W20 and their changes. From Fig. 4D it can be seen that the signal is an equal current level, which is designated L8. It can also be seen from FIG. 4D that the HIGH signal is a DC current level which is denoted by L9. It can also be seen that the LOW signal is represented by level L10 and the EQUAL signal is represented by level L11. As can be seen from the earlier explanation of the AC measuring circuit, the level L9, which corresponds to the signal HIGH, is the result of a NOR operation of the curves W21 and W22 and the level L8. The level L10, which corresponds to the signal LOW, is the result of the NOR combination of the curve shape W23, the inversion of the curve shape W21 and the inversion of the level L8. The level L11, which corresponds to the signal SAME, is the result of a NOR operation of the levels L10 and L9.

As explained earlier, it should be noted that the signal VCS (L3) is the output of the buffer circuit of the regulator for the signal delay shown in FIG. This output signal VCS is used according to the invention to determine the point on the curve which represents the gate signal delay as a function of the power at which the logic circuits operate. This variable is therefore decisive for the constant switching speed or gate signal delay of the logic circuits which receive the signal VCS.

Fig. 13 shows the circuit of the voltage controlled oscillator used, which is constructed in transistor-transistor logic. The input signal VCS to the circuit controls the power in each logic gate (Fig. 14). As explained earlier, changing the power in the logic gates of the voltage controlled oscillator results in a frequency change in the signal RLF. Implementation by transistor-transistor logic in this preferred embodiment can make the level shift circuit (Fig. 9) unnecessary for changing the voltage levels of the RLF signal. If a level shift circuit is not required, as can be easily determined by a person skilled in the art, the signal RLF replaces the level shifted signal of the voltage controlled oscillator as an input signal for the 0 phase comparison circuit (FIG. 5). Likewise, the VR signal and the level-shifted signal of the voltage controlled oscillator would be removed from the circuit since they are no longer required. However, if it is determined by those skilled in the art that a level shift circuit is needed, the new level shift circuit may not require the VR signal to produce a level shifted signal from the voltage controlled oscillator that is compatible with the comparison circuit. It is also known to those skilled in the art that the use of transistor-transistor logic or any other logic in the comparison circuit may require additional circuits in order for the signals U and D (Fig. 4) to be signals with the correct source impedances and / or voltage / current levels and / or temperature responses appear and corrections can be made to the power supply so that the control circuit (FIG. 4) works correctly for the signal delay.

Fig.14 is an example of a gate in transistor-transistor logic that follows in the voltage controlled oscillator Fig. 13 can be used. Other known configurations of transistor-transistor logic can also be used. The signal VCS generated by the buffer circuit or the power amplifier (FIG. 7) passes to all logic gates of the voltage-controlled oscillator (FIG. 13) and to the logic gates in the remaining part of the semiconductor chip, which is not shown, which the 0 comparison circuit (FIG. 5) may or may not contain. The control signal VCS changes the power in the logic gate (Fig. 14). As the VCS signal increases, the power supplied to the logic gate increases, resulting in a decrease in the gate signal delay. In the same way, when the signal VCS decreases, the power supplied to the logic gate decreases, which results in an increase in the gate signal delay. It will be apparent to those skilled in the art that the voltage level of the VCS signal should only be increased to the level at which a further increase in the voltage level does not result in a further decrease in the gate signal delay.

15 shows the voltage-controlled oscillator used in the configuration of the integrated injection logic (I ² _L ). The input signal for the circuit, the signal VCS in the logic gate according to FIG. 16 or the signal VCS ″ in the logic gate according to FIG. 17, controls the power in each logic gate. As previously explained, changing the power in the logic gates of the voltage controlled oscillator results in changing the frequency of the RLF signal. As previously discussed in the description of the use of transistor-transistor logic in the voltage controlled oscillator, the level shift circuit is required or not, the level shifted signal of the voltage controlled oscillator and / or the signal VR may or may not be required, and additional circuitry for proper operation of the signal delay controller (Fig. 4) may or may not be necessary.

In Figs. 16 and 17 show two examples of controlling the power of a 1 ² L gate. Figure 16 shows that the current through element TA is controlled by a variable voltage VCS. The voltage VCC has a fixed value, so that when the voltage of the signal VCS decreases, the power supplied to the logic gate increases, and thereby the signal delay of the logic gate decreases. As the voltage of the VCS signal increases, the power supplied to the logic gate decreases, which in turn increases the signal delay of the logic gate. It will be apparent to those skilled in the art that to achieve the proper operation of the signal delay regulator circuit (FIG. 4), the signals U and D generated by the comparison circuit (FIG. 5) must be logically inverted (U and D) .

Fig. 17 shows an I ² L gate that is controlled by a voltage change across element B. The base of element TA is connected to ground so that when signal VCS changes, the current through element TA changes. As the voltage of the VCS signal increases, the power in the logic gate increases and its signal delay decreases. As the voltage of the VCS signal decreases, the power supplied to the logic gate also decreases, and with it the signal delay. It should be noted that for these special logic gates, the voltage VCS is not distributed to the voltage controlled oscillator and the remaining logic gates on the semiconductor chip. Instead, the signal VCS '' is distributed to the voltage controlled oscillator and the remaining logic gates on the semiconductor chip.

Fig. 18 shows the circuit of a voltage controlled oscillator that can be used in an embodiment with field effect transistors. The input signal VCS controls the power supplied to each logic gate (Fig. 19) leads. As explained earlier, a change in the power supplied to the gates of the voltage controlled oscillator results in a change in the frequency of the signal RLF. Increasing the power supplied to the logic gate (Fig. 19) decreases the signal delay and decreasing the power supplied to the logic gate increases its signal delay.

• 1. Es ist nicht notwendig, einen Phasenregelkreis zu verwenden. Es kann ein Frequenzregelkreis verwendet werden.
• 2. Es ist nicht notwendig, den Systemtakt zu verwenden. Es kann ein eigener Taktgeber verwendet werden.
• 3. Inverter sind nicht notwendigerweise die einzige Art von Gattern, die für den spannungsgesteuerten Oszillator verwendet werden können.
• 4. Der Frequenzvergleich kann durch RRC-Filter und eine Spannungsvergleichsschaltung durchgeführt werden.
• 5. Es kann mehr als ein Regler auf einem Halbleiterchip vorhanden sein.
• 6. Die Pufferschaltung oder der Leistungsverstärker kann einen von 1 verschiedenen Verstärkungsfaktor haben.
• 7. Das Tiefpaßfilter kann sich in der Pufferschaltung befinden.

The following are a number of changes and modifications to the invention that can be made without departing from the scope of the invention:

• 1. It is not necessary to use a phase locked loop. A frequency control loop can be used.
• 2. It is not necessary to use the system clock. A separate clock can be used.
• 3. Inverters are not necessarily the only type of gates that can be used for the voltage controlled oscillator.
• 4. The frequency comparison can be carried out by RRC filters and a voltage comparison circuit.
• 5. There may be more than one controller on a semiconductor chip.
• 6. The buffer circuit or power amplifier can have a gain factor other than 1.
• 7. The low pass filter can be located in the buffer circuit.

• Bei jeder Schaltung mit einer Abhängigkeit der Schaltgeschwindigkeit von der Leistung kann die Schaltgeschwindigkeit eingestellt oder geregelt werden durch Verändern der der Schaltung zugeführten Leistung.

The concept on which the invention is based can be summarized as follows:

• For each circuit with a dependence of the switching speed on the power, the switching speed can be set or regulated by changing the power supplied to the circuit.

The device by which the power can be varied is brought about by a feedback loop which essentially contains the signal of an oscillator (which is composed of the gates to be controlled), a reference signal (clock), a device for comparing the reference and oscillator signals that generate an error signal and a device for converting the error signal into the appropriate control signal.

The oscillator can be constructed in any way from a number of ways known to those skilled in the art. The use of a voltage controlled oscillator has been described for explanation. A clock signal was selected as the reference signal.

The comparison circuit, which functions as a frequency / voltage converter or a frequency; current converter, can be any device known to those skilled in the art, such as a pulse width modulator, D flip-flops, digital-to-analog converter or phase locked loops. The explanation of the use of a phase comparison circuit operating as a phase locked loop has been described in particularly great detail.

Claims (6)

1. Circuit for matching the signal delay times of interconnected semiconductor chips to a desired value, which is characterized by the frequency of an externally supplied pulse train and is achieved by means of a control circuit provided on each semiconductor chip by changing the electrical power supplied to the semiconductor chip, which control circuit is a controllable oscillator and contains a phase comparison circuit in which the frequency of the controllable oscillator is compared with that of the externally supplied pulse train and readjusted in the event of a deviation until synchronization, characterized in that an additional circuit is also connected to the phase comparison circuit and provides a signal at its outputs as to whether the frequency of the controllable oscillator, which characterizes the relative signal delay time of the circuits of the semiconductor chip, is higher, equal or lower than that of the externally supplied pulse train. 2. Circuit according to claim 1, characterized in that the additional circuit is connected to first outputs (U, D) of the phase comparison circuit, to which a low-pass filter following the phase comparison circuit is connected, and to second outputs to which the phase comparison circuit signals (U, D) supplies, which are complementary to those fed to the low-pass filter, and to third outputs (B, C), at which internal signals of the phase comparison circuit are available. 3. A circuit according to claims 1 and 2, characterized in that the supplementary circuit is constructed erknüpfungsgliedern of three _V, the electrical signals present at the outputs with respect to the frequency of the controllable oscillator and in which the outputs of two gates also to the third, the frequency equality indicating, are connected. 4. Circuit according to claims 1 to 3, characterized in that the additional circuit is constructed from NOR gates. 5. Circuit according to claims 1 to 4, characterized in that the electrical signal at the output of the additional circuit is present as an electrical potential. 6. Circuit according to claims 1 to 4, characterized in that the electrical signal is present as an electrical current at the output of the additional circuit.

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