EP0057351B1 - Circuit for delay normalisation of interconnected semiconductor circuits - Google Patents

Description

The invention relates to a circuit for matching the signal delay times of interconnected semiconductor chips with respect to a setpoint value, which is characterized by the frequency of an externally supplied pulse train and is achieved by means of a control circuit provided on each semiconductor chip by changing the electrical power supplied to the semiconductor chip. For this purpose, the control circuit contains a controllable oscillator and a phase comparison circuit in which the frequency of the controllable oscillator is compared with that of the first pulse train supplied and, in the event of a deviation, is readjusted until synchronization.

The current method of circuit design is to design logic circuits and regular arrangements out of them that operate at a certain power level. There are numerous teachings in the prior art to maintain a certain power level or current level within a logic gate. In particular, in the technology of current transfer switches, additional circuits are provided on a semiconductor chip in order to minimize the change in the current level within the logic gate, while the temperature, the supply voltages and also the influences of the manufacturing process vary from lot to lot. Figure 1 shows a typical signal delay versus power curve with an arrow showing current design practice - choosing a power level, maintaining that power level and accepting the resulting signal delay. The design attempts to minimize changes in operational behavior under a number of conditions. The signal delay curve of a gate as a function of power in Figure 1 can move in any direction and even change its slope. At the same time, the control circuit for the power loss has its own faults. This results in a wide spread of the switching speeds of the logic gates.

Figure 2 shows a curve of gate signal delay as a function of power dissipation and serves to illustrate the preferred design method according to the invention. The switching speed or signal delay of the logic gate is selected and the power loss within the circuit is set so that this switching speed is achieved. This is accomplished by designing circuits on the semiconductor chip that are sensitive to the performance characteristics of the logic circuits or matrix arrays on the chip that are applicable during balancing operations. This special circuit (controller for the signal delay) generates a signal which indicates the behavior of the semiconductor chip (switching speed as a function of the power), which is compared with a periodic reference or clock signal used for the entire system. The comparison generates a signal which regulates the electrical power supplied to the logic and / or matrix circuits on the semiconductor chip and thus the operating behavior. (Namely, the point on the curve indicating the gate signal delay as a function of power, which corresponds to a set gate signal delay). By supplying the reference signal to all of the semiconductor chips in the system, all of these chips have the same relative performance, i. H. the same gate signal delay or switching speed. Since a continuous comparison is made between the reference signal and the signal generated on the semiconductor chip, many variables that influence the operational behavior, such as e.g. B. the power supply, temperature changes, fluctuations in the manufacture of the individual chips, etc. minimized or eliminated.

From European patent application 12 839 it is known to provide a digital control circuit on each chip to match the signal delay times of semiconductor chips. It affects the signal delay time by changing the supply voltage. The digital control circuit contains a comparison circuit in which the signal delay of a clock pulse in a chain of inverters is compared with the very precisely defined clock interval. Depending on the comparison result, the counter reading of a bidirectional counter is increased or decreased by 1. The counter reading is decoded via a decoder, which changes the divider ratio of a voltage divider by connecting or disconnecting one of a plurality of parallel resistors by means of one of a plurality of transistors. This changes the voltage present at the tap of the voltage divider, which is fed to an emitter follower. The voltage emitted by this is supplied to the semiconductor chips as a supply voltage and influences their signal delay time.

European patent application 46 482 also describes a circuit for matching the signal delay times of the logic gates of different semiconductor chips, in which a control circuit for the signal delay is likewise provided on each semiconductor chip. An external clock pulse common to all semiconductor chips is fed to it as a reference signal. The control circuit compares its phase position with that of a pulse train that is supplied by a voltage-controlled oscillator belonging to the control circuit. The voltage obtained and compared as a result of comparison influences the voltage-controlled oscillator until the two pulse trains are synchronized. The increased tension will also Logic gates supplied. It changes their consumption of electrical power so that the desired signal delay, which is a function of the electrical power, is achieved.

The invention, as characterized in the claims, achieves the object of designing a circuit of the aforementioned type in such a way that it also provides an indication of the relative signal delay of a semiconductor chip with respect to a setpoint. As a result, semiconductor chips can be divided into different categories with regard to their relative signal delay and used accordingly.

• Figur 1 eine Kurve, die die Gatter-Signalverzögerung als Funktion der dem Gatter zugeführten elektrischen Leistung darstellt. Die Kurve der Fig. 1 gibt den Zustand nach dem Stand der Technik wieder, bei dem die Leistung festgelegt oder gewählt wird und die Schaltgeschwindigkeit oder die Signalverzögerung der Schaltung der ihr zugeführten Leistung entspricht;
• Figur 2 eine Kurve, die die Gatter-Signalverzögerung als Funktion der Leistung für eine logische Schaltung angibt. Bei der Kurve nach Fig. 2 ist die Gatter-Signal-verzögerung (oder Schaltgeschwindigkeit) jeder aus einer Reihe von logischen Schaltungen auf einem Halbleiterchip (oder auf Halbleiterchips) fest vorgegeben oder wurde beim Schaltungsentwurf festgelegt, und die den logischen Schaltungen zugeführte elektrische Leistung (Strom oder Spannung) entspricht der gewählten oder fest vorgegebenen Schaltgeschwindigkeit ;
• Figur 3 ein Blockdiagramm in dem eine Reihe von Halbleiterchips 1 bis n mit monolithisch integrierten Schaltungen dargestellt sind. Jedes Halbleiterchip enthält einen Regler für die Signalverzögerung und eine Reihe mit ihm verbundener logischer Schaltkreise. In der Zeichnung sind nur drei logische Schaltkreise dargestellt. Die logischen Schaltkreise sind als Blöcke dargestellt, die die Legende « Fig. 10 tragen. Ebenso sind die Verbindungen zwischen den logischen Schaltkreisen auf jedem Halbleiterchip und zwischen den Halbleiterchips, da sie für das Verständnis der Erfindung nicht notwendig sind, nicht dargestellt. Den Fachleuten ist bekannt, daß jedes der Halbleiterchips Hunderte von miteinander verbundenen logischen Schaltkreisen enthalten kann. Bei ihnen kann es sich auch um andere als die in Fig. 10 dargestellten (Stromübernahmeschalter oder emittergekoppelte Logikschaltkreise handeln. Aus der nachfolgenden genaueren Beschreibung ist für den Durchschnittsfachmann ersichtlich, daß das beschriebene Prinzip angewandt werden kann bei der Transistor-Transistor-Logik (T²L), der Dioden-Transistor-Logik (DTL), der integrierten Injektionslogik (1²L) und anderen Technologiefamilien als auch bei Matrixanordnungen. Aus der Fig. 3 ist zu ersehen, daß der Regler 4 für die Signalverzögerung jedes Halbleiterchips das gleiche Taktsignal empfängt. Jeder dieser Regler für die Signalverzögerung erzeugt intern auf dem Halbleiterchip ein diskretes bestimmtes Bezugssignal, das in Zusammenarbeit mit dem Taktsignal den Regler für die Signalverzögerung veranlaßt,. ein eindeutiges Signal VCS zu liefern. Beispielsweise liefert der Regler für die Signalverzögerung des Halbleiterchips 1 (Fig. 3) das Signal VCS1, wogegen der Regler für die Signalverzögerung des Halbleiterchips 2 das Signal VCS2 (nicht dargestellt) liefert und der Regler für die Signalverzögerung des Halbleiterchips n liefert das Signal VCSn. Weiter weisen die Größen der Signale VCS1, VCS2, VCSn nicht notwendigerweise eine feste Beziehung zueinander auf. Die Größe oder die Werte jedes der Potentiale VCS1, VCS2, ... bis VCSn diktiert ein Punkt auf der Kurve, die die Gatter-Signalverzögerung als Funktion der Leistung wiedergibt, die diesem Halbleiterchip zugeordnet ist und für die gewünschte Schaltgeschwindigkeit sorgt ;
• Figur 4 das Blockdiagramm eines erfindungsgemäßen Reglers für die Signalverzögerung (Vorrichtung zur Leistungsregelung). Aus Fig. 3 ist ersichtlich, daß jedes Halbleiterchip einen Regler für die Signalverzögerung enthält. Die Schaltung des Reglers für die Signalverzögerung kann für jedes Halbleiterchip die gleiche sein. Jeder der Blöcke in Fig. 4 schließt eine Legende und eine Figurenzahl ein. Beispielsweise weist der Phasenkomparatorblock die Legende « Phasenvergleichsschaltung » und « (Fig. 5) » auf, wogegen der spannungsgesteuerte Oszillator die Legende trägt « (RLF) und « (Fig. 8) ». Diese Legenden bedeuten, daß die Schaltung der Vergleichsschaltung in Fig. 5 dargestellt ist und die Schaltung des spannungsgesteuerten Oszillators in Fig. 8. In dem Ausführungsbeispiel der Erfindung enthält der Regler für die Signalverzögerung eine « Phasenvergleichsschaltung (Fig. 5) », ein « Tiefpaßfilter (Fig. 6) », eine « Pufferschaltung oder einen Leistungsverstärker (Fig. 7) », einen « spannungsgesteuerten Oszillator RLF (Fig. 8) » und eine « Pegelverschiebungsschaltung (Fig. 9) », die so miteinander verbunden sind, wie das in Fig. 4 dargestellt ist. Anstelle des spannungsgesteuerten Oszillators kann auch ein stromgesteuerter Oszillator verwendet werden ;

• Figur 4A idealisierte Kurvenverläufe und Potentialpegel, die in Verbindung mit der Erklärung der Wirkungsweise des Reglers für die Signalverzögerung (Fig. 4) zu betrachten sind ;
• Figur 4B idealisierte Kurvenverläufe und Potentialpegel, die in Verbindung mit der Erklärung der Wirkungsweise der Phasenvergleichsschaltung und der Wechselstrom-Meßschaltung (Fig. 5) zu betrachten sind für das Beispiels eines pegelverschobenen Signals des spannungsgesteuerten Oszillators, das eine niedrigere Frequenz als die Taktfrequenz besitzt ;
• Figur 4C idealisierte Kurvenverläufe und Potentialpegel, die in Verbindung mit der Erklärung der Wirkungsweise der Phasenvergleichsschaltung und der Wechselstrom-Meßschaltung (Fig. 5) zu. betrachten sind für ein Beispiel eines pegelverschobenen Signals des spannungsgesteuerten Oszillators, das eine höhere Frequenz als die Taktfrequenz aufweist ;
• Figur 4D idealisierte Kurvenverläufe und Potentialpegel, die in Verbindung mit der Erklärung der Wirkungsweise der Phasenvergleichsschaltung und der Wechselstrom-Meßschaltung (Fig. 5) für das Beispiel eines pegelverschobenen Signals des spannungsgesteuerten Oszillators zu betrachten sind, das die gleiche Frequenz wie die Taktfrequenz besitzt ;
• Figur 5 ein logisches Blockdiagramm einer handelsüblichen Phasenvergleichsschaltung, die gemäß der Erfindung in dem Regler für die Signalverzögerung (Fig. 4) benutzt werden kann. Ferner sind drei Verknüpfungsglieder dargestellt, die als Wechselstrom-Meßschaltung verwendet werden. Die Eingangssignale für die Wechselstrom-Meßschaltung, die die Signale HOCH, NIEDRIG und GLEICH liefert, stammen von der Phasenvergleichsschaltung ;
• Figur 6 eine Tiefpaß-Filterschaltung, die gemäß der Erfindung in dem Regler für die Signalverzögerung (Fig. 4) verwendet werden kann ;
• Figur 7 eine Pufferschaltung, die gemäß der Erfindung in dem Regler für die Signalverzögerung (Fig. 4) verwendet werden kann. Es sei bemerkt, daß die Pufferschaltung die Funktion eines Leistungsverstärkers erfüllt und auch so bezeichnet werden kann ;
• Figur 8 einen spannungsgesteuerten Oszillator (RLF), der gemäß der Erfindung in dem Regler für die Signalverzögerung (Fig. 4) verwendet werden kann. Es sei bemerkt, daß der spannungsgesteuerte Oszillator vorzugsweise eine Reihe von logischen Schaltkreisen verwendet, bei denen die Gatter-Signal-verzögerung (oder Schaltgeschwindigkeit) durch den Regler für die Signalverzögerung geregelt werden soll. Bei dem hier offenbarten Ausführungsbeispiel der Erfindung ist der logische Schaltkreis, dessen Gatter-Signalverzögerung (oder Schaltgeschwindigkeit) geregelt werden soll, ein Stromübernahmeschalter (emittergekopelter Logikschaltkreis) wie er in Fig. 10 dargestellt ist. Der spannungsgesteuerte Oszillator kann die Form einer Umlaufschleife annehmen, wie das in Fig. 8 dargestellt ist, in der die Gesamtanzahl der Inverterstufen ungerade ist ;
• Figur 9 eine Pegelverschiebungsschaltung, die gemäß der Erfindung in dem Regler für die Signalverzögerung (Fig. 4) verwendet werden kann ;
• Figur 10 einen als Stromübernahmeschalter ausgeführten Logikschaltkreis (emittergekoppelte Logik), dessen Gatter-Signalverzögerung (oder Schaltgeschwindigkeit) gemäß der Erfindung durch den Regler für die Signalverzögerung geregelt wird ;
• Figur 11 einen Bezugsspannungsgenerator zur Lieferung einer Bezugsspannung VREF, der von der Pegelverschiebungsschaltung nach Fig. 9 und dem internen Gatterschaltkreis nach Fig. 12 benutzt werden kann ;
• Figur 12 einen internen Gatterschaltkreis der Stromübernahme-Schaltkreisfamilie (oder emittergekoppelten Logik), der in der Phasenvergleichsschaltung nach Fig. 5 verwendet werden kann ;
• Figur 13 das Blockschaltbild eines spannungsgesteuerten Oszillators (SGO) für die erfindungsgemäße Verwendung in der Leistungsregelvorrichtung eines Systems, in dem die Schaltkreise, deren Signalverzögerung zu regeln oder zu optimieren ist, der technologischen Schaltkreisfamilie der Transistor-Transistor-Logik angehören (die in Fig. 14 dargestellt ist) ;
• Figur 14 einen Schaltkreis in Transistor-Transistor-Logik, dessen Signalverzögerung gemäß der Erfindung geregelt oder optimiert wird durch Verwendung einer Vorrichtung zur Leistungssteuerung, die den spannungsgesteuerten Oszillator nach Fig. 13 enthält ;
• Figur 15 ein Blockschaltbild eines spannungsgesteuerten Oszillators zur erfindungsgemäßen Verwendung der Vorrichtung zur Leistungssteuerung eines Systems, dessen Schaltkreise, deren Signalverzögerung zu regeln oder zu optimieren ist, der Schaltkreisfamilie angehören, die als integrierte Injektionslogik (12 L) bezeichnet wird und in den Fign. 16 oder 17 dargestellt ist ;
• Figur 16 einen 1²L-Schaltkreis, dessen Gatter-Signalverzögerung gemäß der Erfindung geregelt oder optimiert werden soll durch Verwendung einer Vorrichtung zur Leistungskontrolle, die den spannungsgesteuerten Oszillator nach Fig. 15 einschließt;
• Figur 17 einen zweiter IZL-Schaltkreis, dessen Gatter-Signalverzögerung gemäß der Erfindung geregelt oder optimiert werden soll durch Verwendung einer Vorrichtung zur Leistungssteuerung, die den spannungsgesteuerten Oszillator nach Fig. 15 einschließt;
• Figur 18 ein Blockdiagramm eines spannungsgesteuerten Oszillators zur erfindungsgemäßen Verwendung in der Vorrichtung zur Leistungssteuerung eines Systems, in dem die Schaltkreise, deren Signalverzögerung zu regeln oder zu optimieren ist, der Schaltkreisfamilie aus Feldeffekttransistoren angehören (von der ein Mitglied in Fig. 19 dargestellt ist) ;
• Figur 19 einen Feldeffekttransistor-Schaltkreis, dessen Gatter-Signalverzögerung gemäß der Erfindung geregelt oder optimiert werden kann durch Verwendung einer Vorrichtung zur Leistungssteuerung, die den spannungsgesteuerten Oszillator nach Fig. 18 einschließt.

• Fig. 1 zeigt eine typische Kurve der Signalverzögerung eines logischen Gatters als Funktion der zugeführten elektrischen Leistung, die alle Logikfamilien aufweisen. Augenblickliche Praxis ist es, ein logisches Gatter bei einem bestimmten Leistungspegel zu betreiben. Dies wird bewiesen durch die vielen Veröffentlichungen von Schaltungen, die entworfen wurden, um einen bestimmten Leistungspegel oder eine bestimmte Stromeinstellung in der Schaltung aus logischen Gattern aufrechtzuerhalten. Der Gedanke, zu versuchen, eine bestimmte Leistung oder Stromeinstellung aufrechtzuerhalten, führt jedoch zu verschiedenen Problemen. Das erste Problem bezieht sich auf die Herstellung der Halbleiterbauelemente. Während des normalen Verlaufs der Herstellung von Halbleiterbauelementen gibt es kleinere Störungen des Herstellungsprozesses. Diese geringfügigen Abweichungen beeinflussen die Lage der Kurve, die die Abhängigkeit der Schaltgeschwindigkeit als Funktion der Leistung darstellt, wie das in Fig. 1 gezeigt ist. Wenn die Kurve sich ändert, ändert sich die Gatter-Signalverzögerung. Das zweite Problem stellen die Hilfsschaltungen dar, die dazu entworfen wurden, um einen bestimmten Leistungs- oder Strompegel in dem logischen Schaltkreis aufrechtzuerhalten. Diese Schaltungen sind ebenfalls Abweichungen beim Herstellungsprozeß unterworfen und sind gleichzeitig in dem System empfindlich für Änderungen der Versorgungsspannungen und für Temperaturänderungen. Das Endergebnis ist ein logisches Gatter, dessen Leistung innerhalb enger Grenzen geregelt wird, aber dessen Signalverzögerung beträchtlich variieren kann.
• Fig. 2 zeigt das Verfahren gemäß der Erfindung. Die Gatter-Signalverzögerung wird geregelt, während die Leistung des logischen Gatters variieren darf, so daß, wenn sich die Kurve für die Schaltgeschwindigkeit in Abhängigkeit von der Leistung aufgrund des Herstellungsprozesses, der Temperatur oder der Stromversorgung ändert, die Gatter-Signalverzögerung konstant bleibt, während die Leistung variiert.
• Fig. 3 illustriert die Implementierung der Erfindung auf der Systemebene. Das System kann aus n Halbleiterchips bestehen. Auf jedem Halbleiterchip befindet sich eine Regelschaltung für die Signalverzögerung, die die den restlichen Gattern auf dem Halbleiterchip zugeführte Leistung regelt. In diesem Beispiel werden die in Fig. 10 dargestellten logischen Gatter benutzt, die in der Technologie der Stromübernahmeschalter ausgeführt sind. Das Signal VCS dient dazu, die Leistung in dem logischen Gatter durch Regelung der Spannung der Stromquelle zu regeln. Das in Fig. 3 dargestellte Taktsignal gelangt an die Regelschaltung für die Signalverzögerung jedes der n Halbleiterchips. Jedes Taktsignal enthält die Information bezüglich der Schaltgeschwindigkeit oder der zeitlichen Steuerung für die Regelschaltung zur Signalverzögerung. Die Regelschaltung vergleicht dieses Taktsignal mit einem Signal, das von einer auf dem Halbleiterchip befindlichen, die Schaltgeschwindigkeit abfühlenden Schaltung geliefert wird und regelt dann die Leistung in den logischen Gattern auf dem Halbleiterchip so, daß die gleiche Schaltgeschwindigkeit erhalten wird wie sie das Taktsignal vorschreibt. Auf diese Weise ist die Schaltgeschwindigkeit von Halbleiterchip zu Halbleiterchip die gleiche, während die zugeführte Leistung von Halbleiterchip zu Halbleiterchip variiert. Da alle Halbleiterchips in dem System logische Gatter mit der gleichen Schaltgeschwindigkeit aufweisen, braucht der Systemkonstrukteur für einen bestimmten Gatterpfad nich mehr Halbleiterchips mit geringerer und größerer Schaltgeschwindigkeit vorzusehen. Alle Halbleiterchips haben die gleiche Gatter-Signalverzögerung. Es sei bemerkt, daß als Taktsignal vorzugsweise der Systemtakt dient. Aus der nachfolgenden genaueren Beschreibung ist jedoch ersichtlich, daß das dem Regler für die Signalverzögerung zugeführte Taktsignal auch ein anderes als der Systemtakt sein kann.
• Fig. 4 zeigt ein Ausführungsbeispiel für die Regelung der Signalverzögerung. Der Regler für die Signalverzögerung besteht aus der Phasenvergleichsschaltung, dem Tiefpaßfilter, der Pufferschaltung, dem spannungsgesteuerten Oszillator und der Pegelverschiebungsschaltung. Die Phasenvergleichsschaltung vergleicht das dem Halbleiterchip von außen zugeführte Taktsignal mit dem pegelverschobenen Signal des spannungsgesteuerten Oszillators. Die Ausgangssignale U und D erzeugen ein Signal, das eine Impulsbreite aufweist, die direkt proportional zur Phasendifferenz des Eingangstaktsignals und des pegelverschobenen Signals des spannungsgesteuerten Oszillators ist. Dieses pulsbreitenempfindliche Signal besitzt die gleiche Frequenz wie das Eingangstaktsignal. Die Signale U und D gelangen an das Tiefpaßfilter, das die Trägerfrequenz des Eingangstaktsignals aus diesem Signal entfernt. Das Ausgangssignal VCS' ist eine Gleichspannung, die proportional ist der Impulsbreite des Eingangssignals für das Tiefpaßfilter. Das Signal VCS' gelangt zur Pufferschaltung. Die Pufferschaltung ist ein Verstärker mit dem Verstärkungsfaktor 1. Sie besitzt einen hochohmigen Eingang für das Signal VCS' des Tiefpaßfilters. Die Pufferschaltung besitzt auch einen niederohmigen Ausgang, um das Signal VCS den anderen Gattern auf dem Halbleiterchip und der Schaltung des spannungsgesteuerten Oszillators zuzuführen. Das VCS Signal regelt die Leistung der logischen Gatter auf dem Halbleiterchip. In diesem besonderen Ausführungsbeispiel (siehe Fig. 10) regelt das Signal VCS den Strom durch die Stromquelle des logischen Gatters. Bei zunehmendem Signal VCS nimmt die Leistung in der Schaltung zu, wogegen bei abnehmendem Signal VCS die Leistung in der Schaltung abnimmt. Der spannungsgesteuerte Oszillator erzeugt ein Signal RLF, dessen Frequenz proportional ist dem Eingangssignal VCS. Die Schaltung des spannungsgesteuerten Oszillators sollte die gleiche Abhängigkeit der Schaltgeschwindigkeit von der Leistung aufweisen wie die logischen Gatter im restlichen Teil des Halbleiterchips. Wenn daher das Signal VCS die Signalverzögerung des logischen Gatters ändert, ändert sich auch die Frequenz des spannungsgesteuerten Oszillators. Das Ausgangssignal RLF ist ein periodisches logisches Signal. Das Ausgangssignal VR ist die logische Schwelle, oberhalb derer das Signal RLF sich ändert. Diese beiden Signale gelangen zu der Pegelverschiebungsschaltung, die ein Ausgangssignal erzeugt, das pegelverschobene Signal des spannungsgesteuerten Oszillators, das den gleichen logischen Pegel aufweist wie das Eingangstaktsignal und die gleiche Frequenz wie das Signal RLF. Es ist ersichtlich, daß diese Anordnung von Phasenvergleichsschaltung, Tiefpaßfilter, Pufferschaltung, spannungsgesteuertem Oszillator und Pegelverschiebungsschaltung eine Phasenregelschleife darstellt. Durch Verwendung dieser Phasenregelschleife tendiert der spannungsgesteuerte Oszillator dazu, sich mit dem Eingangstaktsignal zu synchronisieren. Diese Wirkungsweise des Phasenregelkreises tendiert dazu, Schwankungen beim Herstellungsprozeß, Temperaturänderungen und Änderungen in der Spannungsversorgung innerhalb der Fähigkeit des spannungsgesteuerten Oszillators, sich mit dem Taktsignal zu synchronisieren, sich nicht auswirken zu lassen. Wenn der spannungsgesteuerte Oszillator einmal synchronisiert wurde, wurde bei den übrigen logischen Gattern auf dem Halbleiterchip die Leistung geändert, so daß die Gatter-Signalverzögerung nun durch die Frequenz des Eingangstaktsignals geregelt wird. Es ist ersichtlich, daß das Eingangstaktsignal, das jetzt auf der Systemebene allen Halbleiterchips zugeführt wird, die Gatter-Signalverzögerung auf jedem einzelnen Halbleiterchip regelt, unabhängig von der Leistung, die das logische Gatter verbraucht oder von der Temperatur des Halbleiterchips oder von den Prozeßschwankungen, die bei der Herstellung der Halbleiterchips von Los zu Los auftreten.

The invention is explained in more detail below in conjunction with the drawings, in which:

• Figure 1 is a graph showing the gate signal delay as a function of the electrical power supplied to the gate. The curve of FIG. 1 shows the state according to the prior art, in which the power is fixed or selected and the switching speed or the signal delay of the circuit corresponds to the power supplied to it;
• Figure 2 is a graph indicating the gate signal delay as a function of power for a logic circuit. In the curve of FIG. 2, the gate signal delay (or switching speed) of each of a series of logic circuits on a semiconductor chip (or on semiconductor chips) is fixed or was specified in the circuit design, and the electrical power supplied to the logic circuits ( Current or voltage) corresponds to the selected or fixed switching speed;
• FIG. 3 shows a block diagram in which a number of semiconductor chips 1 to n with monolithically integrated circuits are shown. Each semiconductor chip contains a controller for signal delay and a number of logic circuits connected to it. Only three logic circuits are shown in the drawing. The logic circuits are shown as blocks bearing the legend «Fig. 10. Likewise, the connections between the logic circuits on each semiconductor chip and between the semiconductor chips are not shown since they are not necessary for an understanding of the invention. It is known to those skilled in the art that each of the semiconductor chips can include hundreds of interconnected logic circuits. They can also be other than those shown in FIG. 10 (current transfer switches or emitter-coupled logic circuits. From the more detailed description below it will be apparent to the person skilled in the art that the principle described can be applied to transistor-transistor logic (T ² L), the diode transistor logic (DTL), the integrated injection logic (1 ² L) and other technology families as well as with matrix arrangements .. From Fig. 3 it can be seen that the controller 4 for the signal delay of each semiconductor chip has the same clock signal Each of these signal delay controllers internally generates a discrete specific reference signal on the semiconductor chip which, in cooperation with the clock signal, causes the signal delay controller to deliver a unique signal VCS. For example, the signal delay controller of the semiconductor chip 1 ( Fig. 3) the signal VCS1, whereas the controller for the signal delay tion of the semiconductor chip 2 supplies the signal VCS2 (not shown) and the controller for the signal delay of the semiconductor chip n supplies the signal VCSn. Furthermore, the sizes of the signals VCS1, VCS2, VCSn do not necessarily have a fixed relationship to one another. The magnitude or values of each of the potentials VCS1, VCS2, ... to VCSn dictate a point on the curve that represents the gate signal delay as a function of the power associated with that semiconductor chip and providing the desired switching speed;
• Figure 4 shows the block diagram of a controller according to the invention for the signal delay (device for power control). From Fig. 3 it can be seen that each semiconductor chip contains a regulator for the signal delay. The circuit of the signal delay controller can be the same for each semiconductor chip. Each of the blocks in Fig. 4 includes a legend and a figure number. For example, the phase comparator block has the legend “phase comparison circuit” and “(FIG. 5)”, whereas the voltage-controlled oscillator bears the legend “(RLF) and“ (FIG. 8) ”. These legends mean that the circuit of the comparison circuit is shown in Fig. 5 and the circuit of the voltage controlled oscillator in Fig. 8. In the embodiment of the invention, the controller for the signal delay contains a "phase comparison circuit (Fig. 5)", a "low pass filter" (Fig. 6) », a« buffer circuit or a power amplifier (Fig. 7) », a« voltage-controlled oscillator RLF (Fig. 8) »and a« level shift circuit (Fig. 9) », which are connected to one another like this is shown in Fig. 4. Instead of the voltage-controlled oscillator, a current-controlled oscillator can also be used;

• Figure 4A idealized waveforms and potential levels, which are to be considered in connection with the explanation of the operation of the controller for the signal delay (Fig. 4);
• Figure 4B idealized waveforms and potential levels, which are to be considered in connection with the explanation of the operation of the phase comparison circuit and the AC measuring circuit (Fig. 5) for the example of a level-shifted signal of the voltage-controlled oscillator, which has a lower frequency than the clock frequency;
• Figure 4C idealized waveforms and potential levels in conjunction with the explanation of the operation of the phase comparison circuit and the AC measurement circuit (Fig. 5) too. consider for an example of a level-shifted signal of the voltage controlled oscillator that has a higher frequency than the clock frequency;
• Figure 4D idealized waveforms and potential levels, which are to be considered in connection with the explanation of the operation of the phase comparison circuit and the AC measuring circuit (Fig. 5) for the example of a level-shifted signal of the voltage-controlled oscillator, which has the same frequency as the clock frequency;
• Figure 5 is a logic block diagram of a commercially available phase comparison circuit which, according to the invention, can be used in the controller for the signal delay (Fig. 4). Furthermore, three logic elements are shown, which are used as an AC measuring circuit. The input signals to the AC measurement circuit which provides the HIGH, LOW and EQUAL signals come from the phase comparison circuit;
• FIG. 6 shows a low-pass filter circuit which, according to the invention, can be used in the signal delay regulator (FIG. 4);
• Figure 7 shows a buffer circuit that can be used according to the invention in the controller for the signal delay (Fig. 4). It should be noted that the buffer circuit fulfills the function of a power amplifier and can also be called this;
• Figure 8 shows a voltage controlled oscillator (RLF), which can be used according to the invention in the controller for the signal delay (Fig. 4). It should be noted that the voltage controlled oscillator preferably uses a number of logic circuits in which the gate signal delay (or switching speed) is to be controlled by the signal delay controller. In the embodiment of the invention disclosed herein, the logic circuit whose gate signal delay (or switching speed) is to be controlled is a power take-over switch (emitter-coupled logic circuit) as shown in FIG. 10. The voltage controlled oscillator may take the form of a circular loop, as shown in Fig. 8, in which the total number of inverter stages is odd;
• FIG. 9 shows a level shift circuit which can be used according to the invention in the signal delay regulator (FIG. 4);
• FIG. 10 shows a logic circuit (emitter-coupled logic) designed as a current takeover switch, the gate signal delay (or switching speed) of which is regulated according to the invention by the controller for the signal delay;
• FIG. 11 shows a reference voltage generator for supplying a reference voltage VREF, which can be used by the level shift circuit according to FIG. 9 and the internal gate circuit according to FIG. 12;
• FIG. 12 shows an internal gate circuit of the current take-over circuit family (or emitter-coupled logic) which can be used in the phase comparison circuit according to FIG. 5;
• FIG. 13 shows the block diagram of a voltage-controlled oscillator (SGO) for use according to the invention in the power control device of a system in which the circuits, the signal delay of which is to be regulated or optimized, belong to the technological circuit family of transistor-transistor logic (which are shown in FIG. 14 is shown);
• FIG. 14 shows a circuit in transistor-transistor logic, the signal delay of which is regulated or optimized in accordance with the invention by using a device for power control which contains the voltage-controlled oscillator according to FIG. 13;
• FIG. 15 shows a block diagram of a voltage-controlled oscillator for the use according to the invention of the device for controlling the power of a system, the circuits of which, the signal delay to be regulated or optimized, belong to the circuit family which is referred to as integrated injection logic (12 L) and is shown in FIGS. 16 or 17 is shown;
• FIG. 16 shows a 1 ² L circuit whose gate signal delay is to be regulated or optimized according to the invention by using a device for power control, which includes the voltage-controlled oscillator according to FIG. 15;
• FIG. 17 shows a second IZL circuit whose gate signal delay is to be regulated or optimized according to the invention by using a device for power control, which includes the voltage-controlled oscillator according to FIG. 15;
• FIG. 18 is a block diagram of a voltage controlled oscillator for use in the device for power control of a system according to the invention, in which the circuits whose signal delay is to be regulated or optimized are part of the family of field effect transistor circuits (a member of which is shown in FIG. 19);
• FIG. 19 shows a field effect transistor circuit whose gate signal delay can be regulated or optimized according to the invention by using a device for power control, which includes the voltage-controlled oscillator according to FIG. 18.

• Fig. 1 shows a typical signal gate signal delay curve as a function of the electrical power supplied by all logic families. Current practice is to operate a logic gate at a certain power level. This is evidenced by the many publications of circuits that have been designed to a certain power level or to maintain a certain current setting in the logic gate circuit. However, the thought of trying to maintain a certain power or current setting leads to various problems. The first problem relates to the manufacture of the semiconductor devices. During the normal course of semiconductor device manufacturing, there are minor disruptions to the manufacturing process. These slight deviations influence the position of the curve, which represents the dependence of the switching speed as a function of the power, as shown in FIG. 1. As the curve changes, the gate signal delay changes. The second problem is the auxiliary circuitry designed to maintain a certain level of power or current in the logic circuit. These circuits are also subject to variations in the manufacturing process and at the same time are sensitive to changes in supply voltages and temperature changes in the system. The end result is a logic gate, the performance of which is regulated within narrow limits, but whose signal delay can vary considerably.
• Fig. 2 shows the method according to the invention. The gate signal delay is controlled while the logic gate power is allowed to vary so that when the switching speed curve changes depending on the power due to the manufacturing process, temperature or power supply, the gate signal delay remains constant while performance varies.
• Figure 3 illustrates the implementation of the invention at the system level. The system can consist of n semiconductor chips. There is a control circuit for the signal delay on each semiconductor chip, which regulates the power supplied to the remaining gates on the semiconductor chip. In this example, the logic gates shown in Fig. 10 are used, which are implemented in the technology of the current transfer switch. The VCS signal is used to regulate the power in the logic gate by regulating the voltage of the current source. The clock signal shown in FIG. 3 reaches the control circuit for the signal delay of each of the n semiconductor chips. Each clock signal contains the information regarding the switching speed or the timing for the control circuit for signal delay. The control circuit compares this clock signal with a signal provided by a circuit which senses the switching speed and which is located on the semiconductor chip and then regulates the power in the logic gates on the semiconductor chip so that the same switching speed is obtained as that prescribed by the clock signal. In this way, the switching speed from semiconductor chip to semiconductor chip is the same, while the power supplied varies from semiconductor chip to semiconductor chip. Since all the semiconductor chips in the system have logic gates with the same switching speed, the system designer need not provide more semiconductor chips with a lower and higher switching speed for a specific gate path. All semiconductor chips have the same gate signal delay. It should be noted that the system clock is preferably used as the clock signal. However, it can be seen from the more detailed description below that the clock signal supplied to the controller for the signal delay can also be different from the system clock.
• Fig. 4 shows an embodiment for the control of the signal delay. The controller for the signal delay consists of the phase comparison circuit, the low-pass filter, the buffer circuit, the voltage-controlled oscillator and the level shift circuit. The phase comparison circuit compares the clock signal supplied to the semiconductor chip from the outside with the level-shifted signal of the voltage-controlled oscillator. The output signals U and D generate a signal that has a pulse width that is directly proportional to the phase difference of the input clock signal and the level-shifted signal of the voltage-controlled oscillator. This pulse width sensitive signal has the same frequency as the input clock signal. The signals U and D reach the low-pass filter, which removes the carrier frequency of the input clock signal from this signal. The output signal VCS 'is a DC voltage which is proportional to the pulse width of the input signal for the low-pass filter. The signal VCS 'arrives at the buffer circuit. The buffer circuit is an amplifier with a gain factor of 1. It has a high-resistance input for the signal VCS 'of the low-pass filter. The buffer circuit also has a low impedance output to feed the VCS signal to the other gates on the semiconductor chip and the circuit of the voltage controlled oscillator. The VCS signal regulates the performance of the logic gates on the semiconductor chip. In this particular embodiment (see Fig. 10), the signal VCS regulates the current through the current source of the logic gate. With increasing signal VCS, the power in the circuit increases, whereas with decreasing signal VCS, the power in the circuit decreases. The voltage controlled oscillator generates a signal RLF, the frequency of which is proportional to the input signal VCS. The circuit of the voltage-controlled oscillator should have the same dependency of the switching speed on the power as the logic gates in the rest of the semiconductor chip. Therefore, when the signal VCS changes the signal delay of the logic gate, the frequency of the voltage controlled oscillator also changes. The output signal RLF is a periodic logic signal. The output signal VR is the logical threshold above which the signal RLF changes. These two signals arrive at the level shift circuit which produces an output signal, the level shifted signal of the voltage controlled oscillator, which has the same logic level as the input clock signal and the same frequency as the signal RLF. It can be seen that this arrangement of phase comparison circuit, low pass filter, buffer circuit, voltage controlled oscillator and level shift circuit represents a phase locked loop. By using this phase locked loop, the voltage controlled oscillator tends to synchronize with the input clock signal. This mode of operation of the phase locked loop tends not to affect fluctuations in the manufacturing process, temperature changes and changes in the voltage supply within the ability of the voltage controlled oscillator to synchronize with the clock signal. Once the voltage controlled oscillator was synchronized, the power on the remaining logic gates on the semiconductor chip was changed so that the gate signal delay is now controlled by the frequency of the input clock signal. It can be seen that the input clock signal now supplied to all semiconductor chips at the system level controls the gate signal delay on each individual semiconductor chip, regardless of the power that the logic gate consumes or the temperature of the semiconductor chip or the process fluctuations occur from lot to lot in the manufacture of the semiconductor chips.

The phase comparison circuit also generates signals B, C, Ü and D which, in conjunction with signals U and D, provide an indication of whether the frequency of the signal supplied by the voltage controlled oscillator is equal to the clock frequency. This display is used to determine whether the semiconductor chip has the AC performance that is dictated by the clock. The AC measurement circuit generates three signals - HIGH, LOW and EQUAL. The "HIGH" signal indicates that the frequency of the voltage controlled oscillator is higher than the clock frequency. The "LOW" signal indicates that the frequency of the voltage controlled oscillator is lower than the clock frequency. The signal "SAME" indicates that the frequency of the voltage controlled oscillator is equal to the clock frequency.

It can also be seen that the phase comparison circuit, the low-pass filter, the buffer circuit and the level shift circuit need not be on the semiconductor chip itself. The important circuit that must be on the semiconductor chip is the voltage controlled oscillator, which senses the switching speed or gate signal delay that is present on the semiconductor chip. The other four logic circuit blocks (FIGS. 5, 6, 7 and 9) can be present outside the semiconductor chip on another semiconductor chip or can also be composed of discrete components. However, the voltage controlled oscillator must be on the same semiconductor chip as the logic gates to be controlled.

Fig. 5 shows a logic block diagram of the phase comparison circuit and the AC measurement circuit. The phase comparison circuit can be a commercially available one. In this example, the logic gates are composed of the circuits of FIG. 12. The function of this logic circuit is to compare the phase of the two input signals, the system clock supplied externally to the semiconductor chip and the level-shifted signal of the voltage-controlled oscillator, and to generate a logic signal at the outputs U and D which has the same frequency as the input signals and has a pulse width that is proportional to the phase difference of the two input signals.

The logic elements used in the AC measuring circuit are also composed of the circuits according to FIG. 12. The function of this circuit is to determine whether the frequency of the voltage controlled oscillator signal is equal to, greater than or less than that of the clock signal. This is accomplished by using different clock signals within the phase comparison circuit to determine whether the condition is equality or inequality.

From Fig. 5 it can be seen that the signal "LOW" is generated by the NOR operation of the signals 0, D and C. It can also be seen from FIG. 5 that the signal "FAST" is generated by the NOR operation of the signals U, D and B. As can be seen from Fig. 5, the signal "EQUAL is generated by the NOR operation of the signals HIGH and LOW.

Fig. 6 shows the circuit diagram of the low-pass filter. The two input signals U and D are added and filtered to remove the carrier frequency. The output signal VCS 'is a direct current signal. The cut-off frequency of the low-pass filter is chosen so that the ripple of the signal VCS 'is minimal and at the same time the stability of the phase-locked loop is maintained.

11 shows a reference voltage generator. The voltage is generated by the components TA, TB, TC and TD. The component TE is used to supply the reference voltage BREF to the other circuits. The reference voltage of this circuit serves as a logic threshold for the logic gates of Fig. 12 and for the phase comparison circuit of Fig. 5. The reference voltage VREF is also used by the level shift circuit of Fig. 9. This voltage serves as the reference voltage for the logic signals.

Fig. 8 shows the circuit of the voltage controlled oscillator. It consists of N logic gates, which are shown individually in FIG. 10 and are connected to one another in a loop arrangement, the output of gate 1 leading to the input of gate 2 and this continuing until gate N, the output of which on the input of gate 1 is returned. This circuit oscillates at a frequency which is dependent on the gate signal delay of the N elements. The actual gate signal delay of each element is controlled by the VCS signal. It can be seen that the VCS signal changes the performance of each gate. Any change in the gate signal delay results in a change in the frequency of the RLF signal. As the VCS signal increases, the frequency of the RLF signal also increases, and as the VCS signal decreases, the frequency of the RLF signal also decreases. The output signal RLF of this circuit reaches the level shift circuit. The VR signal is the logic reference signal of the gates in this loop.

Fig. 9 shows the level shift circuit. Their purpose is to change the logic level of the RLF signal so that signals are obtained which are compatible with the clock signal shown in Fig. 4A generated outside the semiconductor chip. The signal RLF changes between the voltage levels above the signal VR and below this signal. The elements TA, TB, TC and TD form a logic gate configuration in which the current through the element TC flows either through the element TA or through the element TB, depending on the input voltage RLF. The signal VREF, which is derived from the circuit of FIG. 11, serves two functions. The first function is to generate a reference current for the current source elements TC and TD. This reference current is generated using elements G, TF and E and elements TC and D of the current source supplied using a current mirror configuration, the connection between TF and TC.

The second function of voltage VREF is to clamp the level-shifted output signal of the voltage controlled oscillator using diodes J and H so that the output signal is either above the voltage VREF by the voltage drop across a diode or the voltage drop across a diode below this voltage . The mode of operation of the circuit according to FIG. 9 is controlled by the input signal RLF. When the voltage of the input signal is above the voltage VR, the current through element TC flows through element TA. The current through element K flows through element J, which generates a voltage for the level-shifted signal of the voltage-controlled oscillator which is greater than the signal VREF by the voltage drop across the diode. When signal RLF is below voltage VR, current flows through element TC through element TB, causing all of the current through element K to flow through element TB, and current from signal VREF is drawn through element H. This produces a low level signal which is below the voltage VREF by the voltage drop across a diode at the output for the level shifted signal of the voltage controlled oscillator. It can be seen that the operation of this circuit consists in shifting the reference voltage of the logic input signal RLF to the value of the reference voltage VREF. The output signal has the same frequency as the signal RLF, but has a different logic level.

Fig. 12 shows the circuit diagram of an internal gate used in the phase comparison circuit of Fig. 5. The operation of this gate is similar to that of a gate which is implemented using current transfer technology. The reference voltage VREF is generated by the circuit of FIG. 11. The output voltages are clamped levels that are either above or below the signal VREF by the voltage drop across a diode. The circuit of Figure 12 is shown with only two input transistors TA and TB, but other additional transistors can be connected in the same way to form a three or four input logic gate. A voltage at input 1 or at input 2, which is above the input reference voltage VREF, conducts the current through this transistor and pulls the output potential 0 by the voltage drop across a diode below the voltage VREF. The output voltage 0 is higher than the voltage VREF by the voltage drop across a diode. If the voltages at inputs 1 and 2 are both less than the voltage VREF, the current flows through the element TC and pulls the signal at the output 0 of the diode below the value VREF. The output signals in the circuit are clamped by diodes to provide the correct voltages to control the remainder of the phase control circuit shown in FIG. 4.

FIG. 10 is the circuit diagram of a typical logic gate used in both the voltage controlled oscillator (FIG. 8) and the logic gates in the rest of the semiconductor chip, as indicated in FIG. 4. The elements TD and E form a current source which is controlled by a signal VCS. The signal VCS therefore directly controls the power within the logic gate and thus its switching speed. The logic gate is shown with two inputs, transistors TA and TB, but additional transistors can be provided for further inputs, which are connected in the same way. Outputs 0 and 0 are connected to the signal VR via diodes, so that the output voltages are either above or below the signal VR by the voltage drop across a diode. The A Output voltages 1 and 2 of the circuit are either above or below the signal VR, so that when either the input signal 1 or the input signal 2 is above the voltage VR, the current flows through the element TD via the conductive transistor. The output voltage 0 is then around the voltage drop across a diode below the voltage VR. If neither the input voltage 1 nor the input voltage 2 are above the voltage VR, then the output voltage 0 is one diode voltage drop above the voltage VR. Similarly, when both input signals 1 and 2 are below voltage VR, the current through element TD flows through element TC so that signal 0 is below the voltage VR by one diode voltage drop. If both inputs 1 and 2 have the high potential, then the output voltage 0 is lower than the voltage VR by a diode voltage drop. The VR signal is applied to all of the logic gates on the semiconductor chip that are controlled by the signal delay regulator, including those logic gates of the voltage controlled oscillator of FIG. 8, so that all of these logic gates use the same threshold voltage.

The circuit of Fig. 7 is a buffer circuit. It represents a high input impedance for the signal VCS 'and a low output impedance for the signal VCS, so that this signal can be routed to all logic gates over the entire semiconductor chip, as shown in FIG. 4. The circuit is a differential amplifier, which has a gain factor of 1. The elements TA, TB and D form the differential input stage of the circuit. The input signal VCS 'is compared using the elements TA, TB and D with the signal at node 1. The elements TE, TF, G, TH, J and K provide the necessary signal conditions so that the signal at node 1 is identical to the input signal VCS '. The TM and N elements provide additional output buffering and voltage shifting to provide a VCS signal which is applied to the logic gates and the voltage controlled oscillator as shown in FIG. FIG. 4A shows a series of waveforms and potential levels which are to be considered in connection with the explanation of the mode of operation of the controller for the signal delay according to FIG. 4. 4 are the waveform W1 (clock) and the waveform W2 (level-shifted signal of the voltage-controlled oscillator). As shown in Fig. 4A, each of these waveforms has a part of each pulse period in which the voltage waveform is larger than the voltage VREF and a part in which the level is lower than the voltage VREF. It is also apparent from the curves W1 and W2 of FIG. 4A that the curves W1 and W2 have the same periodicity or pulse repetition frequency. However, the waveform W1 of the clock pulses in phase leads the level-shifted waveform W2 of the voltage-controlled oscillator. The output signal U of the phase comparison circuit is a level which is constant over time and is denoted by L1 in FIG. 4A. Note that the size of L1 is larger than that of VREF. 4A that the output signal Ö is the curve shape W3. The curve shape W3 is a periodic pulse train which has a pulse repetition frequency which is equal to that of the curve shape W1. It can also be seen that the duration of the pulses in the curve W3 is the same or directly proportional to the phase difference between the curves W1 and W1. As can be seen from FIG. 4A, the signal VCS 'is a constant DC voltage level L2 over time. The magnitude L2 of the signal VCS 'is a function of the average potential of the signals U (L1) and D (curve shape W3) and the pulse duration of the curve shape W3. As can be seen from the earlier explanation of the function of the buffer circuit (FIG. 7), the signal VCS has a size L3 which is below the size L2 of the signal VCS 'by the base-emitter voltage of a transistor. From Fig. 4A it also appears that the size L2 of the signal VCS 'by an increase, for. B. A, the size of the voltage VREF and that the signal VCS, whose level has been shifted by a DC voltage of 0.8 to 1 volt, is also by the increase Δ above the voltage VREF - 0.8 volts. The curve W4 represents a periodic pulse train that corresponds to the signal RLF of FIGS. 4 and 8 corresponds. The magnitude of the voltage VR is also shown. It can be seen from FIG. 4A that the curve shape W2 (level-shifted signal of the voltage-controlled oscillator) and the curve shape W4 (RLF) correspond to one another in terms of the periodicity and the pulse duration. As shown in FIG. 4, the waveform W4 (RLF) is shifted by the level shift circuit (FIG. 9) and becomes the level shift signal of the voltage controlled oscillator, which is the output signal of the level shift circuit of FIG. 4.

The figures 4B, 4C and 4D show a series of waveforms and potential levels which are to be considered in conjunction with the explanation of the operation of the phase comparison circuit and the AC measuring circuit according to FIG. These three figures (4B, 4C and 4D) show the curves and potential levels for the conditions that the frequency of the voltage controlled oscillator is lower, higher or equal to the clock frequency.

Fig. 4B shows a series of waveforms and potential levels, which are to be considered in connection with the explanation of the operation of the phase comparison circuit and the AC measuring circuit of Fig. 5 for the example that the frequency of the voltage controlled oscillator is lower than the clock frequency quenz is. 5 are the waveforms W5 (clock) and W6 (level-shifted signal of the voltage-controlled oscillator). As can be seen from FIG. 4B, the curve W5 has a smaller periodicity than the curve W6, therefore the curve W6 has a lower frequency than the curve W5. It can be seen from FIG. 4B that the signal U is the curve shape W7. The curve W7 is a periodic pulse train that was generated from the curves W5 and W6. It should be noted that the transition of the curve shape W7 from a level below the voltage VREF to an above level corresponds to the transition of the curve shape W5 from a level below the voltage VREF to an above level. The transition of the curve shape W7 from a level above the voltage VREF to an underlying level corresponds to the transition of the curve shape W6 from a level below the voltage VREF to an above level. 4B that the signal B is the curve W8 and the signal C is the curve W9. The curves W8 and W9 are generated from the curves W5 and W6. The curves W8 and W9 have periodicities and pulse durations which depend on the logical levels of the curves W5 and W6 and on their level changes. From Fig. 4B it can be seen that the signal D is a DC level, which is denoted by 14. It can be seen from FIG. 4B that the HIGH signal is a DC level designated L5. 4 that the signal LOW is represented by the curve W10 and the signal EQUAL by the curve W11. From the earlier explanation of the AC measurement circuit, it is known that the level L5 corresponding to the HIGH signal is the result of the NOR operation of the curves W7 and W8 and the level L4. From the same explanation, it is known that the curve W10 corresponding to the LOW signal is the result of the NOR operation of the curve W9, the inversion of the curve W7 and the inversion of the level L4. From the same explanation of the AC measuring circuit it is known that the curve W11, which corresponds to the signal EQUAL, is the result of the NOR operation of the curve profiles W10 and the level L5.

Fig. 4C shows a series of waveforms and potential levels which are to be considered in connection with the explanation of the operation of the phase comparison circuit and the AC measuring circuit according to Fig. 5 for the example in which the frequency of the voltage-controlled oscillator is higher than the clock frequency. 5 are the waveforms W12 (clock) and W13 (level-shifted signal of the voltage-controlled oscillator). As can be seen from FIG. 4C, the curve W12 has a longer periodicity than the curve W13, therefore the curve W13 has a higher frequency than the curve 12. From FIG. 4C it can be seen that the signal D is the curve W16 . This curve is a periodic pulse train, which is generated from the curves W12 and W13. It should be noted that the transition of curve shape 16 from a level below voltage VREF to a higher level corresponds to the transition of curve shape W12 from a level below voltage VREF to a higher level. A transition in the curve W16 from a level above the voltage VREF to a level below this voltage corresponds to the transition of the curve profile W13 from a level below the voltage VREF to a level above this voltage. It can be seen from FIG. 4C that signal B is curve shape W14 and signal C is curve shape W15. The curves W14 and W15 are generated from the curves W12 and W13. The curves W14 and W15 have periodicities and pulse durations which depend on the logical levels of the curves W12 and W13 and on the changes in these levels. From Fig. 4C it can be seen that the signal U is a DC level, which is denoted by L6. It can be seen from Fig. 4C that the HIGH signal is a curve represented by W17. It can also be seen from this figure that the LOW signal is represented by the level L7 and the EQUAL signal is represented by the curve shape W18. As can be seen from the earlier explanation of the AC measuring circuit, the curve W17, which corresponds to the signal HIGH, is the result of a NOR operation of the curves W16 and W14 and the level L6. The level L7, which corresponds to the signal LOW, is the result of a NOR operation of the curve shape W15, the inverted curve shape W16 and the inverted level L6. The curve shape W18, which corresponds to the signal SAME, is the result of the NOR operation of the curve shape W17 and the level L7.

Fig. 4D shows a series of waveforms and potential levels, which are to be considered in connection with the explanation of the operation of the phase comparison circuit and the AC measuring circuit according to Fig. 5 in the event that the frequency of the voltage controlled oscillator is equal to the clock frequency. The input signals for the phase comparison circuit according to FIG. 5 are the curve profile W19 (clock) and the curve profile 20 (level-shifted signal of the voltage-controlled oscillator). As FIG. 4D shows, the curve W19 has the same periodicity as the curve W20, therefore the curve W20 has the same frequency as the curve W19. FIG. 4D shows that the signal U is the curve W21 and that from the curves W19 and W20 was generated. It should be noted that in the curve W21, a transition from a level below the voltage VREF to an overlying level corresponds to a transition of the curve profile W19 from a level below the voltage VREF to an above level. In the case of the curve W21, the transition from a level above the voltage VREF to an underlying level corresponds to the transition of the curve profile W20 from a level below the voltage VREF to an overlying level. It can be seen from FIG. 4D that signal B is curve shape W22 and signal C is curve shape W23. The curves W22 and W23 are generated from the curves W19 and W20. The curves W22 and W23 have periodicities and pulse durations which depend on the logical levels of the curves W19 and W20 and their changes. From Fig. 4D it can be seen that the signal D is a DC level, which is designated L8. It can also be seen from FIG. 4D that the HIGH signal is a DC current level designated L9. It can also be seen that the LOW signal is represented by level L10 and the EQUAL signal is represented by level L11. As can be seen from the earlier explanation of the AC measuring circuit, the level L9, which corresponds to the signal HIGH, is the result of a NOR operation of the curves W21 and W22 and the level L8. The level L10, which corresponds to the signal LOW, is the result of the NOR combination of the curve shape W23, the inversion of the curve shape W21 and the inversion of the level L8. The level L11, which corresponds to the signal SAME, is the result of a NOR operation of the levels L10 and L9.

As explained earlier, it should be noted that the signal VCS (L3) is the output of the buffer circuit of the regulator for the signal delay shown in FIG. According to the invention, this output signal VCS is used to determine the point on the curve. which represents the gate signal delay as a function of power, at which the logic circuits operate. This variable is therefore decisive for the constant switching speed or gate signal delay of the logic circuits which receive the signal VCS.

Fig. 13 shows the circuit of the voltage controlled oscillator used, which is constructed in transistor-transistor logic. The input signal VCS to the circuit controls the power in each logic gate (Fig. 14). As explained earlier, changing the power in the logic gates of the voltage controlled oscillator results in a frequency change in the signal RLF. Implementation by transistor-transistor logic in this preferred embodiment may make the level shift circuit (Fig. 9) unnecessary for changing the voltage levels of the RLF signal. If a level shift circuit is not required, as can be easily determined by a person skilled in the art, the signal RLF replaces the level shifted signal of the voltage controlled oscillator as an input signal for the 0 phase comparison circuit (FIG. 5). Likewise, the VR signal and the level-shifted signal of the voltage controlled oscillator would be removed from the circuit since they are no longer required. However, if it is determined by those skilled in the art that a level shift circuit is needed, the new level shift circuit may not require the VR signal to generate a level-shifted oscillator signal that is compatible with the comparison circuit. Experts are also known. that the use of transistor-transistor logic or any other logic in the comparison circuit may require additional circuits for the signals U and D (Fig. 4) to appear as signals with the correct source impedances and / or voltage / current levels and / or temperature responses and so that corrections can be made to the power supply so that the control circuit (Fig. 4) works correctly for the signal delay.

FIG. 14 is an example of a transistor-transistor logic gate that can be used in the voltage controlled oscillator of FIG. 13. Other known configurations of transistor-transistor logic can also be used. The signal VCS generated by the buffer circuit or the power amplifier (FIG. 7) passes to all logic gates of the voltage-controlled oscillator (FIG. 13) and to the logic gates in the remaining part of the semiconductor chip, not shown. which may or may not include the 0 comparison circuit (FIG. 5). The control signal VCS changes the power in the logic gate (Fig. 14). As the VCS signal increases, the power supplied to the logic gate increases, resulting in a decrease in the gate signal delay. In the same way, when the signal VCS decreases, the power supplied to the logic gate decreases, which results in an increase in the gate signal delay. It will be apparent to those skilled in the art that the voltage level of the VCS signal should only be increased to the level at which a further increase in the voltage level does not result in a further decrease in the gate signal delay.

15 shows the voltage-controlled oscillator used in the configuration of the integrated injection logic (FL). The input signal to the circuit, the VCS signal in the logic gate of Fig. 16 or the VCS signal in the logic gate of Fig. 17, controls the power in each logic gate. As previously explained, there has been a change the power in the logic gates of the voltage controlled oscillator results in a frequency change of the signal RLF As previously discussed in the description of the use of transistor-transistor logic in the voltage controlled oscillator, the level shift circuit is it required or not, the level-shifted signal of the voltage controlled oscillator and / or the signal VR may or may not be required, and additional circuitry for proper operation of the signal delay controller (FIG. 4) may or may not be necessary. In Figs. 16 and 17 show two examples of controlling the power of a 12L gate. Figure 16 shows that the current through element TA is controlled by a variable voltage. VCS. The voltage VCC has a fixed value, so that when the voltage of the signal VCS decreases, the power supplied to the logic gate increases, and thereby the signal delay of the logic gate decreases. As the voltage of the signal VCS increases, the power supplied to the logic gate decreases, which in turn increases the signal delay of the logic gate. It will be apparent to those skilled in the art that to achieve the proper operation of the signal delay regulator circuit (FIG. 4), the signals U and D generated by the comparison circuit (FIG. 5) must be logically inverted (U and D) .

Fig. 17 shows a 12L gate controlled by a voltage change across element B. The base of element TA is connected to ground so that when signal VCS changes, the current through element TA changes. As the voltage of the VCS signal increases, the power in the logic gate increases and its signal delay decreases. As the voltage of the VCS signal decreases, the power supplied to the logic gate also decreases, and with it the signal delay. It should be noted that for these special logic gates, the voltage VCS is not distributed to the voltage controlled oscillator and the remaining logic gates on the semiconductor chip. Instead, the signal VCS "is distributed to the voltage controlled oscillator and the remaining logic gates on the semiconductor chip.

Fig. 18 shows the circuit of a voltage controlled oscillator that can be used in an embodiment with field effect transistors. The input signal VCS controls the power that is supplied to each logic gate (Fig. 19). As explained earlier, a change in the power supplied to the gates of the voltage controlled oscillator results in a change in the frequency of the signal RLF. Increasing the power supplied to the logic gate (Fig. 19) decreases the signal delay and decreasing the power supplied to the logic gate increases its signal delay.

• 1. Es ist nicht notwendig, einen Phasenregelkreis zu verwenden. Es kann ein Frequenzregelkreis verwendet werden.
• 2. Es ist nicht notwendig, den Systemtakt zu verwenden. Es kann ein eigener Taktgeber verwendet werden.
• 3. Inverter sind nicht notwendigerweise die einzige Art von Gattern, die für den spannungsgesteuerten Oszillator verwendet werden können.
• 4. Der Frequenzvergleich kann durch RRC-Filter und eine Spannungsvergleichsschaltung durchgeführt werden.
• 5. Es kann mehr als ein Regler auf einem Halbleiterchip vorhanden sein.
• 6. Die Pufferschaltung oder der Leistungsverstärker kann einen von 1 verschiedenen Verstärkungsfaktor haben.
• 7. Das Tiefpaßfilter kann sich in der Pufferschaltung befinden.

The following are a number of changes and modifications to the invention that can be made without departing from the scope of the invention:

• 1. It is not necessary to use a phase locked loop. A frequency control loop can be used.
• 2. It is not necessary to use the system clock. A separate clock can be used.
• 3. Inverters are not necessarily the only type of gates that can be used for the voltage controlled oscillator.
• 4. The frequency comparison can be carried out by RRC filters and a voltage comparison circuit.
• 5. There may be more than one controller on a semiconductor chip.
• 6. The buffer circuit or power amplifier can have a gain factor other than 1.
• 7. The low pass filter can be located in the buffer circuit.

The concept on which the invention is based can be summarized as follows:

For each circuit with a dependence of the switching speed on the power, the switching speed can be set or regulated by changing the power supplied to the circuit.

The device by which the power can be varied is brought about by a feedback loop which essentially contains the signal of an oscillator (which is composed of the gates to be controlled), a reference signal (clock), a device for comparing the reference and Oscillator signals that generate an error signal and a device for converting the error signal into the appropriate control signal.

The oscillator can be constructed in any way from a number of ways known to those skilled in the art. The use of a voltage controlled oscillator has been described for explanation. A clock signal was selected as the reference signal.

The comparison circuit, which performs the function of a frequency / voltage converter or a frequency / current converter, can be any device known to the person skilled in the art, such as a pulse width modulator, D flip-flops, digital-to-analog converter or phase locked loops. For the purpose of explanation, the use of a phase comparison circuit operating as a phase locked loop has been described in particularly detail.

Claims (6)

1. Circuit for adapting the signal delay times of interconnected semiconductor chip (1-n ; Fig. 3) to a nominal value that is characterized by the frequency of an externally applied pulse sequence (W1 ; Fig. 4A), and reached by means of a regulator circuit (4 ; Fig. 3) provided on each semiconductor chip, by modifying the electric power applied to the semiconductor chip, said regulator circuit comprising a controllable oscillator (Fig. 4; Fig. 8) and a phase comparing circuit (Fig. 4, Fig. 5) where the frequency of the controllable oscillator is compared with that of the externally applied pulse sequence, and re- regulated to reach synchronization if there is a difference, characterized in that also connected to the phase comparing circuit is an additional circuit (5) which at its outputs supplies a signal to indicate whether the frequency of the controllable oscillator characterizing the relative signal delay time of the semiconductor chip circuits is higher than, equal to or lower than that of the externally applied pulse sequence.

2. Circuit as claimed in claim 1, characterized in that the additional circuit is connected to first outputs (U, D) of the phase comparing circuit (Fig. 5) which are connected to a low pass filter (Fig. 6) following the phase comparing circuit, as well as to second outputs to which the phase comparing circuit supplies signals (U, D) which are complementary to that applied to the low pass filter, and to third outputs (B, C) where internal signals of the phase comparing circuit are available.

3. Circuit as claimed in claims 1 and 2, characterized in that the additional circuit is composed of three logic circuits (Fig. 12) at whose outputs the electric signals relating to the frequency of the controllable oscillators are supplied, and where the outputs of two logic circuits are also connected to the third one which displays frequency synchronism.

4. Circuit as claimed in any one of claims 1 to 3, characterized in that the additional circuit is composed of NOR circuits.

5. Circuit as claimed in any one of claims 1 to 4, characterized in that the electrical signal is available at the output of the additional circuit as an electrical potential.

6. Circuit as claimed in any one of claims 1 to 4, characterized in that the electrical signal at the output of the additional circuit is available as electric current.

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