EP0652676A1 - Verfahren und Vorrichtung zur Komprimierung eines digitalen Bewegtbildsignals - Google Patents

Verfahren und Vorrichtung zur Komprimierung eines digitalen Bewegtbildsignals Download PDF

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Publication number
EP0652676A1
EP0652676A1 EP93118088A EP93118088A EP0652676A1 EP 0652676 A1 EP0652676 A1 EP 0652676A1 EP 93118088 A EP93118088 A EP 93118088A EP 93118088 A EP93118088 A EP 93118088A EP 0652676 A1 EP0652676 A1 EP 0652676A1
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EP
European Patent Office
Prior art keywords
pixel data
parallel
block
order bits
pixel
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EP93118088A
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English (en)
French (fr)
Inventor
Ikuo C/O Sony Corporation Tsukagoshi
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Sony Corp
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Sony Corp
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Priority to EP93118088A priority Critical patent/EP0652676A1/de
Publication of EP0652676A1 publication Critical patent/EP0652676A1/de
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/43—Hardware specially adapted for motion estimation or compensation
    • H04N19/433—Hardware specially adapted for motion estimation or compensation characterised by techniques for memory access
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/50—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding
    • H04N19/503—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving temporal prediction
    • H04N19/51—Motion estimation or motion compensation
    • H04N19/523—Motion estimation or motion compensation with sub-pixel accuracy
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/14—Picture signal circuitry for video frequency region
    • H04N5/144—Movement detection
    • H04N5/145—Movement estimation

Definitions

  • the quantity of difference data can be further reduced by calculating the motion vector with half-pixel precision.
  • a typical method for determining the motion vector with half pixel precision will be described with reference to Figure 2.
  • a primary motion vector MVi is obtained for each block with one-pixel precision, as just described.
  • a secondary motion vector Vi with half-pixel precision is determined by calculating pixels with half-pixel precision, indicated by X, ⁇ , and ⁇ , by interpolation in the horizonal, vertical, and vertical directions, respectively.
  • Figure 4 is a block diagram showing the construction of the movement detecting section.
  • the motion detection and motion compensation circuit 16 first calculates the primary motion vector MVi with one-pixel precision. Using the primary motion vector MVi, the motion detection and motion compensation circuit 16 defines a search area of 10 pixels ⁇ 10 pixels in which interpolation pixels will be generated.
  • the search area is an area of the reference picture that extends from 0 to 9 pixels in the x - and y -directions, in which the pixel indicated by the primary motion vector MVI with one pixel precision is located at 1,1.
  • the motion detection and motion compensation circuit 16 combines the secondary motion vector Vi with the previously-obtained primary motion vector MVi to generate the desired motion vector MVH with half-pixel precision. Finally, the motion detection and motion compensation circuit 16 supplies the matching block that most closely matches the picture block S2 as the reference block S3, and provides the block of differences between the picture block and the reference block S3 as the difference block S4.
  • the primary motion detector circuit 21 derives the primary motion vector MVi from the picture block S2 and the reference picture S12, and supplies the primary motion vector MVi to the interpolation address generating circuit 22 as primary motion vector data S21.
  • the block/raster converting circuit 23 converts the blocks of the reference picture S12 into a raster signal.
  • the raster signal is fed into the parallelizing circuit 24, and the resulting parallel pixel data S23 are successively written into the multi-port Video Random Access Memory (VRAM) 25.
  • VRAM Video Random Access Memory
  • the other eight pairs of parallel paths C through R each correspond to blocks obtained by shifting the designated block by -1 ⁇ 2, 0, and +1 ⁇ 2 pixel in each of the x - and y -directions.
  • Each of the eight pairs of parallel paths therefore generates one 8 ⁇ 4 block of parallel half pixel data corresponding to moving the designated block by -1 ⁇ 2, 0, and +1 ⁇ 2 pixel in each of the x - and y -directions.
  • each line of the 10 ⁇ 10 search area has a duration of five clock cycles.
  • the pixel data for the same pixel on adjacent lines of the search area are separated by 5 clock cycles.
  • Interpolating is performed by adding the pixel data of selected adjacent pixels in the x - and y -directions.
  • the pixel data to be added are selected by delaying the pixel data for the search area received from the multi-port VRAM 25.
  • the interpolated data is then resynchronized by additional delays.
  • the paths C and F provide the high-order bits and the low-order bits, respectively, of the parallel half-pixel data of the matching block obtained by shifting the designated block by one half of a pixel in the minus x -direction.
  • the paths C and F also provide the high-order bits and the low-order bits, respectively, of the parallel half-pixel data of the matching block obtained by shifting the designated block by one half of a pixel in the plus x -direction.
  • interpolation is carried out in the horizontal direction only.
  • Path C provides the high-order bits of the parallel half-pixel data of the matching blocks obtained by shifting the designated block in the plus and minus x -directions by summing the high-order bits and the low-order bits of the same parallel pixel data of the search area.
  • the high order bits and the low order bits of the same parallel pixel data of the search area S24 are delayed by the one-unit delays 35C and 35F, respectively, and the delayed high-order bits and low order bits are summed in the adder 42C.
  • the resulting half-pixel data from the adder 42G are passed through the three one-unit delays 36G, 37G and 38G before being delivered via the path G to the serializer 27, where the high-order bits of the matching block obtained by shifting the designated block by one half of a pixel in the minus y -direction are selected.
  • Path I provides the high-order bits of the parallel half-pixel data by adding the high-order bits of the parallel pixel data of the search area to the high-order bits of the parallel pixel data of the same pixel in the following line of the search area.
  • the parallel pixel data of the search area S24 are first delayed by the 5-unit delay 34G before being split into high-order and low-order bits.
  • the high order bits are then additionally delayed by the one-unit delay 35G before being fed to the adder 42I.
  • the parallel pixel data are additionally delayed by the 5-unit delay 34I before being split into high-order and low-order bits.
  • the high order bits are then additionally delayed by the one-unit delay 35I before also being fed to the adder 42I.
  • the resulting half-pixel data from the adder 42I are passed through the three one-unit delays 36I, 37I and 38I to synchronize them with the pixel data on the paths A and B, before being delivered via the path I to the serializer 27, where the high-order bits of the matching block obtained by shifting the designated block by one half of a pixel in the plus y -direction are selected.
  • Path J operates similarly to path I, except that the low-order bits from the 5-unit delay 34G are further delayed by the one-unit delay 35H before being added by the adder 42J to the low-order bits from the second five unit delay 34I, additionally delayed by the one-unit delay 35J.
  • the resulting half-pixel data are then delayed by the three one-unit delays 36J, 37J, and 38J to synchronize them with the pixel data in paths A and B, before they are delivered via the path J to the serializer 27, where the low-order bits of the matching block obtained by shifting the designated block by one half of a pixel in the plus y -direction are selected.
  • Paths K through R provide half pixel data for the matching blocks obtained by shifting the designated block by one half of a pixel in both the x -and y -directions. These half pixel data are generated by interpolation between already-generated half pixel data.
  • Path K provides the high-order bits of the parallel half-pixel data of the matching blocks obtained by shifting the designated block in the minus y -direction and in the plus and minus x -directions by summing the high-order bits of the parallel half pixel data shifted in the x -direction from path C and the high-order bits of the parallel half pixel data shifted in the x -direction from path C of the previous line.
  • the half pixel data are delivered via the path K to the serializer 27, where the high-order bits of the parallel half-pixel data of the matching block obtained by shifting the designated block in the minus x -direction and the minus y -direction are selected.
  • the half pixel data are also delivered via the path M to the serializer 27, where the high-order bits of the parallel half-pixel data of the matching block obtained by shifting the designated block in the plus x -direction and minus y -direction are selected.
  • Path N provides the low-order bits of the parallel half-pixel data of the matching blocks obtained by shifting the designated block in the minus y -direction and the plus and minus x -directions by adding the low-order bits of the parallel half-pixel data shifted in the x -direction from path F to the low-order bits of the parallel half-pixel data shifted in the x -direction from path F of the previous line.
  • the half pixel data are delivered via the path L to the serializer 27, where the low-order bits of the parallel half-pixel data of the matching block obtained by shifting the designated block in the minus x -direction and the minus y -direction are selected.
  • the half pixel data are also delivered via the path N to the serializer 27, where the low-order bits of the parallel half-pixel data of the matching block obtained by shifting the designated block in the plus x -direction and minus y -direction are selected.
  • the half pixel data are delivered via the path O to the serializer 27, where the high-order bits of the parallel half-pixel data of the matching block obtained by shifting the designated block in the minus x -direction and the plus y -direction are selected.
  • the half pixel data are also delivered via the path Q to the serializer 27, where the high-order bits of the parallel half-pixel data of the matching block obtained by shifting the designated block in the plus x -direction and plus y -direction are selected.
  • the half pixel data are delivered via the path P to the serializer 27, where the low-order bits of the parallel half-pixel data of the matching block obtained by shifting the designated block in the minus x -direction and the plus y -direction are selected.
  • the half pixel data are also delivered via the path R to the serializer 27, where as the low-order bits of the parallel half-pixel data of the matching block obtained by shifting the designated block in the plus x -direction and plus y -direction are selected.
  • the difference absolute value sum calculating circuit 50A receives the matching block 26A from the delay circuits 39A and 39B in the block parallelizing circuit 27, and the delayed picture block S27, which is the picture block S2, delayed by the delay circuit 29 ( Figure 4).
  • the subtracting circuit 52A determines the pixel-by-pixel difference between the matching block S26A, and the delayed picture block S27, additionally delayed by the delay circuit 51A.
  • the resulting block of differences is fed as the residual block S30A into the absolute value circuit 53A, which determines the absolute value of the residual block S30A.
  • the block of the absolute values of the residual block S30A is fed from the absolute value circuit 53A to the accumulator formed by the adder 54A and the delay circuit 55A.
  • the accumulator generates a difference absolute value sum for the block of absolute values.
  • the difference absolute value sum is fed to the delay circuit 56A, which provides the difference absolute value sum signal S31A to the minimum value determining circuit 57.
  • the difference absolute value sum signals S31A to S31I from the difference absolute value sum calculating circuits 50A through 50I respectively indicate the difference absolute value sum for each of the nine residual blocks S30A through S30I, each representing the differences between the delayed picture block S27 and one of the nine matching blocks consisting of the designated block and the blocks obtained by shifting the designated block by -1 ⁇ 2, 0, and +1 ⁇ 2 pixel in each of the x - and y -directions.
  • the output of the minimum value determining circuit 57 feeds to the read-only memory 58 the selection signal S32, which indicates which of the residual blocks S30A through S30I has the least difference absolute value sum, and therefore which of the corresponding nine matching blocks S26A through S26I most closely matches the picture block S2.
  • the read-only memory provides the secondary motion vector Vi with half-pixel precision in accordance with the selection signal S32.
  • the reference block selector 62 receives the nine matching blocks S26A through S26I from the block serializer 27, and also receives the selection signal S32 from the minimum value determining circuit 57. The reference block selector 62 selects the one of the nine matching blocks S26A through S26I indicated by the selection signal S32 as the reference block S3.
  • the difference block selector 63 receives the nine residual blocks S30A through S30I from the subtractor, such as the subtractor 52A, in each of the difference absolute value sum calculating circuits 50A through 50I, and also receives the selection signal S32 from the minimum value determining circuit 57.
  • the difference block selector 63 selects the one of the nine residual data blocks S30A through S30I indicated by the selection signal S32 as the difference block S4.
  • the picture block S2 is fed from the pre-processing circuit 2 and the reference picture S12 is fed from the frame memory 14 into the motion detection and motion compensation circuit 16.
  • the mark ⁇ indicates a real pixel
  • marks ⁇ and X indicate half-pixels
  • the mark o indicates the original pixel identified by the primary motion vector MVi with one-pixel precision.
  • the Figures show the whole search area in the x -direction, and part of the search area in the y -direction.
  • the half-pixel formed by interpolation in the x -direction between the real pixels of address 0 and address 1 is shown with the mark ⁇ on the line joining addresses 0 and 1, and is indicated as half pixel A01.
  • the half-pixel which is formed by interpolation in the x -direction between the real pixels of address 1 and address 2 is shown with the mark ⁇ on the line connecting addresses 1 and 2, and is identified as half-pixel A12, and so on.
  • Processing in the compressed plane generates the required interpolation points with half-pixel precision in the picture plane, making it possible to calculate 10 ⁇ 3 half pixels by interpolation in 5 ⁇ 3 clock cycles, i.e., in half the number of clock cycles.
  • the nine matching blocks are generated in parallel. This means that, despite the delays required to execute the interpolation process, the nine matching blocks each of 64 half pixels can be calculated by interpolation in fewer than 64 clock cycles.
  • a set of 50 half-pixel data is generated by interpolation on each of the eighteen data paths A through R for each picture block S2.
  • the set of 50 half pixel data on each of the data paths includes unwanted half pixel data in addition to the 32 wanted half-pixel data that will constitute half of one matching block.
  • the block parallelizing circuit 27 uses the FIFO memory set 43 to select the wanted half-pixel data by writing into the FIFO memory set 43 only the 32 wanted half-pixel data that will be included in each respective matching block.
  • the wanted half-pixel data are selected by transmitting write pulses with appropriate timing to each FIFO memory in the FIFO memory set, and, after a fixed time, reading data written into the FIFO memory set 43.
  • FIG. 7 and 8 correspond to the data indicated in Figures 10 and 11.
  • Data is written into the FIFO memory 43 when the write pulse (-we) is at a low level (that is, in the logical "L" state), and the written data is read out by starting the read pulse (-re) after a fixed period of time.
  • the read pulses (-re) fed to the FIFO memories in each pair of FIFO memories, such as the FIFO memories 43A and 43B is of a clock-alternate type. This enables the 8-bit pixel data represented by the high-order bits and the low-order bits stored in the pair of FIFO memories to be read sequentially to provide the matching blocks, such as the matching block S26A.
  • the motion vector detecting circuit 28 determines the difference absolute value sums between the matching blocks S26A through S26I, and the delayed picture block S27, and selects the one of the residual blocks S30A through S30I that has the least difference absolute value sum as the difference block S4 with half-pixel precision.
  • the motion vector detecting circuit 28 also selects the matching block from which the residual block having the least difference absolute value sum was derived as the reference block S3 with half-pixel precision.
  • the pixel data in the search picture S12 is parallelized by the parallelizing circuit 24, and then the half-pixel interpolating circuit 26 derives eight blocks of interpolation pixels with half-pixel precision in the area around the matching block designated by the motion vector with one-pixel precision. Then, by rearranging the interpolation pixels in the block serializing circuit 27, nine interpolation blocks displaced in the x - and y -directions are supplied to the motion vector determining circuit 28. This makes it possible to easily obtain the motion vector with half-pixel precision using a single clock without increasing the number of frame memories.
  • the pixel data of the reference picture are successively transformed into parallel pixel data, and the parallel pixel data with a compressed address space are then interpolated to generate parallel half-pixel data for the half pixels in the search area designated by the primary motion vector with one-pixel precision.
  • the half-pixel data are fed out in parallel blocks of half-pixel data, one for each of plural matching blocks obtained by displacing the block designated by the motion vector with one-pixel precision by +1 ⁇ 2, -1 ⁇ 2, and 0 vertically and horizontally.

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  • Engineering & Computer Science (AREA)
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  • Compression Or Coding Systems Of Tv Signals (AREA)
EP93118088A 1993-11-08 1993-11-08 Verfahren und Vorrichtung zur Komprimierung eines digitalen Bewegtbildsignals Withdrawn EP0652676A1 (de)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0766479A2 (de) * 1995-09-29 1997-04-02 Mitsubishi Denki Kabushiki Kaisha Vorrichtung zur Codierung und Decodierung eines digitalen Bildsignales
DE19648612A1 (de) * 1996-11-14 1998-05-20 Teles Ag Verfahren zur Bewegtbilddatenkompression und Kodiervorrichtung zur Durchführung des Verfahrens
WO2000018125A1 (de) * 1998-09-23 2000-03-30 Siemens Aktiengesellschaft Verfahren und anordnung zur codierung eines digitalisierten bildes sowie verfahren und anordnung zur decodierung eines codierten digitalisierten bildes
WO2005096632A1 (en) * 2004-03-31 2005-10-13 Koninklijke Philips Electronics N.V. Motion estimation and segmentation for video data

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JPS57127982A (en) * 1981-01-27 1982-08-09 Nec Home Electronics Ltd Memory address system
JPH0290245A (ja) * 1988-09-27 1990-03-29 Seiko Epson Corp インターフェイス装置
US4937666A (en) * 1989-12-04 1990-06-26 Bell Communications Research, Inc. Circuit implementation of block matching algorithm with fractional precision
GB2236449A (en) * 1989-09-20 1991-04-03 British Broadcasting Corp Motion estimation for television signals
US5030953A (en) * 1990-07-11 1991-07-09 Massachusetts Institute Of Technology Charge domain block matching processor
EP0497586A2 (de) * 1991-01-31 1992-08-05 Sony Corporation Bewegungsnachweisungsschaltung
EP0517095A1 (de) * 1991-05-30 1992-12-09 Sony Corporation Schaltung zur Interpolation eines Bildsignals
EP0544122A1 (de) * 1991-10-31 1993-06-02 Victor Company Of Japan, Limited Verfahren zur Kompensierung von Bewegungen in Bildern

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57127982A (en) * 1981-01-27 1982-08-09 Nec Home Electronics Ltd Memory address system
JPH0290245A (ja) * 1988-09-27 1990-03-29 Seiko Epson Corp インターフェイス装置
GB2236449A (en) * 1989-09-20 1991-04-03 British Broadcasting Corp Motion estimation for television signals
US4937666A (en) * 1989-12-04 1990-06-26 Bell Communications Research, Inc. Circuit implementation of block matching algorithm with fractional precision
US5030953A (en) * 1990-07-11 1991-07-09 Massachusetts Institute Of Technology Charge domain block matching processor
EP0497586A2 (de) * 1991-01-31 1992-08-05 Sony Corporation Bewegungsnachweisungsschaltung
EP0517095A1 (de) * 1991-05-30 1992-12-09 Sony Corporation Schaltung zur Interpolation eines Bildsignals
EP0544122A1 (de) * 1991-10-31 1993-06-02 Victor Company Of Japan, Limited Verfahren zur Kompensierung von Bewegungen in Bildern

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* Cited by examiner, † Cited by third party
Title
K.M. YANG ET AL.: "Very High Efficiency VLSI Chip-Pair for Full Search Block Matching with Fractional Precision", ICASSP '89, vol. 4, 23 May 1989 (1989-05-23), IEEE,GLASGOW,SCOTLAND, pages 2437 - 2440, XP000090108 *
PATENT ABSTRACTS OF JAPAN vol. 14, no. 293 (P - 1066) 25 June 1990 (1990-06-25) *
PATENT ABSTRACTS OF JAPAN vol. 6, no. 225 (P - 154) 10 November 1982 (1982-11-10) *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0766479A2 (de) * 1995-09-29 1997-04-02 Mitsubishi Denki Kabushiki Kaisha Vorrichtung zur Codierung und Decodierung eines digitalen Bildsignales
EP0766479A3 (de) * 1995-09-29 1999-02-03 Mitsubishi Denki Kabushiki Kaisha Vorrichtung zur Codierung und Decodierung eines digitalen Bildsignales
DE19648612A1 (de) * 1996-11-14 1998-05-20 Teles Ag Verfahren zur Bewegtbilddatenkompression und Kodiervorrichtung zur Durchführung des Verfahrens
WO2000018125A1 (de) * 1998-09-23 2000-03-30 Siemens Aktiengesellschaft Verfahren und anordnung zur codierung eines digitalisierten bildes sowie verfahren und anordnung zur decodierung eines codierten digitalisierten bildes
WO2005096632A1 (en) * 2004-03-31 2005-10-13 Koninklijke Philips Electronics N.V. Motion estimation and segmentation for video data

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