EP0647354A4 - Procede de fabrication d'un affichage a matrice active. - Google Patents

Procede de fabrication d'un affichage a matrice active.

Info

Publication number
EP0647354A4
EP0647354A4 EP93910769A EP93910769A EP0647354A4 EP 0647354 A4 EP0647354 A4 EP 0647354A4 EP 93910769 A EP93910769 A EP 93910769A EP 93910769 A EP93910769 A EP 93910769A EP 0647354 A4 EP0647354 A4 EP 0647354A4
Authority
EP
European Patent Office
Prior art keywords
layer
conductive material
depositing
recited
electrically
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP93910769A
Other languages
German (de)
English (en)
Other versions
EP0647354A1 (fr
Inventor
Miki Brinkenstein
Joachim Gluck
Ernst Luder
Original Assignee
Advanced Technology Incubator Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Technology Incubator Inc filed Critical Advanced Technology Incubator Inc
Publication of EP0647354A1 publication Critical patent/EP0647354A1/fr
Publication of EP0647354A4 publication Critical patent/EP0647354A4/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs

Definitions

  • the invention relates generally to the field of thin film transistor driven active matrix displays, and more particularly to the field of manufacturing processes for fabricating thin film transistor driven active matrix displays.
  • the invention most particularly relates an improved process for fabricating thin film transistor driven active matrix liquid crystal display devices having a pixel capacitance in parallel to the pixel.
  • the inventive process also provides enhanced protection to the channel region of the transistors, thus improving transistor performance.
  • liquid crystal displays In the field of liquid crystal displays, and in particular in the field of active matrix liquid crystal displays, major international electronics companies have, for the last decade, expended hundreds of millions of dollars for the development of large area, high resolution displays. In addition to being large area, liquid crystal displays also must be able to display information at video speed rates, and be able to illustrate images in a wide variety of colors.
  • Fabricating a color LCD is a highly sophisticated endeavor, merging the sciences of chemistry, photography, microelectronic engineering and precision manufacturing techniques. These combined processes are as complex as producing a large scale semiconductor.
  • the basic design principles of LCD's are in fact closely coupled with semiconductor manufacturing technology.
  • the active matrix color LCD used in, for example, a "notebook" computer has an average of 307,200 picture elements ("pixels"). Each pixel contains red, green, and blue elements. In order to address each element of each pixel at video rate speeds, a separate transistor must be provided at each element. That translates into 921,600 transistors. A comparable 14 inch diagonal LCD display would therefore require approximately 1,232,000 transistors. Essentially, each screen is a large microchip.
  • the principal source of defects in the manufacturing of LCD's is the fabrication of the switching element, or thin film transistor, disposed at every picture element. Fabrication of the thin film switching element typically requires 5 and up to 7 separate deposition-mask-etch steps in order to fabricate the transistor. As each layer of material is deposited, masked, and etched to create a new layer of structure, critical tolerances of less than 1 micron must be maintained in order to produce an operative device. As additional deposition-mask-etch steps are required, the likelihood of error increases, and hence, manufacturing yield of the display decreases.
  • an improved method for fabricating field effect thin film transistor driven active matrix display device having parallel capacitance and a protected channel transistor for improved performance said transistor device also having gate regions, source regions, and drain regions.
  • the improved method comprises the steps of providing a substrate member such as glass, plastic, quartz, and other known high temperature substrate materials. Thereafter, a first layer of electrically conductive material is disposed upon said substrate, which layer is patterned to form the gate contacts of each TFT and first address means in electrical communication with said gate contacts.
  • the first address means typically includes a first address line adapted to be electrically connected to electronic circuitry disposed about the peripheral edges of the substrate.
  • the layer of electrically conductive material which may be fabricated from chromium, aluminum, molybdenum, tantalum, silver, tin, gold, and combinations thereof, is then patterned using a first mask, and conventional photolithographic and etching techniques to form said gate contacts and address means.
  • a layer of electrically insulating material such as silicon oxide, silicon nitride, or silicon carbide is disposed atop said patterned layer of electrically conductive material.
  • the layer, the gate insulating layer of electrically insulating material is deposited to a thickness sufficient to assure that there are no defects or apertures formed therein whereby there would be electrical communication between the first layer of electrically conductive material and any subsequently deposited layers.
  • Disposed atop the layer of electrically insulating material is a body of semiconductor material.
  • the body of semiconductor material may be a single layer of semiconductor material such as, for example, amorphous silicon, amorphous germanium or combinations of silicon or germanium alloy materials.
  • the body of semiconductor material may be a multilayered structure in which each layer of semiconductor material is either intrinsic or slightly p- or n-type doped.
  • the body of semiconductor material is a two layer structure comprising a first layer of intrinsic amorphous silicon semiconductor material
  • the second layer is a layer of slightly n-doped amorphous silicon deposited directly atop said layer of intrinsic amorphous silicon material.
  • the second layer of electrically conductive material is a thin layer of metal such as chromium and ⁇ or aluminum.
  • This second electrically conductive layer is then patterned using a second mask, and conventional photolithographic and etching techniques to form the second address line as well as the source and drain contact regions of the transistor.
  • the source and drain contact regions are vertically disposed and electrically insulated from said gate region.
  • This second layer also forms the contact of the pixel capacitor. This layer also serves to protect the semiconductor layer from the harsh environment of subsequent processing steps.
  • the patterned second electrically conductive layer is employed as the mask for the subsequent etching of the body of semiconductor material.
  • all semiconductor material not directly underlying said second layer of electrically conductive material are removed from the substrate.
  • the result is the remaining structure thus includes only the body of semiconductor material underlying said second layer of electrically conductive material all of which is disposed atop the layer of electrically insulating material.
  • a layer of transparent conductive oxide, such as indium-tin-oxide is disposed atop the entire structure.
  • the layer of indium-tin-oxide is patterned using a third mask, and conventional photolithographic and etching techniques to form a second conductive pathway atop such second address line as well as the source and drain regions of the thin film transistor device.
  • the transparent conductive oxide layer is also patterned to be in electrical communication with the pixel capacitor.
  • the layer of indium-tin-oxide may be further patterned so as to form that component.
  • the layer of transparent conductive material as a mask, it is possible to etch the remaining layer of electrically conductive material between the source and drain regions so as to assure that there is no direct electrical communication therebetween.
  • the channel is protected from the harsh processing environment. Exposure to such conditions can degrade performance of the material comprising the channel region of the transistor.
  • Figure 1 is a perspective, plan view of a transistor driven active matrix device, after a first deposition-mask-etch operation.
  • Figure 2a is a cross-sectional view, taken along line A-A of Figure 1, after the deposition of a insulating layer, a semiconductor body, and an electrically conductive layer.
  • Figure 2b is a cross-sectional view taken along line A-A of Figure 1, after a mask- etch operation on the electrically conductive layer illustrated in Figure 2a.
  • Figure 2c is a cross-sectional view, taken along line C-C of Figure 2d, after an
  • Figure 2d is a perspective plan view of the display device of Figure 2c.
  • Figure 3a is a cross-sectional view of the thin film transistor device after deposition and mask patterning of a layer of transparent conductive oxide material, said transparent conductive device adapted to be the first electrode of a liquid crystal picture element, electrically contacting a storage capacitor.
  • Figure 3b is a perspective plan view of the thin film transistor device and first pixel electrode of Figure 3a.
  • Figure 4 is a cross-sectional view of the device in Figure 3b, taken along line A-A thereof, after exposing the channel region of the transistor between the source region and the drain region, by an etch process.
  • an improved electronic display such as a liquid crystal display, and more specifically, by way of example and not by way of limitation, an active matrix liquid crystal display. It is to be understood that while the improved method disclosed and claimed herein is of particular utility in the manufacture of active matrix liquid crystal displays, such process has great utility in other fields of electronics, including, for example, the fabrication of memory devices, microprocessor devices, and other computer circuitry.
  • FIG 1 there is depicted therein a perspective plan view illustrating the first step of the improved process for fabricating an active matrix display plate having a storage capacitor in parallel.
  • a substrate 10 upon which the thin film transistor and any associated circuitry or other components are deposited.
  • the thin film transistor is the switching element for a single picture element of an active matrix liquid crystal display
  • a single substrate may have several million such pixel and switching devices disposed thereon.
  • substrate 10 is typically a rigid member capable of withstanding the elevated temperatures necessary to fabricate active matrix display devices.
  • preferred materials from which the substrate is fabricated include glass, plastic, quartz, and combinations thereof.
  • the substrate 10 is fabricated from Corning Industry's "7059" glass.
  • a layer of electrically conductive material 12 Disposed upon said substrate 10 is a layer of electrically conductive material 12.
  • the electrically conductive material is selected from the group of materials including
  • the electrically conductive material may be deposited by any number of known, conventional, deposition techniques. Examples of acceptable deposition techniques include sputtering, chemical vapor deposition ("CVD"), plasma enhanced chemical vapor
  • the electrically conductive material is a layer of chromium deposited, by a sputtering process, to a thickness of between 500 and 8000 angstroms, and most preferably between 1000 and 4000 angstroms.
  • a first mask is then used with conventional photolithographic and wet etching techniques to form a first address means 14a and gate region 16 of the thin film transistor device and first address means 14b of a second row of devices.
  • the first address means 14a, 14b take the form of an address lines adapted to be connected to electronic circuitry which may be disposed at the periphery of the substrate 10.
  • the first address line 14 is adapted to provide an electrical connection between the peripheral electronic circuitry and the gate region 16 whereby electrical impulses generated by the peripherally mounted circuitry are carried to the gate region.
  • FIG. 2a there is illustrated therein a cross-sectional side view taken along line A-A of Figure 1, and illustrating the deposition of subsequent layers of material forming the display pixel and thin film transistor device.
  • a layer of electrically insulating material 18 disposed atop said substrate 10, and said first address line 14 and gate region 16 is a layer of electrically insulating material 18.
  • Electrically insulating layer 18 may be fabricated from any of a number of electrically insulating materials including, for example, sihcon nitride, silicon carbide, and silicon oxide.
  • the layer of insulating material 18 may be deposited by any number of conventional deposition techniques including, CVD, PECVD, sputtering or evaporation.
  • the electrically insulating layer 18 is a layer of silicon nitride deposited to a thickness of between 3000 and 6000 angstroms, by a PECVD process.
  • the body of semiconductor material 20 may be either a single layer of a single conductivity type, or may be a multilayered structure including both intrinsic and doped layers of semiconductor material.
  • the body of semiconductor material should be deposited to a thickness of between 1000 and 5000 angstroms, and be deposited by any of a number of known deposition techniques, including PECVD, CVD, evaporation, and sputtering.
  • the semiconductor material used in fabricating said body of semiconductor material 20 include silicon, germanium, silicon: germanium alloys, germanium: silicon alloys, and combinations thereof.
  • the body of semiconductor material 20 may also be fabricated of crystalline, polycrystalline, microcrystalline or amorphous semiconductor materials.
  • the body of sihcon material 20 is a two-layer structure comprising a first layer of intrinsic amorphous silicon 20a and a slightly n-doped layer of amorphous silicon 20b.
  • Layer 20a of amorphous sihcon is deposited by PECVD over the entire layer of electrically insulating material 18 to a thickness of between 500 and 3000 angstroms.
  • the layer of n-doped amorphous silicon material 20b is disposed over the entire layer 20a by PECVD to a thickness of between 500 and 3000 angstroms.
  • layer 22 may be fabricated from any of a number of electrically conducting materials including those discussed hereinabove with respect to layer 12. Moreover, those materials may be deposited by conventionally known techniques such as discussed hereinabove with respect to layer 12.
  • layer 22 is a thin layer of metal, such as chromium and aluminum, wherein the chromium is deposited first, and the aluminum atop the chromium. This metal layer is deposited to a total thickness of between 1000 and 3000 angstroms by a sputtering technique.
  • electrically conductive layer 22 is patterned to form second address means 24, source contact region 26 and drain contact region 28 of the transistor device of Figure 2d, and metal contact region 25 of storage capacitor 39 of Figure 3b.
  • a second mask is used with conventional photolithographic and wet etching techniques to form said second address line 24 and contact regions 25, 26 and 28.
  • any number of conventionally known photolithographic and wet etching techniques may be used to pattern second electrically conductive layer 22.
  • the patterned layer of electrically conductive material 22 is used as a mask for the subsequent process of etching the body of semiconductor material. Specifically, by using the patterned, second layer of electrically conductive material 22 as a mask during a subsequent etch step, only that semiconductor material underlying said layer of electrically conductive material 22 will remain after the etch process is completed.
  • the body of semiconductor material 20 is etched using a dry etching technique such as plasma or reactive ion etching ("RIE") technique, or conventional plasma etch.
  • RIE reactive ion etching
  • Figure 2c illustrates the results of employing a dry etch technique such as RIE to the structure of Figure 2b. The body of semiconductor material 20 remains only in those regions underlying the layer of
  • electrically conductive material 22 The layer of electrically insulating material 18 is unaffected by the dry etch technique. Accordingly, the body of semiconductor material 20 and the second electrically conductive layer 22 are vertically disposed, and electrically insulated from the first address line 14 and the gate region 16.
  • the configuration of the first and second address lines 14 and 24 respectively, as well as the gate region 16, source and drain contacts 26, 28, and storage capacitor 39 are illustrated in Figure 2d.
  • electrically insulating layer 18, and semiconductor body 20 are not shown in Figure 2d.
  • the structure illustrated in Figure 2c is a cross-sectional side view taken along line C-C of Figure 2d.
  • the layer of electrically conductive material 30 is a layer of a transparent conductive oxide material, which is deposited over the entire substrate member 10 so as to cover conductive layer 22 and insulating layer 18.
  • transparent conductive materials suitable for this purpose include indium tin oxide, tin oxide, indium oxide, cadmium stannate, and combinations thereof.
  • the layer of transparent conductive material 30 may be deposited by any of a number of known conventional techniques including sputtering, evaporation,
  • layer 30 is a layer of indium tin oxide deposited to a thickness of between 500 and 3000 angstroms by a sputtering process.
  • a third and final mask is used with conventional photolithographic and etching techniques to pattern the layer of transparent conductive material 30 to form a second conductive pathway 32, source region 34 and drain region 36 atop said second layer of electrically conductive material 22.
  • the layer of transparent conductive material may be further patterned to form a first pixel electrode 38 and contact a storage capacitor 39 in parallel with said first pixel electrode of said display.
  • a conventional wet etch technique is used to form structures 32, 34, 36, 38 and 39 illustrated in Figure 3b.
  • the final step in the improved process of fabricating the thin film transistor device is accomplished by using the layer of transparent conductive material 30 and photoresist as above, as a mask for the subsequent process of wet etching the remaining electrically conductive material 22 and layer 20b in region 40 of Figure 3b between source 34 and drain 36.
  • the area of material under region 40 is known as the channel of the transistor device.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Abstract

Procédé amélioré de fabrication d'un dispositif d'affichage à cristaux liquides à matrice active à nombre accru de pixels assurant un affichage de qualité améliorée. Ledit procédé comporte moins de phases de masquage/attaque, ce qui simplifie le processus de fabrication. Ledit procédé prévoit une protection de la région de canal (40) du dispositif de commutation du transistor à couche mince de chaque pixel (38) contre les agressions du milieu de fabrication.
EP93910769A 1993-03-31 1993-04-26 Procede de fabrication d'un affichage a matrice active. Withdrawn EP0647354A4 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE4310640 1993-03-31
DE4310640A DE4310640C1 (de) 1993-03-31 1993-03-31 Verfahren zur Herstellung einer Matrix aus a-Si:H-Dünnschichttransistoren
PCT/US1993/003854 WO1994023446A1 (fr) 1993-03-31 1993-04-26 Procede de fabrication d'un affichage a matrice active

Publications (2)

Publication Number Publication Date
EP0647354A1 EP0647354A1 (fr) 1995-04-12
EP0647354A4 true EP0647354A4 (fr) 1995-08-30

Family

ID=6484430

Family Applications (1)

Application Number Title Priority Date Filing Date
EP93910769A Withdrawn EP0647354A4 (fr) 1993-03-31 1993-04-26 Procede de fabrication d'un affichage a matrice active.

Country Status (3)

Country Link
EP (1) EP0647354A4 (fr)
DE (1) DE4310640C1 (fr)
WO (1) WO1994023446A1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4339721C1 (de) * 1993-11-22 1995-02-02 Lueder Ernst Verfahren zur Herstellung einer Matrix aus Dünnschichttransistoren
DE19754784B4 (de) * 1997-12-10 2004-02-12 Robert Bosch Gmbh Verfahren zur Herstellung einer Matrix aus Dünnschichttransistoren mit Speicherkapazitäten
KR100904757B1 (ko) * 2002-12-30 2009-06-29 엘지디스플레이 주식회사 액정표시장치 및 그의 제조방법

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4102733A (en) * 1977-04-29 1978-07-25 International Business Machines Corporation Two and three mask process for IGFET fabrication
EP0211401A2 (fr) * 1985-08-02 1987-02-25 General Electric Company Transistors à film mince en silicium N+ amorphe pour dispositifs d'affichage à cristaux liquides adressés d'une façon matricielle
EP0211402A2 (fr) * 1985-08-02 1987-02-25 General Electric Company Procédé et structure pour une matrice à transistors à film mince adressant des dispositifs d'affichage à cristaux liquides
US4778560A (en) * 1986-06-03 1988-10-18 Matsushita Electric Industrial Co., Ltd. Method for production of thin film transistor array substrates
EP0288011A2 (fr) * 1987-04-20 1988-10-26 Hitachi, Ltd. Dispositif d'affichage à cristaux liquides et méthode de commande pour ce dispositif
US4990460A (en) * 1989-01-27 1991-02-05 Nec Corporation Fabrication method for thin film field effect transistor array suitable for liquid crystal display
US5060036A (en) * 1988-12-31 1991-10-22 Samsung Electron Devices Co., Ltd. Thin film transistor of active matrix liquid crystal display
JPH0548106A (ja) * 1991-02-20 1993-02-26 Alps Electric Co Ltd 薄膜トランジスタ及びその製造方法
EP0544069A1 (fr) * 1991-11-26 1993-06-02 Casio Computer Company Limited Panneau de transistor à couches minces et sa méthode de fabrication

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5153690A (en) * 1989-10-18 1992-10-06 Hitachi, Ltd. Thin-film device

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4102733A (en) * 1977-04-29 1978-07-25 International Business Machines Corporation Two and three mask process for IGFET fabrication
EP0211401A2 (fr) * 1985-08-02 1987-02-25 General Electric Company Transistors à film mince en silicium N+ amorphe pour dispositifs d'affichage à cristaux liquides adressés d'une façon matricielle
EP0211402A2 (fr) * 1985-08-02 1987-02-25 General Electric Company Procédé et structure pour une matrice à transistors à film mince adressant des dispositifs d'affichage à cristaux liquides
US4778560A (en) * 1986-06-03 1988-10-18 Matsushita Electric Industrial Co., Ltd. Method for production of thin film transistor array substrates
EP0288011A2 (fr) * 1987-04-20 1988-10-26 Hitachi, Ltd. Dispositif d'affichage à cristaux liquides et méthode de commande pour ce dispositif
US5060036A (en) * 1988-12-31 1991-10-22 Samsung Electron Devices Co., Ltd. Thin film transistor of active matrix liquid crystal display
US4990460A (en) * 1989-01-27 1991-02-05 Nec Corporation Fabrication method for thin film field effect transistor array suitable for liquid crystal display
JPH0548106A (ja) * 1991-02-20 1993-02-26 Alps Electric Co Ltd 薄膜トランジスタ及びその製造方法
EP0544069A1 (fr) * 1991-11-26 1993-06-02 Casio Computer Company Limited Panneau de transistor à couches minces et sa méthode de fabrication

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 017, no. 344 (E - 1390) 29 June 1993 (1993-06-29) *
See also references of WO9423446A1 *

Also Published As

Publication number Publication date
EP0647354A1 (fr) 1995-04-12
WO1994023446A1 (fr) 1994-10-13
DE4310640C1 (de) 1994-05-11

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