EP0612053A1 - Video subsystem for a computer system - Google Patents

Video subsystem for a computer system Download PDF

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Publication number
EP0612053A1
EP0612053A1 EP94301116A EP94301116A EP0612053A1 EP 0612053 A1 EP0612053 A1 EP 0612053A1 EP 94301116 A EP94301116 A EP 94301116A EP 94301116 A EP94301116 A EP 94301116A EP 0612053 A1 EP0612053 A1 EP 0612053A1
Authority
EP
European Patent Office
Prior art keywords
monitor
adapter
video
mid
identification signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP94301116A
Other languages
German (de)
English (en)
French (fr)
Inventor
Michael Flinders
Adrian John Hawes
Cynthia Kocialski
Marco Michael Rengan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of EP0612053A1 publication Critical patent/EP0612053A1/en
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/006—Details of the interface to the display terminal
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/04—Exchange of auxiliary data, i.e. other than image data, between monitor and graphics controller
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/04—Exchange of auxiliary data, i.e. other than image data, between monitor and graphics controller
    • G09G2370/042—Exchange of auxiliary data, i.e. other than image data, between monitor and graphics controller for monitor identification

Definitions

  • the present invention relates generally to a computer system architecture and, more specifically, to a video subsystem having a video display adaptor, a monitor cable, and a video display monitor designed so that the monitor identification pins may be reused to provide a bidirectional serial link between the adaptor and the monitor.
  • Personal computer systems are well known in the art. Personal computer systems in general, and IBM Personal Computers in particular, have attained widespread use for providing computer power to many segments of today's modern society.
  • Personal computers can typically be defined as a desktop, floor standing, or portable microcomputer that is comprised of a system unit having a single central processing unit (CPU) and associated volatile and non-volatile memory, including all RAM and BIOS ROM, a system monitor, a keyboard, one or more flexible diskette drives, a fixed disk storage, and an optional printer.
  • CPU central processing unit
  • BIOS ROM volatile and non-volatile memory
  • system monitor including all RAM and BIOS ROM, a system monitor, a keyboard, one or more flexible diskette drives, a fixed disk storage, and an optional printer.
  • One of the distinguishing characteristics of these systems is the use of a motherboard or system planar to electrically connect these components together.
  • These systems are designed primarily to give independent computing power to a single user and are inexpensively priced for purchase by individuals or small businesses. Examples
  • Personal computer systems are typically used to run software to perform such diverse activities as word processing, manipulation of data via spread-sheets, collection and relation of data in databases, displays of graphics, design of electrical or mechanical systems using system-design software, etc.
  • the video display adapter also known as a "microcomputer display adapter” and herein as an “adapter” or a “video adapter,” generates the electrical signals corresponding to the visual image displayed by the video display monitor, also known as a "visual display unit” and herein as a “monitor” or "video monitor.”
  • the adapter may be either an integral part of the system planar or may be an adapter card electrically connected to the system planar via an expansion slot.
  • the monitor cable connecting the monitor to the adapter typically has 15 pins.
  • the 15 pins at the connector mating with the video adapter typically include: red, green, and blue analog video pins, each having an associated ground pin, the horizontal synchronization (HSYNC) and vertical synchronization (VSYNC) timing signal pins, four monitor identification (MID) signal pins, a plug ground pin, a self-test pin, and a sync ground pin.
  • the MID signals are directed toward the adapter and are typically used to convey one piece of static information about the monitor--the type of monitor--to the adapter.
  • the HSYNC and VSYNC signals are generated by the video adapter and directed to the monitor and are used to control the horizontal and vertical blanking within the monitor, respectively.
  • the three video signals are generated by the adapter and directed to the monitor and are analog electrical signals corresponding to the visual image displayed by the monitor.
  • Typical monitor cables provide 4 binary bits of static MID data to the adapter. Four binary bits provide 16 possible MID codes.
  • the MID code for a given monitor is fixed. For example, a monitor with a MID code of 10102 will always have that code. Because the code is fixed, manufacturers hardwire the code into the monitor cable. Thus, typical monitor cables provide only one small piece of information in only one direction--toward the adapter.
  • the 16 possible MID codes were sufficient to cover the spectrum of monitors.
  • the adapter there is a need for the adapter to be able to detect the power-on or power-off status of the monitor.
  • an enhanced mode signalling capability from the adapter to the monitor, whereby the adapter will communicate the desired display parameters (e.g. resolution, frequency, etc.) to the monitor.
  • monitors In addition, there is a need for the monitor to transmit vital product data and monitor characteristics data to the adapter. In short, there is currently a need to transmit many pieces of data either from the monitor to the adapter and vice versa. Current components cannot meet this need because, currently, monitors only supply one piece of permanent information to the adapter and adapters have no way of communicating to the monitors.
  • the present invention provides a video subsystem for a computer system, comprising: a video adapter; a video monitor; and a monitor cable electrically connecting the adapter to the monitor, said cable having at least one monitor identification signal path for delivery of identification signals from the monitor to the adapter, wherein the monitor and the adapter have means for generating a communications link for dynamic communications between them along said identification signal paths.
  • the monitor identification signal paths thus comprise electrical paths between the monitor and the adapter suitable for dynamic communications of control information, as distinct from the electrical paths for delivery of video data which are provided by known display cables.
  • the adapter, the monitor, and the monitor cable are preferably each modified in such a manner that the monitor identification pins are able to be reused to provide an electrical pathway for a bidirectional serial link between the adapter and the monitor.
  • This redesigned video subsystem is termed the "Monitor/Adapter Interconnect Extension" ("MIX").
  • the present invention thus enables expansion of the number of MIDs which it is possible to convey from a monitor to an adapter, without adding additional pins to the monitor cable.
  • the invention preferably also enables relatively large amounts of information (relative to prior art video subsystems) to be communicated between a video adapter and a video monitor, again without adding additional lines or pins to the monitor cable.
  • the MIX adapter is modified to read the MID code from the MID lines as well as communicate bidirectionally over the MID lines.
  • the MIX monitor cable herein the "display cable” is modified so it no longer has the MID code hardwired inside it and, thus, the display cable need no longer be an integral part of the monitor.
  • the display cable merely provides 15 electrical signal paths between the MIX adapter and the MIX monitor.
  • the MIX monitor is modified so it no longer relies on the monitor cable to generate the MID code.
  • the MIX monitor is designed to generate the MID code itself.
  • the MIX monitor is designed with means to communicate bidirectionally with the adapter over the MID lines.
  • both the MIX monitor and the MIX adapter presume that they are not connected to a MIX-capable counterpart.
  • the MIX monitor presents a fixed MID code along the MID lines.
  • the MIX adapter reads any MID code from the MID lines.
  • the adapter starts the handshake by signalling to the monitor by setting both the HSYNC and VSYNC to a known state, then toggling one or both of them from one state to the other for a fixed number of toggles at a predetermined rate.
  • a non-MIX monitor will ignore the signals.
  • a MIX monitor will recognize that it is connected to a MIX adapter and will respond by presenting a special code on the MID lines. This special code allows the MIX adapter to recognize that a MIX monitor is powered up and has received the handshake signal. The monitor then stops asserting the MID code on the MID lines and the MIX adapter and MIX monitor are free to communicate bidirectionally along the MID lines.
  • the present invention to provide a video subsystem in which the adapter, the monitor, and the monitor cable are each modified to enable the MID lines to be reused as a bidirectional communication link.
  • Figure 1A is a schematic view of a prior art video subsystem.
  • Figure 1B is an electrical schematic of a prior art video subsystem showing the monitor identification subcircuit.
  • Figure 2A is a schematic view of a video subsystem according to an embodiment of the present invention.
  • Figure 2B is an electrical schematic of a video subsystem according to an embodiment of the present invention showing the MID/MIX subcircuit.
  • Figures 3A through 3E are timing diagrams showing various alternative communication configurations for communicating over the reused MID lines.
  • FIG. 1A and 1B show a prior art video subsystem 10.
  • a typical prior art video subsystem 10 has a video adapter 20 connected to a video monitor 22.
  • the monitor 22 has associated with it an integral monitor cable 24 attached to the monitor 22 at an attachment point 26.
  • the monitor cable 24 connects to the video adapter 20 at a display connector 28 and allows electrical communication between the video adapter 20 and the video monitor 22.
  • Prior art video adapters 20 are well known in the art. They typically include a ROM BIOS, a test subcircuit, a video memory, a digital to analog converter, a cathode ray tube (CRT) controller, a sequencer, a graphics controller, and an attribute controller.
  • Prior art monitors 22 are also well known in the art. They typically include a power supply, a CRT subcircuit, and an input subcircuit.
  • the display connector 28 is typically a 15-pin connector and typically brings 14 signal lines out from the video adapter 20: three video signal lines (red, green, and blue), each with an associated ground line; four monitor identification (MID) signal lines; a horizontal synchronization timing signal (HSYNC) line; a vertical synchronization timing signal (VSYNC) line; a sync ground line; a self-test signal line; and a plug ground line.
  • the three video signals are analog signals ranging from 0.0 to 0.7 VDC.
  • the HSYNC, and VSYNC signals are typically TTL or "Fast" TTL signals with typical TTL or "Fast” TTL logic levels, which are well known in the art.
  • the MID lines are typically pulled up to a high logic state with pull-up resistors of an appropriate value within the adapter 20.
  • FIG. 1B is a schematic diagram showing an example of a prior art monitor ID subcircuit 30, which is a combination of the hardwired MID subcircuit 32 within the monitor cable 24 and the test subcircuit 34 of the adapter 20.
  • the four MID lines MID0-MID3 provide a four-bit nibble of binary data that can be read by monitor ID input buffer 36 of the test subcircuit 34 of the adapter 20.
  • the monitor ID lines MID0-MID3 are pulled up to a logic 1 by associated pull-up resistors R0-R3, which are part of the test subcircuit 34 of the video adapter 20. Recall that the MID lines are either logic 1 or logic 0.
  • a desired MID code bit may easily be hardwired within the monitor cable 24 by either tying the desired MID line to the ground line (if a MID code bit of logic level 0 is desired) or not tying the desired MID line to the ground line (if a MID code bit of logic level 1 is desired) within the monitor cable 24.
  • the MID1 and MID3 lines are tied to ground at 38 and 40, respectively, therefore, they are at logic level 0 when the monitor cable 24 is plugged into the display connector 34, as shown in Figure 1B. Conversely, the MID0 and MID2 lines are not tied to ground, therefore, they remain at logic level 1. The MID code is then readable by the MID input buffer 36 of the adapter 20.
  • the monitor cable 24 typically comprises at least nine conductors 42 that electrically connect the adapter 20 ,to the monitor 22. Five conductors transmit the three video data signals, HSYNC, and VSYNC from the adapter 20, which generates these signals, to the monitor 22, which receives these signals. The four remaining conductors provide ground paths and include the three video ground lines and the sync ground line. As shown in Fig. 1B, the four MID lines MID0-MID3 do not reach the monitor 22. However, the MID lines MID0-MID3 can be extended into the monitor 22, where they are hardwired to reflect a particular MID code. The critical feature of the prior art MID subcircuit 30 is that the MID code is hardwired.
  • Using the prior art video subsystem 10 is very simple. The user merely plugs the monitor cable 24 into the display connector 28 of the video adapter 20. Either the video adapter 20 or the monitor 22 may be turned on first. Neither is aware of the other's power status.
  • the MID input buffer 36 of the test subcircuit 34 When the adapter 20 is powered on, the MID input buffer 36 of the test subcircuit 34 reads the MID code from the MID lines MID0-MID3 and transmits it to remaining adapter circuitry 44 via remaining test subcircuitry 46, thereby making this code available for use by the adapter 20 and the software running on the computer system. Then remaining adapter circuitry 44 of the adapter 20 starts transmitting the three video data signals (R, G, and B), the VSYNC signal, and the HSYNC signal. As previously mentioned, the three video ground lines and the sync ground lines do not have associated directed signals per se, but merely provide electrical ground paths.
  • Some newer monitor cables 24 have MID codes based on four bits of four possible states: 0, 1, H, or V. That is, instead of being limited to either tying a MID line to ground or not (resulting in either logic 0 or logic 1, respectively), some monitor cables either do not tie a MID line to anything (resulting in logic 1), or tie the MID to either ground, HSYNC, or VSYNC. Thus, a resulting MID code may be, for example, 1H1V s or 00HV s ("s" meaning "special”). In systems with this type of MID, four reads are needed to adequately determine the MID code.
  • HSYNC and VSYNC are placed into a logic 1 state by the remaining adapter circuitry 44 and the MID code is read by the MID input buffer 36. Any of the MID lines MID0-MID3 at logic 0 during that read are deemed tied to ground and at special level "0.”
  • HSYNC is placed into a logic 0 state and VSYNC is placed into a logic 1 state by the remaining adapter circuitry 44 and the MID code is read by the MID input buffer 36.
  • Any of the MID lines MID0-MID3 at logic 0 during that read, that were not at logic 0 before, are deemed tied to HSYNC and at special level "H.”
  • HSYNC is placed into a logic 1 state and VSYNC is placed into a logic 0 state by the remaining adapter circuitry 44 and the MID code is read by the MID input buffer 36.
  • HSYNC is placed into a logic 0 state and VSYNC is placed into a logic 0 state by the remaining adapter circuitry 44 and the MID code is read by the MID input buffer 36.
  • Any of the MID lines MID0-MID3 NOT at logic 0 during that read, are deemed not tied to either ground, HSYNC, or VSYNC and are at special level "1.” Thus, these four reads allow the system to determine the true MID code.
  • the monitor 22 will have nothing to display until the adapter 20 is powered on. Once the adapter 20 is powered on and begins transmitting the five directed signals (R, G, B, HSYNC, and VSYNC) the monitor 22 will display a visual image corresponding to the five directed signals.
  • the prior art video adapter 20, the prior art video monitor 22, and the prior art monitor cable 24 of the prior art video subsystem 10 are modified so that the MID lines MID0-MID3 can be reused to provide a communication link between the adapter and the monitor.
  • FIGS 2A and 2B show a video subcircuit 110 of the present invention.
  • the video subcircuit 110 comprises a video adapter 120 electrically connected to a video monitor 122 by a display cable 124.
  • the display cable 124 may be, but is not required to be, an integral part of either the video adapter 120, or the video monitor 122, or both the adapter 120 and the monitor 122, or may be an integral part of neither the adapter 120 nor the monitor 122.
  • the display cable 124 is an integral part of neither the adapter 120 or the monitor 122.
  • the display cable 124 connects to the monitor 122 at a monitor connector 126 and connects to the adapter 120 at a display connector 128.
  • R, G, and B are analog signals ranging from 0.0 to 0.7 VDC.
  • HSYNC and VSYNC are TTL signals.
  • the four ground lines (three video ground lines and the sync ground line) remain the same and merely provide ground paths.
  • the MID signals become I2C (inter-integrated circuit) signals.
  • the I2C bus is an open collector serial bus offered by Signetics Corp., a subsidiary of Philips N.V.
  • Figure 2B shows a MID/MIX subcircuit 130 comprising the display cable 124 and portions 140 and 142 of the adapter 120 and the monitor 122, respectively.
  • the MID input buffer 36 of the prior art adapter 20 is replaced by an adapter MID/MIX subcircuit 136.
  • the hardwired MID subcircuit 32 within the prior art monitor cable 24 is replaced with four conductors COMM0-COMM3. These communications lines COMM0-COMM3, previously the MID lines MID0-MID3 and associated with the same pins of the 15-pin connector, will carry the MID code from the monitor 122 to the adapter 120 and will subsequently provide a communications path between the adapter 120 and the monitor 122.
  • the communication lines COMM0-COMM3 are pulled up to logic 1 by pull-up resistors R0-R3.
  • a monitor MID/MIX subcircuit 138 is added.
  • the adapter MID/MIX subcircuit 136 and the monitor MID/MIX subcircuit 138 serve numerous functions: (1) they serve to simulate the hardwired MID subcircuit 32 of the prior art video subsystem 10, (2) they perform any handshaking needed to identify MIX-capable counterparts, and (3) they perform the dynamic communication between the video adapter 120 and the monitor 122.
  • Remaining monitor circuitry 146 differs from the circuitry of a prior art monitor 22 in several respects: (1) The remaining monitor circuitry 146 interfaces with and controls the monitor MID/MIX subcircuit 138 and must be designed to do so. (2) The remaining monitor circuitry 146 must be designed with any additional circuitry needed to provide the information to be sent to the adapter 120, such as vital product data and monitor characteristics. (3) Lastly, the remaining monitor circuitry 146 must be designed with any additional circuitry needed to implement any commands sent from the adapter 120, such as changing pixel resolution or changing signal frequency. In short, the nature and extent of the changes needed in the remaining monitor circuitry 146 depends entirely on the nature and the extent of the functions added to the monitor 122.
  • remaining adapter circuitry 148 and remaining test subcircuitry 150 must be designed with any circuitry needed to perform any added functions. Like the remaining monitor circuitry 146, the nature and extent of the changes needed in the remaining adapter circuitry 148 and the remaining test subcircuitry depends entirely on the nature and the extent of the functions added to the adapter 120.
  • the adapter 120 behaves as a prior art adapter 20.
  • the adapter 120 will attempt to read, using either one or four reads as described above, the MID code from the four communications lines COMM0-COMM3 using the adapter MID/MIX subcircuit 136.
  • the MID code the adapter 120 will read depends on what is attached to the display connector 128 of the adapter 120. If the adapter 120 is not connected to any monitor cable at all, the communication lines COMM0-COMM3 will remain pulled up to logic level 1 and the adapter 120 will read a MID code of 11112 or 1111 s .
  • the adapter 120 If the adapter 120 is connected to a prior art monitor 24 of a prior art monitor 22, the adapter 120 will read the MID code from the hardwired MID subcircuit 32 of the prior art monitor cable 24, whether the prior art monitor 22 is powered on or not. Again, the adapter reads the MID codes from the communication lines COMM0-COMM3 using the adapter MID/MIX subcircuit 136.
  • the MID code the adapter 120 reads will depend on whether the monitor 122 is powered on or not. If the monitor 122 is not powered on, the communication lines COMM0-COMM3 will remain pulled up to logic level 1 by pull-up resistors R0-R3 and the adapter 120 will read a MID code of 11112 or 1111 s . If the monitor 122 is powered on then the monitor MID/MIX subcircuit 138 of the monitor 122 can present whatever MID code it desires on the communication lines COMM0-COMM3 for the adapter 120 to read. Once the adapter 120 reads the MID code, it makes the MID code available to the software.
  • the adapter 120 determines whether the connected monitor is MIX-capable or not. That is, the adapter 120 must determine if the unknown monitor attached is a monitor 122 of the present invention or a prior art monitor 22. Therefore, the adapter 120 sends a trigger signal to the unknown monitor that lets the unknown monitor know that the adapter 120 is MIX-capable.
  • this trigger signal consists of the adapter 120 placing both HSYNC and VSYNC in the same known logic state then toggling them both simultaneously from one state to the other at a predetermined rate (e.g. , approximately 10 Khz) for a predetermined number of cycles (e.g. , eight complete cycles).
  • a predetermined rate e.g. , approximately 10 Khz
  • a predetermined number of cycles e.g. , eight complete cycles
  • a non-MIX monitor 20 will ignore the trigger signal.
  • a MIX monitor 122 will respond to the trigger signal generated by the adapter 120 in such a manner that the adapter 120 knows the monitor 122 is indeed a MIX-capable monitor 122.
  • the MIX monitor 122 will present a Powered on ID (PID) code along the communication lines COMM0-COMM3 to complete the handshake.
  • PID Powered on ID
  • the exact code is immaterial. The only requirement is that the PID be different from the code presented before handshaking, so the adapter 120 knows a MIX monitor 122 is present.
  • the monitor MID/MIX subcircuit 138 ceases asserting the MID code along the communication lines COMM0-COMM3, allowing them to be pulled up to the open-collector floating state of 11112 by the pull-up resistors R0-R3.
  • the adapter 120 and monitor 122 are then free to begin communicating along the communication lines COMM0-COMM3 using the adapter MID/MIX subcircuit 136 and the monitor MID/MIX subcircuit 138.
  • the I2C bus specifically contemplates bidirectional serial communication using two of the four lines, but numerous other communication schemes are possible.
  • the adapter 120 and monitor 122 could communicate along just one communication line: a single bidirectional data line, as shown in Figure 3A.
  • they could communicate using a clock line and a data line, thereby using two communication lines, as shown in Figure 3B.
  • the adapter 120 and monitor 122 could communicate using two data lines, a clock line, and a framesync line, as shown in Figure 3D; or they could use three data lines and a single clock line, as shown in Figure 3E.
  • Unidirectional versions of the bidirectional communication schemes listed above are also possible. In the best mode, the communication is bidirectional using just two communication lines: a bidirectional clock line and a bidirectional data line, as shown in Figure 3B.
  • the adapter 120 and the monitor 122 share a common data line or lines.
  • This invention also contemplates using unidirectional data lines.
  • the adapter 120 and the monitor 122 could communicate using a common clock line, generated by the adapter, a data line directed by the adapter 120 to the monitor 122, and a data line directed by the monitor 122 to the adapter 122, thereby using three communications lines. Numerous combinations and permutations of the above examples are possible and are intended to come within the scope of the invention.
  • the monitor 122 If the monitor 122 is powered off when the adapter 120 transmits the trigger signal, either the adapter 120 will not assert the trigger signal or the monitor 122 will miss the trigger signal. Therefore, the monitor 122 must have some way of signalling to the adapter 120 that (1) it is now powered on, and, more importantly, (2) it is a MIX-capable monitor.
  • the adapter 120 can poll the communication lines COMM0-COMM3 for a code other than 11112 or 1111 s . Once a different code is read, the adapter 120 knows a monitor (type unknown) is now attached and the adapter 120 may then initiate handshaking, as described above.
  • PID Powered on ID
  • the adapter 120 would periodically poll the communications lines COMM0-C0MM3 for the PID code. Once the adapter 120 receives the appropriate PID code, it would present the trigger signal. The monitor 122 would respond to the trigger signal with an appropriate MID code, thereby completing the handshaking.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Two-Way Televisions, Distribution Of Moving Picture Or The Like (AREA)
  • Information Transfer Systems (AREA)
  • Controls And Circuits For Display Device (AREA)
EP94301116A 1993-02-16 1994-02-16 Video subsystem for a computer system Withdrawn EP0612053A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US1779493A 1993-02-16 1993-02-16
US17794 1996-05-15

Publications (1)

Publication Number Publication Date
EP0612053A1 true EP0612053A1 (en) 1994-08-24

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EP94301116A Withdrawn EP0612053A1 (en) 1993-02-16 1994-02-16 Video subsystem for a computer system

Country Status (3)

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EP (1) EP0612053A1 (ko)
JP (1) JPH06259050A (ko)
KR (1) KR970003088B1 (ko)

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EP0708399A3 (ko) * 1994-10-14 1996-05-08 Ibm
US5652845A (en) * 1993-02-10 1997-07-29 Hitachi, Ltd. Display apparatus
EP0778516A3 (en) * 1995-12-01 1997-11-12 Texas Instruments Incorporated Hardware independent display device interface
GB2314493A (en) * 1996-06-18 1997-12-24 Lg Electronics Inc Monitor communicates with computer via serial peripheral interface
EP0827131A2 (en) * 1996-08-29 1998-03-04 Canon Kabushiki Kaisha System generating display control signals adapted to the capabilities of the display device
US6243780B1 (en) 1996-11-29 2001-06-05 Lg Electronics Inc. Interface of a monitor communicating with personal computer
WO2002067234A2 (de) * 2001-02-16 2002-08-29 Siemens Aktiengesellschaft Displaymodul
EP1256923A2 (en) * 2001-05-11 2002-11-13 Eizo Nanao Corporation Display device and image display system with adjustment of video circuit parameters in accordance with application software
EP1507253A2 (de) * 2003-08-11 2005-02-16 Kontron Embedded Modules GmbH Anzeigeadapter

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DE4025295A1 (de) * 1989-08-10 1991-02-14 Apple Computer Computer zur wiedergabe von videodaten auf einem monitor
EP0456923A1 (en) * 1990-05-14 1991-11-21 International Business Machines Corporation Display system

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Cited By (24)

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Publication number Priority date Publication date Assignee Title
US5887147A (en) * 1993-02-10 1999-03-23 Hitachi, Ltd. Display apparatus
US5652845A (en) * 1993-02-10 1997-07-29 Hitachi, Ltd. Display apparatus
US6549970B2 (en) 1993-02-10 2003-04-15 Hitachi, Ltd. Display unit with controller enabling bi-directional communication with computer
US6513088B2 (en) 1993-02-10 2003-01-28 Hitachi, Ltd. Display unit and method enabling bi-directional communication with video source
US6247090B1 (en) 1993-02-10 2001-06-12 Hitachi, Ltd. Display apparatus enabled to control communicatability with an external computer using identification information
EP0708399A3 (ko) * 1994-10-14 1996-05-08 Ibm
US5948091A (en) * 1995-12-01 1999-09-07 Texas Instruments Incorporated Universal digital display interface
EP0778516A3 (en) * 1995-12-01 1997-11-12 Texas Instruments Incorporated Hardware independent display device interface
GB2314493B (en) * 1996-06-18 1998-12-16 Lg Electronics Inc Monitor communicable with personal computer
GB2314493A (en) * 1996-06-18 1997-12-24 Lg Electronics Inc Monitor communicates with computer via serial peripheral interface
EP0827131A3 (en) * 1996-08-29 1999-03-03 Canon Kabushiki Kaisha System generating display control signals adapted to the capabilities of the display device
EP0827131A2 (en) * 1996-08-29 1998-03-04 Canon Kabushiki Kaisha System generating display control signals adapted to the capabilities of the display device
US6661414B1 (en) 1996-08-29 2003-12-09 Canon Kabushiki Kaisha Display system with a displaying apparatus that transmits control information
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KR940020232A (ko) 1994-09-15
JPH06259050A (ja) 1994-09-16
KR970003088B1 (ko) 1997-03-14

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