EP0591769A3 - Process for manufacturing a self-adjusted contact and semiconductor structure. - Google Patents

Process for manufacturing a self-adjusted contact and semiconductor structure. Download PDF

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Publication number
EP0591769A3
EP0591769A3 EP93115286A EP93115286A EP0591769A3 EP 0591769 A3 EP0591769 A3 EP 0591769A3 EP 93115286 A EP93115286 A EP 93115286A EP 93115286 A EP93115286 A EP 93115286A EP 0591769 A3 EP0591769 A3 EP 0591769A3
Authority
EP
European Patent Office
Prior art keywords
self
adjusted
contact
manufacturing
semiconductor structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP93115286A
Other languages
German (de)
French (fr)
Other versions
EP0591769A2 (en
EP0591769B1 (en
Inventor
Hanno Dipl-Phys Melzner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of EP0591769A2 publication Critical patent/EP0591769A2/en
Publication of EP0591769A3 publication Critical patent/EP0591769A3/en
Application granted granted Critical
Publication of EP0591769B1 publication Critical patent/EP0591769B1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

A self-adjusted (self-aligned) contact (via) (5), in particular an S/D region (2) bit-line contact which is self-adjusted with respect to the word line is produced as a result of adjacent word lines (3a) being at a greater distance from one another in the vicinity of the S/D region than at other points. The narrow gaps are completely filled by surface-wide deposition of an insulating interlayer and subsequent anisotropic edging, while insulating spacers (4'') are formed on the side walls of the encapsulated word lines (3) in the enlarged gaps, together with a self-adjusted contact (5). <IMAGE>
EP93115286A 1992-09-29 1993-09-22 Process for manufacturing a self-adjusted contact and semiconductor structure Expired - Lifetime EP0591769B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE4232621A DE4232621C1 (en) 1992-09-29 1992-09-29 Manufacturing process for a self-aligned contact hole and semiconductor structure
DE4232621 1992-09-29

Publications (3)

Publication Number Publication Date
EP0591769A2 EP0591769A2 (en) 1994-04-13
EP0591769A3 true EP0591769A3 (en) 1994-12-14
EP0591769B1 EP0591769B1 (en) 1999-01-20

Family

ID=6469129

Family Applications (1)

Application Number Title Priority Date Filing Date
EP93115286A Expired - Lifetime EP0591769B1 (en) 1992-09-29 1993-09-22 Process for manufacturing a self-adjusted contact and semiconductor structure

Country Status (7)

Country Link
US (2) US5432381A (en)
EP (1) EP0591769B1 (en)
JP (1) JPH06196569A (en)
KR (1) KR100279014B1 (en)
AT (1) ATE176085T1 (en)
DE (2) DE4232621C1 (en)
TW (1) TW234776B (en)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR970004922B1 (en) * 1993-07-27 1997-04-08 삼성전자 주식회사 Wiring structure of high integrated semiconductor
JP2947054B2 (en) * 1994-03-04 1999-09-13 ヤマハ株式会社 Wiring formation method
JP3104534B2 (en) * 1994-06-27 2000-10-30 ヤマハ株式会社 Semiconductor device and its manufacturing method.
JPH0917863A (en) * 1995-06-29 1997-01-17 Rohm Co Ltd Semiconductor device and wiring method of semiconductor device
JP3277103B2 (en) * 1995-09-18 2002-04-22 株式会社東芝 Semiconductor device and manufacturing method thereof
JPH10321724A (en) * 1997-03-19 1998-12-04 Fujitsu Ltd Semiconductor device and manufacture therefor
US6348411B1 (en) 1998-09-03 2002-02-19 Micron Technology, Inc. Method of making a contact structure
US6166441A (en) * 1998-11-12 2000-12-26 Intel Corporation Method of forming a via overlap
US6566759B1 (en) * 1999-08-23 2003-05-20 International Business Machines Corporation Self-aligned contact areas for sidewall image transfer formed conductors
US6261924B1 (en) 2000-01-21 2001-07-17 Infineon Technologies Ag Maskless process for self-aligned contacts
KR100352909B1 (en) * 2000-03-17 2002-09-16 삼성전자 주식회사 Method of forming self-aligned contact structure in semiconductor device and self-aligned contact structure fabricated thereby
US6976181B2 (en) * 2001-12-20 2005-12-13 Intel Corporation Method and apparatus for enabling a low power mode for a processor
KR20030087744A (en) * 2002-05-09 2003-11-15 삼성전자주식회사 Method for forming contact hole in integrated circuit
DE10342547B4 (en) * 2003-09-12 2007-02-08 Infineon Technologies Ag Method for producing an integrated circuit device with through-connection elements and connection units
WO2015040798A1 (en) * 2013-09-20 2015-03-26 パナソニックＩｐマネジメント株式会社 Semiconductor device and manufacturing method therefor

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4916087A (en) * 1988-08-31 1990-04-10 Sharp Kabushiki Kaisha Method of manufacturing a semiconductor device by filling and planarizing narrow and wide trenches
JPH0429318A (en) * 1990-05-25 1992-01-31 Oki Electric Ind Co Ltd Manufacture of semiconductor device
JPH04279037A (en) * 1991-03-07 1992-10-05 Toshiba Corp Manufacture of solid image pick-up element
JPH04315454A (en) * 1991-04-12 1992-11-06 Sony Corp Manufacture of semiconductor device

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0388075B1 (en) * 1989-03-16 1996-11-06 STMicroelectronics, Inc. Contacts for semiconductor devices
JP2689703B2 (en) * 1989-08-03 1997-12-10 富士電機株式会社 MOS type semiconductor device
JPH03201532A (en) * 1989-12-28 1991-09-03 Casio Comput Co Ltd Formation of pore or fine trench
US5275972A (en) * 1990-02-19 1994-01-04 Matsushita Electric Industrial Co., Ltd. Method for fabricating a semiconductor integrated circuit device including the self-aligned formation of a contact window
US5094900A (en) * 1990-04-13 1992-03-10 Micron Technology, Inc. Self-aligned sloped contact

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4916087A (en) * 1988-08-31 1990-04-10 Sharp Kabushiki Kaisha Method of manufacturing a semiconductor device by filling and planarizing narrow and wide trenches
JPH0429318A (en) * 1990-05-25 1992-01-31 Oki Electric Ind Co Ltd Manufacture of semiconductor device
JPH04279037A (en) * 1991-03-07 1992-10-05 Toshiba Corp Manufacture of solid image pick-up element
JPH04315454A (en) * 1991-04-12 1992-11-06 Sony Corp Manufacture of semiconductor device

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 16, no. 196 (E - 1200) 12 May 1992 (1992-05-12) *
PATENT ABSTRACTS OF JAPAN vol. 17, no. 150 (E - 1339) 25 March 1993 (1993-03-25) *
PATENT ABSTRACTS OF JAPAN vol. 17, no. 81 (E - 1321) 18 February 1993 (1993-02-18) *

Also Published As

Publication number Publication date
EP0591769A2 (en) 1994-04-13
DE4232621C1 (en) 1994-03-10
US5460690A (en) 1995-10-24
US5432381A (en) 1995-07-11
DE59309324D1 (en) 1999-03-04
KR940007994A (en) 1994-04-28
JPH06196569A (en) 1994-07-15
EP0591769B1 (en) 1999-01-20
KR100279014B1 (en) 2001-02-01
ATE176085T1 (en) 1999-02-15
TW234776B (en) 1994-11-21

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