EP0565807A1 - MOS-Leistungstransistorbauelement - Google Patents

MOS-Leistungstransistorbauelement Download PDF

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Publication number
EP0565807A1
EP0565807A1 EP92830189A EP92830189A EP0565807A1 EP 0565807 A1 EP0565807 A1 EP 0565807A1 EP 92830189 A EP92830189 A EP 92830189A EP 92830189 A EP92830189 A EP 92830189A EP 0565807 A1 EP0565807 A1 EP 0565807A1
Authority
EP
European Patent Office
Prior art keywords
region
source
fact
transistor
regions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP92830189A
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English (en)
French (fr)
Inventor
Guido Brasca
Edoardo Botti
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
SGS Thomson Microelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics SRL filed Critical SGS Thomson Microelectronics SRL
Priority to EP92830189A priority Critical patent/EP0565807A1/de
Priority to JP05088938A priority patent/JP3131525B2/ja
Priority to US08/047,803 priority patent/US5396119A/en
Publication of EP0565807A1 publication Critical patent/EP0565807A1/de
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits

Definitions

  • the present invention relates to a MOS power transistor device.
  • MOS power transistors are known to be damaged by exceeding the maximum power dissipatable by the device (and which is constant alongside variations in drain-source voltage), as in the case of shortcircuiting or overloading, which produce a substantial increase in the temperature of the chip integrating the MOS transistors.
  • several types of protection have been proposed, none of which, however, have proved entirely effective.
  • a bipolar sensing transistor is integrated and appropriately located inside the MOS power transistor, for detecting the temperature inside the chip integrating the MOS transistor, and, in the event the maximum permissible temperature is exceeded, so regulating the gate-source drop of the MOS transistor as to prevent a further increase in temperature.
  • Temperature sensing devices as applied to bipolar power transistors are already known (see, for example, the article by Robert J. Widlar and Mineo Yamatake entitled “Dynamic Safe-Area Protection for Power Transistors Employs Peak-Temperature Limiting", IEEE Journal of Solid-State Circuits, Vol. SC-22, No.1, February 1987).
  • Such devices consist of a PN junction distributed throughout the bipolar power transistor close to the active emitter.
  • the junction is biased by a current source so that the drop at the junction is zero when the limit temperature is reached.
  • An operational amplifier is input-connected to the junction terminals, and, on the limit temperature being exceeded, takes over control of the base circuit of the power transistor to regulate the temperature.
  • Such a solution is not applicable to MOS power transistors.
  • Number 1 in Fig.1 indicates a MOS power transistor to be protected against overloading or shortcircuiting.
  • a bipolar NPN transistor 2 having the collector region connected to the gate regions of MOS transistor 1 and to gate terminal G; the emitter region connected to the source regions of MOS transistor 1 and to source terminal S; and the base region connected to its own terminal B.
  • MOS transistor 1 also presents a drain terminal D.
  • Transistor 2 defines a temperature sensing element, and is integrated in an insulated pocket formed inside MOS transistor 1 to produce a four-terminal device 3 which, by virtue of being integrated with it, is capable of detecting the temperature of MOS transistor 1.
  • device 3 is shown by way of example in Fig.3, which shows a cross section of chip 10 through the portion of MOS transistor 1 integrating sensing transistor 2.
  • Fig.3 shows a grounded P-type substrate 11 over which extends an N-type epitaxial layer 12.
  • N-type epitaxial layer 12 Across the junction formed by substrate 11 and epitaxial layer 12, there extend buried N+-type layers 13a, 13b. Together with the epitaxial layer, buried layers 13a form the drain regions of MOS transistor 1, while layer 13b forms the collector of sensing transistor 2.
  • Epitaxial layer 12 is divided into a number of pockets isolated from one another by P-type isolating regions 14 extending from substrate 11 to the upper surface defined by epitaxial layer 12.
  • one isolating region 14a defines a loop interposed partially between buried layers 13a, 13b, so as to separate pocket 12b housing sensing transistor 2 from pocket 12a housing MOS transistor 1, and which surrounds pocket 12b on all sides.
  • Buried layers 13a, 13b are connected by respective N+-type sinkers 15a, 15b to drain contact 16 and collector contact 17 respectively.
  • Epitaxial pocket 12b houses the P-type base region 18 of sensing transistor 2, connected to contact 20 and in turn housing an N+-type emitter region 19 connected to contact 21.
  • Pocket 12a houses P-type body regions 23, each of which houses a pair of N+-type regions 24 forming the source regions of MOS transistor 1 and connected to respective contacts 25.
  • connections 30 for connecting source regions 24 to one another, to emitter region 19 and terminal S; connections 31 for connecting gate regions 27 to one another, to collector region 15b, 13b and terminal G; connections 32 for connecting drain regions 12a, 13a, 15a to one another and to terminal D; and connection 33 for connecting base region 18 to terminal B.
  • the above connections may be metallized for high current, and consist of a polycrystalline silicon layer for low current (in this case the gate connections). The process permitting, provision may also be made for metallization at two levels.
  • Fig.2 shows one possible application of Fig.1 device 3, wherein 4 indicates an ordinary circuit for driving MOS transistor 1, and 5 a voltage source between base terminal B of sensing transistor 2 and source terminal S, for biasing the base-emitter junction of sensing transistor 2 to reference voltage V REF .
  • sensing transistor 2 is off, and MOS transistor 1 operates normally.
  • sensing transistor 2 gradually starts to conduct up to temperature T UM , at which it absorbs the maximum current I MAX supplied by drive circuit 4, thus rendering control of the voltage drop at the gate-source junction of MOS transistor 1 independent of drive circuit 4.
  • it is sensing transistor 2 that sets the voltage drop V GS at the gate-source junction so that it equals the voltage drop between its own collector and emitter, thus preventing any further increase in temperature, and maintaining thermal feedback of the system at temperature T UM .
  • Fig.4 shows a further embodiment of the device, suitable for applications in which the drive device of MOS transistor 1 consists of a differential stage (P-channel MOS or bipolar PNP transistors).
  • the drive device of MOS transistor 1 consists of a differential stage (P-channel MOS or bipolar PNP transistors).
  • collector terminal C of sensing transistor 2 instead of being shortcircuited with the gate terminal of MOS transistor 1, is outside the device, here indicated by 3'.
  • device 3' is preferably connected to the drive circuit as shown in Fig.5, wherein the drive circuit 4' comprises a differential stage 35 in turn comprising a bias current source 36 supplying current I MAX ; a pair of PNP transistors 37, 38; and a differential-single output conversion stage comprising an NPN transistor 39 and diode-connected NPN transistor 40.
  • the drive circuit 4' comprises a differential stage 35 in turn comprising a bias current source 36 supplying current I MAX ; a pair of PNP transistors 37, 38; and a differential-single output conversion stage comprising an NPN transistor 39 and diode-connected NPN transistor 40.
  • current source 36 is located between the supply line and mutually connected emitters of transistors 37, 38; the emitters of transistors 37, 38 are also connected to collector terminal C of sensing transistor 2; the base terminal of transistor 37 defines the input of differential stage 35; the base terminal of transistor 38 is connected to drain terminal D of MOS transistor 1; the collector of transistor 37 is connected to the collector of transistor 39 and gate terminal G of MOS transistor 1; the emitter of transistor 39 is grounded, and the base connected to the base of diode-connected transistor 40, the collector of which is connected to the collector terminal of transistor 38.
  • a high-power resistor 41 is provided between gate terminal G of MOS transistor 1 and ground, and, here too, a voltage source 5 is connected between the base and emitter terminals of sensing transistor 2.
  • Device 3' in Fig.5 operates in the same way as Fig.2 device 3, i.e. on reaching temperature T UM , it absorbs the maximum current I MAX supplied by source 36, so as to control the gate-source voltage drop of MOS transistor 1 and so prevent any further increase in temperature, but without unbalancing differential stage 4' at temperatures below T UM (normal operating condition).
  • the device according to the present invention provides for effective SOA (Safe Operating Area) protection, troublefree layout, and a good MOS transistor/sensing transistor area ratio.
  • SOA Safe Operating Area
  • control circuit ensuring safe operation of the device is extremely straightforward in design and, therefore, highly reliable and cheap to produce.
  • the solutions described herein provide for fully exploiting the high output power capacity of the MOS transistor, even in the presence of highly reactive loads.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Bipolar Transistors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electronic Switches (AREA)
  • Semiconductor Integrated Circuits (AREA)
EP92830189A 1992-04-17 1992-04-17 MOS-Leistungstransistorbauelement Ceased EP0565807A1 (de)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP92830189A EP0565807A1 (de) 1992-04-17 1992-04-17 MOS-Leistungstransistorbauelement
JP05088938A JP3131525B2 (ja) 1992-04-17 1993-04-15 Ｍｏｓパワー・トランジスタ・デバイス
US08/047,803 US5396119A (en) 1992-04-17 1993-04-15 MOS power transistor device with temperature compensation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP92830189A EP0565807A1 (de) 1992-04-17 1992-04-17 MOS-Leistungstransistorbauelement

Publications (1)

Publication Number Publication Date
EP0565807A1 true EP0565807A1 (de) 1993-10-20

Family

ID=8212091

Family Applications (1)

Application Number Title Priority Date Filing Date
EP92830189A Ceased EP0565807A1 (de) 1992-04-17 1992-04-17 MOS-Leistungstransistorbauelement

Country Status (3)

Country Link
US (1) US5396119A (de)
EP (1) EP0565807A1 (de)
JP (1) JP3131525B2 (de)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2717323A1 (fr) * 1993-09-14 1995-09-15 Int Rectifier Corp MOSFET de puissance avec protection de sur-intensité et de surchauffe.
FR2725306A1 (fr) * 1994-08-30 1996-04-05 Int Rectifier Corp Mosfet de puissance ayant un circuit de commande et de protection contre les surintensites de courant et les surtemperatures decouple du corps de diode
WO1999060628A1 (de) * 1998-05-15 1999-11-25 GKR Gesellschaft für Fahrzeugklimaregelung mbH Power-mos-transistor mit temperaturschutzschaltung
US6806772B2 (en) 2002-11-06 2004-10-19 Itt Manufacturing Enterprises, Inc. Power transistor array temperature control system
CN110350484A (zh) * 2019-06-25 2019-10-18 徐州中矿大传动与自动化有限公司 一种igbt短路故障快速保护方法及电路

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4471226B2 (ja) * 2007-07-23 2010-06-02 統寶光電股▲ふん▼有限公司 半導体集積回路
CN105758898B (zh) * 2016-04-15 2019-02-26 中国科学院过程工程研究所 一种高灵敏自反馈型气敏传感器报警电路

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0282734A1 (de) * 1987-02-13 1988-09-21 Kabushiki Kaisha Toshiba Integrierter und kontrollierter Leistungs-MOSFET
DE3821460A1 (de) * 1987-09-28 1989-04-13 Mitsubishi Electric Corp Leistungs-halbleiterelement und verfahren zu dessen herstellung
EP0384900A2 (de) * 1989-02-22 1990-08-29 STMicroelectronics S.r.l. Überhitzungsschutz-Auslöseschaltung mit schmalem Veränderungsbereich des Schwellenwerts

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3018501A1 (de) * 1980-05-14 1981-11-19 Siemens AG, 1000 Berlin und 8000 München Schalter mit einem als source-folger betriebenen mis-pet
JPH0783252B2 (ja) * 1982-07-12 1995-09-06 株式会社日立製作所 半導体集積回路装置
JPS63181376A (ja) * 1987-01-23 1988-07-26 Toshiba Corp 半導体装置
US4940906A (en) * 1988-08-08 1990-07-10 Zdzislaw Gulczynski Power switch driver
US4901127A (en) * 1988-10-07 1990-02-13 General Electric Company Circuit including a combined insulated gate bipolar transistor/MOSFET

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0282734A1 (de) * 1987-02-13 1988-09-21 Kabushiki Kaisha Toshiba Integrierter und kontrollierter Leistungs-MOSFET
DE3821460A1 (de) * 1987-09-28 1989-04-13 Mitsubishi Electric Corp Leistungs-halbleiterelement und verfahren zu dessen herstellung
EP0384900A2 (de) * 1989-02-22 1990-08-29 STMicroelectronics S.r.l. Überhitzungsschutz-Auslöseschaltung mit schmalem Veränderungsbereich des Schwellenwerts

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 9, no. 99 (E-311)(1822) 27 April 1985 & JP-A-59 224 172 ( HITACHI SEISAKUSHO ) 17 December 1984 *

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2717323A1 (fr) * 1993-09-14 1995-09-15 Int Rectifier Corp MOSFET de puissance avec protection de sur-intensité et de surchauffe.
FR2725306A1 (fr) * 1994-08-30 1996-04-05 Int Rectifier Corp Mosfet de puissance ayant un circuit de commande et de protection contre les surintensites de courant et les surtemperatures decouple du corps de diode
WO1999060628A1 (de) * 1998-05-15 1999-11-25 GKR Gesellschaft für Fahrzeugklimaregelung mbH Power-mos-transistor mit temperaturschutzschaltung
US6671152B1 (en) 1998-05-15 2003-12-30 Gkr Gesellschaft Fur Fahrzeugklimaregelung Mbh Power MOS transistor with overtemperature protection circuit
US6806772B2 (en) 2002-11-06 2004-10-19 Itt Manufacturing Enterprises, Inc. Power transistor array temperature control system
CN110350484A (zh) * 2019-06-25 2019-10-18 徐州中矿大传动与自动化有限公司 一种igbt短路故障快速保护方法及电路

Also Published As

Publication number Publication date
US5396119A (en) 1995-03-07
JPH0669513A (ja) 1994-03-11
JP3131525B2 (ja) 2001-02-05

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