EP0554259A1 - Procede et circuit generateur de signaux logiques de sortie a partir de signaux logiques d'entree selon des enchainements logiques de signaux - Google Patents

Procede et circuit generateur de signaux logiques de sortie a partir de signaux logiques d'entree selon des enchainements logiques de signaux

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Publication number
EP0554259A1
EP0554259A1 EP19910914123 EP91914123A EP0554259A1 EP 0554259 A1 EP0554259 A1 EP 0554259A1 EP 19910914123 EP19910914123 EP 19910914123 EP 91914123 A EP91914123 A EP 91914123A EP 0554259 A1 EP0554259 A1 EP 0554259A1
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EP
European Patent Office
Prior art keywords
signal
signals
transfer
generated
reconstruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Application number
EP19910914123
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German (de)
English (en)
Inventor
Dieter Prof. SCHÜTT
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
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Siemens AG
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Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of EP0554259A1 publication Critical patent/EP0554259A1/fr
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1737—Controllable logic circuits using multiplexers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/02—Digital function generators
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled

Definitions

  • the invention relates to a method and a circuit for carrying out the method for generating logic
  • a logical signal combination of logical signals is known. It is known that logical signal combinations can be represented with the aid of logical signals, so-called Boolean signals, whose value set has only a logical ONE and a logical ZERO in many applications. Boolean algebra can be defined in a known manner. It is known that a logical signal combination for all combinations of logical input signal values can be represented in a table form, in a so-called truth table. It is known that two different signal combinations result in the same result if and only if their two defense tables are the same.
  • Signals for a logical ONE and a logical ZERO can be defined in particular in the electronic field, as well as in many other fields, for example optical, pneumatic, mechanical, etc. fields. These defined logic signals can be used as input signals for a large number of definable logic signal combinations.
  • the following forms of representation are known.
  • a logical signal according to a logical variable can be represented.
  • Logical signals and logical variables are to be designated as such by using lower case letters.
  • a logical signal combination of one or more logical signals can be designated according to a logical function of logical variables.
  • Logical functions are to be designated as such by using capital letters and a list of their variables given in brackets.
  • the logic signal generated according to a logic signal combination can be represented as a single logic signal.
  • a single logical signal can be generated by a logical signal combination.
  • a notation is used to designate logical signal combinations.
  • a omitted point immediately between two logical variables denotes an AND operation of these two variables.
  • a plus sign immediately between two logical variables denotes an OR operation.
  • a slash above a logical variable indicates its inversion or negation.
  • a logical variable can also be specified as a parenthesis expression, which contains a logical combination of logical variables.
  • a plus sign within a circle denotes one
  • EXCLUSIVE-OR operation An equal sign denotes an identical truth table for the respective expressions on the left and right thereof.
  • "1" denotes a truth table consisting of logical ONE throughout.
  • "0" denotes a truth table consisting consistently of logical ZERO.
  • additional logic signals can be generated in order to be able to recognize errors in the storage or transmission of several individual logic signals.
  • Parity bits are generated, for example, by an EXOR combination of several individual signals to be checked. With the aid of Hamming coding, errors can be recognized and also corrected from a plurality of such parity bits by using a parity bit additionally generated by them
  • Syndrome word is generated, which is used for error correction.
  • the object of the invention is to provide a further method and a circuit for carrying out this method for generating logical signals from logical input signals, so that a logical output signal can be generated by means of these signals, which is a logical
  • the invention is based on the knowledge that a tuple of logical transfer signals can be generated from the logical input signals as a form of representation of a
  • Transfer signals can be generated, for example, by means of a selection from logical intermediate signals prepared for this purpose. Transfer signal tuples can be linked to form additional transfer signal tuples. In addition, circuit components can be used for error detection as well as for error correction.
  • a tuple of transfer signals can be linked to reconstruction signals
  • Transfer signals can be defined as an algebra logical connections corresponding to the logical connections already explained. It can be shown that this can be achieved by using transfer signals which can be generated for a respectively assigned reconstruction signal,
  • the designation input signal, transfer signal, output signal refers to a circuit for generating a logic signal combination. For the time being, it does not seem sensible that to generate a single output signal from a number of input signals according to a logical signal combination, first several signals in the form of a tuple of transfer signals
  • a logical demonstration signal should be considered to explain the notation used. This is to be generated by a logical signal combination from two logical input signals.
  • the demonstration signal generated is to be represented as a logical variable d.
  • the two input signals should be represented as logical variables x 1 and x 2 .
  • D D (x 2 , x 1 ).
  • Obtained demonstration signal value of the demonstration signal as an output signal.
  • Brackets can be summarized, marked as such by a subscript "d". Within the bracketed expressions marked by the subscript "d”, there are always definitions, multiplications, Potentiations, etc. to be carried out according to the known
  • Easier generation can be derived from this.
  • the logical input signal values are given for x 1 and x 2 for determining the respective number of the number tuple according to Table 1 as a truth table.
  • a form of representation equivalent to the respective number tuple as a binary number is listed below one another in Table 2.
  • an equivalent representation as a decimal number is listed next to each other in Table 2.
  • Table 2 is a symbolic representation of the given logical signal combination.
  • table 2 shows an associated name for the respective demonstration signal. So in Table 2 they are
  • Demonstration signal d D (x K , ... x 1 ); For the output signal values of the demonstration signal is by indexing
  • Signal linkage by definition, can be represented as the following number tuple (d T , d T-1 , d T-2 , ... d 3 , d 2 , d 1 ); Based on this
  • the assigned logical signal combination can be represented as the following binary number
  • Each demonstration signal d (m) can therefore be optionally represented by definition - either as a number tuple (d T (m) , d T-1 , ..., d 1 (m) ), or as a binary number (d T (m) . .. d 1 (m) ) b ,
  • Demonstration signals d (m) shown for K 2.
  • these logical signals can be linked and represented in further logical combinations.
  • the input signal x 1 can always be represented by the demonstration signal d (3) , and that
  • Input signal x 2 can always also be represented by the demonstration signal d (5) , as can be seen from Table 2.
  • the number tuples can also be used as logical vectors, for example
  • Number tuples for example, as an output signal to one
  • This number is linked to that number of the number tuple at the same position, which corresponds to the same combination of input signal values, to the respective number of the
  • One of the demonstration signals for example d (9) , can be represented by linking other demonstration signals, or by by definition associated number tuple, or by
  • the associated decimal digit as a superscript number also serves to identify the associated truth table. This is not necessarily the case with other logic signals. Generally serves a
  • Reconstruction signals r (n) ; n 1, ... N; 2 N 2 k ;
  • Reconstruction signals of this type are easier to find and check, particularly in their form of representation as a number tuple.
  • the reconstruction signal, the transfer signals are to be determined as follows:
  • Output signal a is not yet a logical to be specified
  • Output signal a is intended as a logical signal combination
  • a (x 2 , x 1 ) of the input signals x 1 and x 2 are specified, for example on the basis of a truth table to be specified, which can be specified as table 4 as follows.
  • Table 4
  • the transfer signals can be represented as follows:
  • BOOT algebra As an abbreviation for "boolean tuple algebra”.
  • boost tuple algebra According to the number N of transfer signals, it is referred to as a BOOT N algebra. This will be explained in more detail below.
  • logical signal combinations of input signals can be defined by definition. Any logical
  • a so-called BOOT N is to be a tuple of a number N of logical functions, which are to be used in each case to generate the transfer signals.
  • transfer signals are to be generated which, for example, can be represented in the form of a number tuple or as a binary number or as a decimal number.
  • a tuple is used which contains the output signal which can be generated therefrom and the signal combination of the input signals associated with this output signal
  • each of these transfer signals is assigned, consisting of a number of logical transfer signals which are generated in such a way that each of these transfer signals has an OR combination of an AND combination of the output signal with a reconstruction signal assigned to the transfer signal and an AND combination of an OEM transfer signal each assigned arbitrary signal with a respective scatter signal assigned to the transfer signal, and that each AND operation of each of the reconstruction signals with another of the reconstruction signals is always logically ZERO, and that an OCER operation of all
  • Reconstruction signals is always logically ONE, and that each AND operation of each of the reconstruction signals with the respectively assigned scatter signal is always logically ZERO, so that the output signal is based on this tuple
  • Reconstruction signal can be generated.
  • the output signal is to be a combined OR combination of all AND combinations
  • Generation of the output signal can therefore be represented as the BOOT 3 according to (10 d , 5 d , 0 d ) by definition.
  • the following BOOT 3 11 d , 1 d , 8 d ) can be used to define an output signal that can be generated.
  • These two output signals should be linkable as logic signals, for example by an AND link.
  • the transfer signals for the linked output signal a (3) can be specified in accordance with
  • the linked output signal a (3) can be generated from it in accordance with:
  • Every logical signal can therefore be represented, like that one
  • This link is used to define transfer signals. From these transfer signals, a BOOT belonging to the logic signal is put together, from whose transfer signals the logic signal can be generated. To link such logical signals that can be generated from transfer signals, it is therefore sufficient to link the transfer signals according to the BOOTs.
  • a logic switching mechanism can be constructed which uses a BOOT of transfer signals instead of a single logic signal and which links these BOOTs of transfer signals with one another. For example, for only one output, the logical signal to be output is to be reconstructed and generated from the respective BOOT of transfer signals.
  • Transfer signal is correctable.
  • the regulation according to the invention for generating the transfer signals results in special linking rules by means of which the test circuits and the test signals can be used.
  • Error detection, error correction and general safety aspects can be included a priori in circuit designs.
  • applications for encrypting signals can also be achieved and checked as a result.
  • Reconstruction signals always result in a logical ONE, and that each AND operation of one of the further reconstruction signals with the reconstruction signal associated with the transfer signal does not result in a logical ZERO for all combinations of input signal values, so that the output signal
  • Y (2) (x 2 , x 1 ) A (x 2 , x 1 ) .R (2) (x 2 , x 1 ) + B (2) (x 2 , x 1 ) .S (2) ( x 2 , x 1 );
  • any logical function A (x 2 , x 1 ) can be represented
  • a (x 2 , x 1 ) Y (1) (x 2 , x 1 ) .R (1) (x 2 , x 1 ) +
  • any logical function can be determined and determined by a tuple of logical functions. This is used when defining transfer signals, from which an output signal can always be generated. It is now to be shown how such a tuple can be expanded, for example by one of the logical ones
  • tuple Functions of the tuple can be replaced by a tuple of other logical functions. It is also intended to show how a tuple can be reduced, for example by replacing some of the logical functions of the tuple with a single logical function. This will first be explained using transfer signals. For example for the BOOT already considered
  • y (3) (a 4 , 0,0,0);
  • the tuple of the transfer signals can also be represented, as already explained, as a tuple of logical number tuples:
  • the transfer signal y (1) is considered , it should be explained in more detail how further transfer signals can be generated for this transfer signal by using this transfer signal y (1) as an intermediate that can be generated
  • Output signal is to be considered, and as such is assigned to the other transfer signals.
  • the identifier is expanded by a comma and an additional additional identifier, for example in the form of a numbering, within the identifying superscript bracket.
  • two further reconstruction signals r (1,1) and r (1,2) should be specified for a considered transfer signal y (1) and its associated reconstruction regional r (1) .
  • a paired AND link should always be logically zero
  • a further scatter signal s (l, j) ; j 1.2; be specified, the AND operation of which is always logically ZERO with the associated further reconstruction signal
  • a further transfer signal can be defined for each further reconstruction signal such as fclct:
  • y (1,1) y (1) .r (1,1) + b (1,1) .s (1,1) ;
  • y (1,2) y (1) .r (1,2) + b (1,2) .s (1,2) ;
  • r (1,2) y (1) .r (1,2) + b (1,2) .s (1,2) ;
  • y (1) y (1,1) .r (1,1) .r (1) + y (1,2) .r (1,2) .r (1) ;
  • Output signal can be generated according to
  • Output signal can be generated according to
  • Table 2 can be used.
  • the new transfer signals y (1,1) and y (1,2 ) are to be generated from the replaced transfer signal y (1) as follows:
  • a tuple of four transfer signals can be generated from the tuple of the three transfer signals:
  • the BOOT 4 can be replaced by the BOOT 3 .
  • a few special cases will be considered below. For example, for a BOOT N , the transfer signals of which are the same as the respectively associated reconstruction signals, the logical signal represented thereby is always logical
  • the logic signal shown is always logic ZERO for a BOOT N , the transfer signals of which are each the same as the respectively assigned scatter signals, so that such a BOOT can be used as an O element.
  • Reconstruction signals with a BOOT N likewise consist of all reconstruction signals, but the respective order of the reconstruction signals in each of the BOOTs is a non-identical permutation.
  • p1, p2, ..., pn, ..., pN permutation of 1,2, ..., n, ..., N;
  • Verification of the reconstruction signals can be used.
  • r (T) x 1 x2 ... x K -1 x K ;
  • r (1) x 1 x 2 ... x K-1 x K ;
  • a BOOT can again be provided as an element of this BOOT as a form of representation for this element, the reconstruction signals of which can also be specified differently in terms of number and definition. For example, as already explained, a transfer signal y (1) from a BOOT 3 by two further transfer signals y (1,1) and y (1,1) as a BOOT 2 according to
  • a logical signal can be represented by this BOOT 3 , in which an element is represented as a BOOT 2 .
  • the four transfer signals y (1,1) , y (1 ' 2) , y (2) , y (3) of this BOOT 3 containing a BOOT 2 are in the process of generating this shown signals assigned the respective reconstruction signals as follows.
  • the reconstruction signals r (1,1) , r (1,2) are assigned for the BOOT 2 , so that the following applies:
  • a neutral BOOT in particular can be defined on the one hand as a neutral 1 element for AND operations of BOOTs and on the other hand as a neutral O element for
  • a further preferred embodiment of the invention is characterized in that a transfer signal can be generated, correspondingly continued further tuples of generated further transfer signals and further reconstruction signals. If, for example, with a larger number K of
  • BOOT N1 can be expanded to a BOOT N2 , whereby N1 applies / - N2 / A
  • Reconstruction signals for the respective BOOT must always be defined in such a way that their pairs AND operation is always logical ZERO, on the one hand, and
  • BOOTs can therefore only be expanded to a limited extent. While any transfer signal of a considered BCOT can be represented at any time by further transfer signals of, for example, another BOOT, an executable extension of the BOOT by means of the further transfer signals depends on whether the reconstruction signals associated with the further transfer signals with the reconstruction signals of the considered BOOT fulfill the stated relations that their AND combination in pairs is always logically ZERO and an OR combination of all is always logically ONE.
  • the superscript and bracketed identifier should be supplemented by a comma and an additional identifier attached to it, for example in the form of a numbering for the other transfer signals.
  • r (n1) .r (n2) 0; 1 L n1 n2 LN;
  • y (n) are represented by further transfer signals, by means of which the following further BOOT J can be formed to represent y (n) :
  • r (n, j1) .r (n, j2) 0; 1 L j1 j2 J;
  • y (n) y (n, J) r (n, J) + ... + y (n, j) r (n, j) + ... + y (n, 1) .r (n, 1) ;
  • a specific transfer signal for example y (n, j)
  • a specific transfer signal can be represented by further transfer signals, by means of which a further BOOT can be formed, etc.
  • the following primary BOOT (y (N) , ..., y (n) , ... y (1) ) is used to represent the output signal a ;
  • the transfer signal y (n) can be represented as follows:
  • a further preferred embodiment of the invention is characterized in that each of the transfer signals of a primary tuple can be generated, corresponding to a respective further tuple of generated further transfer signals and further reconstruction signals.
  • each primary transfer signal y (n) can be made up of a number N of transfer signals from a primary BOOT by an equal number J of others
  • y (n, j) y (n) .r (n, j) + b (n, j) .s (n, j) ;
  • y (n) y (n, J) .r (n, J) + ... + y (n, 1) .r (n, 1) ;
  • n 1, ... N; so that a total of N times 3 of further transfer signals y (n, j) instead of all previous transfer signals y (i) of the number N is to be generated after this change of representation.
  • the other reconstruction signals for displaying one of the previous transfer signals can also be used unchanged for displaying the other previous transfer signals, so that the following applies:
  • Order another BOOT of further transfer signals of a second order are formed by a change of representation.
  • a further change in the form of representation can be used to form a further BOOT of further transfer signals of a third order in the manner explained. And so on.
  • y (j (1), j (2)) y (j (1)) r (j (1), j (2)) + b (j (1), j (2)) s (j (1), j (2)) ;
  • the number of transfer signals of this BOOT is therefore equal to J (1) times J (2) times ... times J (i) .
  • Another preferred embodiment of the invention is characterized by paired inverted reconstruction signals. Such reconstruction signals can be generated more easily. In addition, there is an advantageous clarity of the concept.
  • a further preferred embodiment of the invention is characterized by inverted scatter signals assigned to the reconstruction signals. For example, the scatter signals can be generated more easily in this way. Further advantages result in particular in the case of suitably predetermined arbitrary signals. This will be explained in the following. For a BOOT 2 , for example, both arbitrary signals are always specified according to logical ONE.
  • y (1) . y (2) (ar + ).
  • OR operation can always be checked according to ONE, for example for error detection:
  • AND operation can always be checked according to ZERO, for example for error detection.
  • a further preferred embodiment of the invention is characterized by at least one arbitrary signal, which is the logical combination of the output signal to be assigned, but from at least one inverted input signal
  • this reconstruction signal can only be one of the following four logical signals:
  • Another preferred embodiment of the invention is characterized in that one of the reconstruction signals is equal to one of the input signals.
  • y (1) ax 1 + b (1) . 1 ;
  • y (2) a. 1 + b (2) .x 1 ;
  • y (1) (a 4 , a 3 , a 2 , a 1 ) .3 d + .12 d ;
  • y (1) and y (2) are to be selected for the generation of the output signal.
  • This can be done, for example, by means of a selection switching mechanism.
  • PLA's programmable logic switchgear
  • this can result in simplifications for the architecture and the above-mentioned concept.
  • not all different output signals need to be generated as intermediate signals.
  • it is sufficient to generate those four intermediate signals and use them to select the respective transfer signals for the BOOT.
  • the output signal can be generated from these selected transfer signals by means of the reconstruction signals. It can be specified which two
  • Intermediate signals are to be selected as transfer signals for a given logical combination (a 4 , a 3 , a 2 , a 1 ) in order to generate the output signal.
  • the transfer signal y (1) is to be selected as follows
  • the transfer signal y (2) is to be selected as follows
  • These two transfer signals can also be selected as a BOOT of logical signals (y (1) , y (1) )
  • one of four processed intermediate signals can be generated by means of a selection circuit, which is activated depending on m, for example
  • the transfer signals can be one of four
  • the transfer signals can be one of four
  • the transfer signals can be one of four
  • the scatter signals can be predefined in accordance with the respectively assigned inverted reconstruction signals.
  • the arbitrary signals can in each case according to the respectively assigned signal link to form the
  • respective intermediate output signals can be predetermined from, for example, all inverted input signals.
  • y (1) ax 1 + A ( K , ..., x 1 ). 1 ;
  • logical links to be specified can be represented.
  • the logical values of the output signal can be combined depending on the input signals x 1 to x K on the one hand into a tuple, which is shown in Table 6, and
  • the reconstruction signals as well as their logical combination, which in the case under consideration is equal to one of the Input signals or an inverted input signal can be represented as a decimal number.
  • T21 T2 + T11
  • T22 T2 + T12
  • y (1,1)
  • Peculiarities in other applications can be achieved, for example, in that a different sequence can be provided for each of which is used as a reconstruction signal
  • the signal linkage assigned as an intermediate output signal can be used, for example, to form the arbitrary signals, but not all of them inverted
  • Input signals but only be provided from a few inversions of the input signals, so that also
  • an interchange in a sequence of input signals as variables for function formation within the list of variables can also be provided.
  • the variables instead of at least one, for example the variables have a fixed logic value, for example logic 0 or logic 1. Likewise can
  • a logical function of at least one of the variables can also be provided instead of at least one of the variables.
  • Function formation from several input signals is also possible to form the reconstruction signals.
  • the transfer signals can additionally facilitate and support the achievement of symmetrical peculiarities for the truth tables. A large variety can thus be achieved for symmetrical peculiarities of transfer signals. The advantages that can be derived from this will be explained in more detail on the basis of the case considered above.
  • the transfer signals can be represented using these smaller number tuples, which are to be named using Roman numerals.
  • a further simplification of the representation of the number tuples is obtained with a BOOT, the definition of which can preferably be found on the basis of the output signal.
  • Zi can be defined as a Roman number, which can be obtained explicitly in the following way
  • RRR * (((y RZI ) d (16) I-1 ) d + ... + ((y RZi ) d (16) i-1 ) d + ... ... + ((y R22 ) d (16) 1 ) d + ((y RZ1 ) d (16) 0) d) d ;
  • y SZi Y SZi (x K , x K-1 ) from (0d, 6d, 9d, 15d);
  • Another preferred embodiment of the invention is characterized in that one of the reconstruction signals is equal to an EXOR combination of at least two input signals. This results, for example, in the case of a specific selection of arbitrary signals and scatter signals
  • y (1) a. (x 1 ⁇ x 2 ) + b (1) . (x 1 ⁇ 2 );
  • y (1) (a 3 , a 3 , a 2 , a 2 );
  • y (2) (a 4 , a 4 , a 1 , a 1 );
  • each transfer signal can only take up a limited number of number tuples.
  • the output signal is generated in accordance with
  • Select output signals y (1) and y (2) can be done for example by means of a selection circuit. This can be used, for example, for programmable logic
  • the transfer signals y (1) and y (2) are to be selected as follows
  • BOOT of a higher order can be defined, for example. ;
  • the BOOT can be redefined, for example for locating, converting, modifying or as a starting point for extensions.
  • novel circuits, circuit architectures, circuit concepts, etc. can be found and checked. Logical combinations of, in particular, many input signals are thereby significantly facilitated.
  • a further preferred embodiment of the invention is characterized in that the transfer signals are generated at one location and are transferred to another location where the output signal is generated from the transfer signals. Reconstruction signals may be required to generate the output signal. In some use cases this can
  • Output signal can also be generated without a reconstruction signal and solely by linking transfer signals. Instead of reconstruction signals that have already been generated, those input signals that are required to generate these reconstruction signals can also be transmitted. Depending on the application, the reconstruction signals or some of the input signals or only some of the reconstruction signals and some of the input signals can therefore be provided during the transmission in addition to the required transfer signals. For example, in the case of encryption or similar applications, it may be necessary, for example from confidentiality requirements, input signals and
  • This BOOT generation can be agreed, for example, by means of a so-called second information channel.
  • a generator can generate a number of
  • Input signal values must be agreed so that their change can be determined in accordance with the agreement.
  • Logical links for the formation of reconstruction signals should be agreed with this generator for input signals, so that these can be determined in particular during the decoding.
  • scatter signals assigned to these reconstruction signals are to be generated, so that the reconstruction signals and the scatter signals always fulfill the relations according to the invention.
  • arbitrary signals can be generated, for example, from the input signals.
  • the reconstruction signals are to be generated during the decoding.
  • the decoding signals are to be generated during the decoding.
  • Agreed generator generate input signal values from which these reconstruction signals can be formed according to agreed, for example, changing logic operations. These can be used to decode the BOOT transferred as follows:
  • Decoding does not need to be known either the scatter signals used in the coding or the arbitrary signals used. Only the respectively agreed reconstruction signals or their agreed generation are necessary for the successful decoding. Effective encryption can be achieved, particularly in the case of frequently changing scatter signals and random signals.
  • a further preferred embodiment of the invention is characterized in that the transfer signals are stored at one point in time and in that the output signal is generated from read out transfer signals at another point in time. As with the aforementioned transmission of transfer signals, the confidentiality requirements can also decisively determine the respective application of the invention when storing transfer signals. The modifications mentioned also apply to the storage of
  • Transfer signals Another preferred embodiment of the invention is characterized in that a transfer signal is selected from such a range of a number of processed intermediate signals so that an AND operation of the
  • the link is generated instead of the individual output signals from those transfer signals which are in turn provided at the same position in the tuple.
  • a switching mechanism can be constructed in which individual signals can be generated in the form of tuples from transfer signals and linked as tuples.
  • a further preferred embodiment of the invention is characterized in that a circuit block is provided, to which at least one of a number of the input signals is supplied, and from which a tuple which is assigned to the output signal which can be generated therefrom and to the signal combination of the input signals which is associated with this output signal, generated from a number of transfer signals, which are generated so that each of these transfer signals each an OR operation of one hand
  • an AND operation of an arbitrary signal assigned to the transfer signal corresponds to a scatter signal assigned to the transfer signal, and that each AND operation of one of the reconstruction signals with another of the reconstruction signals is always logically ZERO, and that an OR operation of all Reconstruction signals is always logically ONE, that each AND operation of one of the reconstruction signals with each
  • Such a circuit block can be used modularly.
  • a further preferred embodiment of the invention is characterized in that at least one circuit component is provided in the circuit block for processing at least one offer of a number of intermediate signals for which an AND operation of one of these intermediate signals with one of the reconstruction signals is the same as an AND operation of this reconstruction signal with the output signal.
  • Such a circuit component can be used in a modular manner in circuit blocks for generating a plurality of tuples of transfer signals.
  • Signal value is inverted to the second intermediate signal, a fourth intermediate signal, the signal value to the first
  • Circuit component can be used advantageously, for example, as already explained with reference to Table 7.
  • Intermediate signals processed namely a first intermediate signal; whose signal value is always logically ZERO, a second intermediate signal whose signal value is equal to an EXOR combination of two of the input signals, a third intermediate signal whose signal value is inverted to the second intermediate signal, a fourth intermediate signal whose signal value is the first
  • a further preferred embodiment of the invention is characterized in that the circuit component processes sixteen intermediate signals, specifically a first intermediate signal, the signal value of which is equal to an AND operation of one of the input signals and an EXOR operation of two further of the input signals, a second intermediate signal, whose signal value is equal to an AND operation of one of the input signals with an inverted EXOR combination of the two further of the input signals, a third intermediate signal, the signal value of which is equal to an OR combination of the first and second intermediate signals, a fourth
  • EXOR operation of the two further of the input signals is a fifth intermediate signal, the signal value of which is equal to an OR operation of the third and second intermediate signals, a sixth intermediate signal, the signal value of which is equal to an OR operation of the fourth and second intermediate signals seventh intermediate signal, whose signal value is equal to an OR operation of the fourth and third intermediate signals, an eighth intermediate signal, whose signal value is equal to the inverted seventh intermediate signal, a ninth intermediate signal, whose signal value is equal to the inverted sixth intermediate signal, a tenth intermediate signal, whose signal value is equal to the inverted fifth intermediate signal, an eleventh intermediate signal whose signal value is equal to the inverted fourth intermediate signal, a twelfth
  • Intermediate signals may require a smaller number of tuple transfer signals. This is useful, for example, for BOOTs of higher orders.
  • a further preferred embodiment of the invention is characterized in that at least one circuit part is provided in the circuit block for generating at least one of the transfer signals by means of a selection of one of the Intermediate signals of the processed offer.
  • a circuit part can be programmable, for example
  • the programmable hard-wired circuit connections can be modified in a simple manner. This can also be provided with optical means, for example. For example, a
  • Variably predeterminable logic signal links can be provided in this way.
  • Logical signal combination by means of which the output signal can be generated from the input signals, is input in the form of a combination signal, which is composed of a number of logical signals, the signal value of which, as binary digits, corresponds to a truth table for the output signal.
  • a link signal which can be input in this form in accordance with a variably predeterminable signal link can preferably be used for control signals from multiplexer elements.
  • Has multiplexer elements which are each the four
  • Intermediate signals of the circuit component are supplied as multiplexer input signals, and to which two of four binary digits of the link signal are input as control signals, with a most significant of these binary digits as a higher-order control signal and a least significant one of these binary digits as a low-order control signal for one of the multiplexer elements, and with a more significant one the remaining two of these binary digits as a higher-order control signal and a lower-order of these two remaining of these binary digits as a lower-order control signal for the other of the multiplexer elements.
  • Has multiplexer elements which are each the four
  • Intermediate signals of the circuit component are supplied as multiplexer input signals, and to which two of four binary digits of the combination signal are input as control signals, with a most significant of these binary digits as a higher-order control signal and a most significant of the remaining three of these binary digits as a low-order one
  • Control signal for one of the multiplexer elements and with a higher-order of the two remaining of these binary digits as a lower-order control signal and a lower-order of these two remaining of these binary digits as a higher-order control signal for the other of the multiplexer elements.
  • Such a circuit part can be used advantageously, for example, as already explained with reference to Table 5.
  • Circuit block is for example for generating
  • Transfer signals for BOOTs of higher orders can be used.
  • Circuit components each of which generates four intermediate signals, and has a circuit part which has two multiplexer elements, with the four intermediate signals which are generated by one of the circuit components and which are supplied to the one of the multiplexer elements as multiplexer input signals, and with the four intermediate signals which are generated by the other of the circuit components and which are fed to the other of the multiplexer elements as multiplexer input signals, and with a higher-order control signal for one of the multiplexer elements as a most significant binary digit of four binary digits of the combination signal supplied to the circuit part and with a higher-order control signal for the other of the multiplexer elements than a least significant binary digit of the four supplied binary digits of the combination signal, and with a low-order control signal for one of the multiplexer elements as a lower-order binary digit of the two remaining binary digits of the link signal, and with a low-order control signal for the other of the multiplexer elements as a higher-order binary digit from these two remaining binary digits of the link signal.
  • a further preferred embodiment of the invention is characterized in that the circuit block has at least one logic element which has a first, a second, a third AND logic element and an OR logic element, with one of the input signals which is the first AND logic element at a non-inverting input, and the second AND gate at one
  • AND gate is fed to a non-inverting input, and with another of the control signals, which the first AND gate at a non-inverting input, the second AND gate at an inverting input, and the third AND gate at a non Is fed inverting input, as well as with one of the transfer signals, which is generated by the OR logic element from the signals supplied to it, which are generated by the three AND logic elements.
  • circuit block has at least one logic element, which has a first, a second, a third, a fourth, a fifth AND logic element and an OR logic element, with one of the input signals, which the first AND gate at a non-inverting input, the second AND gate at an inverting input, the third
  • AND gate is fed to a non-inverting input, and the fourth AND gate is fed to an inverting input, and with a further one of the
  • AND gate is fed to a non-inverting input, as well as with another of the control signals, which the first AND gate is not at one
  • circuit block is advantageous, for example, with regard to a runtime for forming the transfer signals.
  • circuit block has at least one circuit part to which two of the input signals and four of the control signals are fed.
  • a further preferred embodiment of the invention is characterized in that the circuit part has a first and a second logic element, with a higher-order control signal for the second logic element equal to a least significant of the four control signals supplied to the circuit part and with a lower-order one
  • Control signal for the second logic element is equal to a next higher value of the four control signals supplied to the circuit part and with a lower quality control signal for the first logic element is equal to a next higher quality of the four control signals supplied to the circuit part
  • Control signals and with a higher-order control signal for the first logic element equal to a most significant of the four control signals supplied to the circuit part are, for example, inexpensive
  • Test signals can be generated from the generated transfer signals, from which the output signal to be generated can also be generated, so that it can be checked.
  • Another preferred embodiment of the invention is characterized in that the generated transfer signals are checked in a test circuit. It can from the
  • a further preferred embodiment of the invention is characterized in that the transfer signals can be corrected in accordance with test signals which are generated by a circuit component. Test signals can be generated, by means of which an incorrectly generated transfer signal can be corrected, so that such errors can be coped with.
  • FIG. 1 shows a first circuit for generating a logical output signal from two logical input signals in accordance with a variably assignable logical link.
  • FIG. 2 shows a multiplexer element which is used in the circuits in FIGS. 1, 3, 14, 20, 21, 26, 27.
  • FIG. 3 shows a second circuit for generating a logical output signal from two logical input signals in accordance with a logical combination which can be predetermined.
  • FIG. 4 shows a third circuit for generating a logical output signals from a number of logical input signals according to a variably predeterminable logical link.
  • FIG. 5 shows a fourth circuit for generating a logical output signal from a number of logical input signals in accordance with a variably predeterminable logical combination.
  • FIG. 6 shows a fifth circuit for generating a logical output signal from a number of logical input signals in accordance with a variably predeterminable logical combination.
  • FIG. 7 shows a sixth circuit for generating a logical output signal from a number of logical input signals in accordance with a variably predeterminable logical combination.
  • FIG. 8 shows a seventh circuit for generating a logical output signal from three logical input signals in accordance with a variably predeterminable logical one
  • FIG. 9 shows an embodiment for a circuit component which is used in the circuit of FIG. 8.
  • FIG. 10 shows a further embodiment for the same circuit component from FIG. 8.
  • FIG. 11 shows a multiplexer element which is used in the circuit of FIG. 8.
  • FIG. 12 shows an eighth circuit for generating a logical output signal from two logical input signals in accordance with a programmable, hard-wired logic combination.
  • FIG. 13 shows a ninth circuit for generating a logical output signal from two logical input signals according to a programmable, hard-wired logic link.
  • FIG. 14 shows a tenth circuit for generating two output signals from three input signals in accordance with a programmable, hard-wired logic
  • FIG. 15 shows an eleventh circuit for generation
  • FIG. 16 shows a twelfth circuit for generating a logical output signal according to three variably predeterminable signal combinations.
  • FIG. 17 shows a thirteenth circuit for generating a logical output signal according to three variably predeterminable signal combinations.
  • FIG. 18 shows a fourteenth circuit for generating logical transfer signals in accordance with a variably predeterminable signal combination from input transfer signals.
  • FIG. 19 shows a fifteenth circuit for generating logical transfer signals in accordance with three signal links which can be predetermined.
  • FIG. 20 shows a test circuit for checking the transfer signals of FIG. 19.
  • FIG. 21 shows a sixteenth formwork for generating correctable transfer signals according to a variable signal link.
  • FIG. 22 shows a circuit component for correction the transfer signals of Figure 21.
  • FIG. 23 shows a circuit component for generating test signals from FIG. 21.
  • FIG. 24 shows a circuit component for generating test signals for use in connection with the
  • FIG. 25 shows a circuit component for generating test signals for use in connection with the
  • FIG. 26 shows a seventeenth circuit for generating correctable transfer signals in accordance with programmable, hard-wired, logic operations.
  • FIG. 27 shows an eighteenth circuit for generating a logical output signal from two input signals in accordance with a variably predeterminable signal combination.
  • FIG. 28 shows a further embodiment for a circuit block from FIG. 1.
  • FIG. 29 shows a further embodiment for a circuit block which is used in FIGS. 3, 16, 17, 18, 19.
  • FIG. 30 shows a further embodiment for one
  • FIG. 31 shows a test element for the circuit of FIG. 18,
  • FIG. 1 shows, two logic input signals x 1 and x 2 are provided in a first circuit.
  • a logical output signal a (m) is generated in accordance with a variably predeterminable logical combination.
  • the respective one is variable
  • the logical link to be specified is in accordance with the previously
  • Table 2 explained as a logic signal m entered according to a binary number, the binary digits according to 2, 2, 2, 2 can be entered as binary signals, so that they are binary
  • Signals form a link signal m.
  • the input signals x 1 and x 2 are input to a circuit block BA2, from which a BOOT 2 is generated by overcab signals y (1) and y (2) .
  • a circuit element RSA is provided for generating a reconstruction signal r from the two input signals.
  • the circuit element RSA is provided for generating a reconstruction signal r from the two input signals.
  • Reconstruction signal r is generated by supplying the two input signals x 1 and x 2 , from which the reconstruction signal r is generated by EXOR operation by the following
  • the intermediate signal z 1 is generated so that it is always logic ZERO.
  • the intermediate signal z 4 is generated so that it is always logically ONE.
  • the circuit component ZWA is supplied with the input signal x 1 , which is forwarded as the intermediate signal z 2 .
  • the input signal x 1 is inverted by an inverter INV.O. This inverted input signal x 1 , that is 1 , is passed on as the intermediate signal z 3 .
  • Multiplexer elements MUX4.0 and MUX4.1 are provided. Each of the multiplexer elements MUX4 are all four
  • Multiplexer elements MUX4 is a selector switch
  • the transfer signal y (1) is generated and forwarded by the multiplexer element MUX4.0. from
  • Multiplexer element MUX4.1 the transfer signal y (2) is generated and forwarded.
  • the selection switch of the multiplexer element MUX4 is supplied with two logic control signals, which are input as a low-order binary digit and a higher-order binary digit, which are combined as
  • the multiplexer element MUX4.0 is as low value binary number, the binary digit 2 einperade the link signal m, and when the high-order binary digit binary number is input 2 2 of the linkage signal m.
  • the multiplexer element MUX4.1 is entered with the binary digit 2 of the link signal as the low-order binary digit, and the binary digit 2 of the link signal m is entered as the higher-order binary digit.
  • the transfer signals y (1) and y (2) are accordingly generated, as indicated in table 7 already explained.
  • the multiplexer input signals are selected in the multiplex elements MUX4 in such a way that the binary digits supplied in each case, that is to say on the one hand for 2 2 , 2 1 at
  • multiplex element MUX4.0 and, on the other hand, for 2 3 , 2 0 for multiplex element MUX4.1, as a two-digit binary number, how many of the four multiplexer input signals mentioned are to be selected.
  • the first to fourth multiplexer input signals are selected in accordance with the two-digit binary numbers 00 to 11.
  • These selected signals are emitted as a transfer signal y (1) by the multiplexer element MUX4.0 on the one hand and on the other hand as a transfer signal y (2) by the multiplexer element MUX4.1.
  • transfer signals y (1) and y (2) are accordingly selected in accordance with Table 7, specifically as a function of the binary digits supplied in each case, by means of which the signal link m to be assigned is determined in each case.
  • the binary digits agreed by definition for the respective signal combination m to be specified are given in Table 2 previously explained.
  • the reconstruction signal r is generated by an EXOR logic element EXOR as the circuit element RSA by EXOR logic of the two input signals x 1 and x 2 .
  • EXOR an AND logic element AND.1 is provided, to which the input signal x 1 on the one hand and on the other hand that inverted by an inverter INV.1
  • OR gate OR.1 is supplied. As a second signal, this OR logic element OR.1 is supplied with a further signal which is generated by an AND logic element AND.2.
  • the AND logic element AND.2 receives, on the one hand, the input signal x 2 and, on the other hand, the input signal x 1 inverted by a further inverter INV.2 1 , fed to form the AND link. That from
  • the reconstruction signal r and the two transfer signals y (1) and y (2) become one
  • Reconstruction element supplied REK The specified one is
  • An AND logic element AND.4 is provided for linking the reconstruction signal r and the transfer signal y (1) .
  • a further AND logic element AND.3 is provided for linking the transfer signal y (2) and that of one
  • Inverter INV.3 inverted reconstruction signal r that is.
  • the signals generated by the two AND logic elements AND.3 and UND.4 are linked by an OR logic element OP .4 to form the output signal a (m) .
  • the reconstruction element REK forms a multiplexer element
  • MUX2 which selects one of two supplied signals y (1) or y (2) , depending on one supplied as a control signal
  • the table 7 explained above lists which of the intermediate signals is selected as one of multiplexer input signals in accordance with the link m to be specified by the multiplex element MUX4.0 as the transfer signal y (1) , and which is selected by the multiplex element MUX4.1 as that
  • Transfer signal y (2) The generated output signal a (m) can therefore be represented according to the following formula
  • a multiplexer element MUX4 consists of an OR logic element OR.M, which the signals generated by AND logic elements UND.M.0, UND.M.1, UND.M.2 and UND.M.3 be fed.
  • OR.M OR logic element
  • Each of these AND logic elements AND.M is supplied with a multiplexer input signal ze 0 , ze 1 , ze 2 , ze 3 from one of multiplexer inputs on the one hand, and an enable signal, on the other hand
  • AND logic elements UND.Z.0, UND.Z.1, UND.Z.2 and UND.Z.3 are each generated. These are controlled from control inputs by means of two control signals zg 1 and zg 0 . As a binary digit of a two-digit binary number, these control signals are used to control the selection of the one to be released
  • control signal zg 0 being the lower-order binary digit
  • control signal zg 1 being the higher-order binary digit
  • the AND gate AND.Z.0 is supplied with the control signal zg 0 inverted by an inverter INV.M0, and the control signal zg 1 inverted from a further inverter INV.M1 is fed so that the AND gate AND.Z .0 only releases its enable signal zh 0 , which is used in the AND logic element AND.M.0 to enable the first multiplexer input signal ze 0 to be selected if the two binary digits 00 are supplied by means of the control signals zg 1 and zg 0 . Otherwise, that is to say for the binary digits 01, 10, 11, the multiplexer input signal ze 0 is blocked at the AND logic element AND.M.0.
  • Control signal zg 0 is supplied to AND gate AND.Z.1, and control signal zg, inverted by inverter INV.M1, is supplied, so that AND gate AND.Z.1 only releases its enable signal zh 1 . which is used in the AND logic element AND.M.1 to enable the second multiplexer input signal ze to be selected if the two binary digits 01 are supplied by means of the control signals zg 1 and zg 0 . Otherwise, that is to say for the binary digits 00, 10, 11, the multiplexer input signal ze 1 is blocked with the AND logic element AND.M.1.
  • the AND link AND.Z.2 is on the one hand from
  • Control signals zg 1 and zg 0 are routed. Otherwise, that is to say for the binary digits 00, 01, 11, the multiplexer input signal zs 2 is blocked at the AND logic element AND.M.2.
  • the two control signals zg 1 and zg 0 are fed to the AND logic element AND.Z.3, so that the AND logic element AND.Z.3 only releases its release signal zh-, which is used for the AND logic element UND.M.3 Release of the visrten
  • selectable multiplexer input signals ze 3 is used if the binary digits 11 are supplied by means of the control signals zg 1 and zg 0 . Otherwise, that is to say for binary digits 00, 01, 10, the multiplexer input signal ze 3 is blocked at the AND logic element AND.M.3.
  • One of the four multiplexer input signals is output by the OR logic element OR.M as a multiplexer output signal zf jswsils depending on the control signals en zg 1 and zg 0 present in accordance with the following table 8.
  • Table 8
  • FIG. 3 shows, two logic input signals x 1 and x 2 are provided in the second circuit, from which a logic output signal a is generated in accordance with a variably inputable logic operation.
  • the respective logical link is entered in accordance with the table 2 explained above as a link signal m according to a binary number, the binary digits of which can be entered as binary control signals according to 2 3 , 2 2 , 2 1 , 2 0 , so that these binary signals form the link signal m.
  • the input signals x 1 and x 2 are input to a circuit block BB2, from which a BOOT 2 of the transfer signals y (1) and y (2) is generated.
  • the input signal x 1 is used as the reconstruction signal r.
  • This reconstruction signal r and the two transfer signals y (1) and y (2) are fed to a reconstruction element REK, from which the output signal a (m) is generated by the following combination of these three signals:
  • circuit block BB2 There is one in circuit block BB2
  • Circuit component ZWB provided for generating four intermediate signals z 1 , z 2 , z 3 , z 4 .
  • the intermediate signal z 1 is generated so that it is always logic ZERO.
  • the intermediate signal z 4 is generated so that it is always logically ONE.
  • Circuit component ZWB an EXOR logic element EXOF is provided, which the two input signals x 1 and x 2
  • MUX4.1 are provided. All four intermediate signals z 1 , z 2 , z 3 and z 4 are supplied to each of the multiplexer elements MUX4.
  • the binary digits of the logic signal m are supplied to the sub-circuit UEB.
  • the multiplex elements MUX4.0 and MUX4.1 are provided, which are the same as those in FIG. 1 and FIG. 2, and which are also controlled in each case on the basis of two of the binary digits in the form of two of the binary control signals which control the Multiplex elements MUX4 are supplied.
  • the multiplexer input signals Of the four supplied multiplexer input signals, one is selected and passed on as a multiplexer output signal.
  • the multiplexer input signal to be selected first is intermediate signal z 1 for both multiplex elements MUX4 dss. According to Table 2, this can be represented as a logical link according to 0 d .
  • the multiplexer input signal to be selected as the fourth is the intermediate signal z 4 in both multiplex elements. Accordingly, this can be represented according to Table 2 as a logical link according to 15 d .
  • the EXOR logic element EXOR which is the same as that of FIG. 1, generates the intermediate signal z 2 by EXOR logic of the two input signals x 1 and x 2 .
  • the intermediate signal z 2 can therefore be represented according to Table 2 as a logical combination according to 6 d .
  • Intermediate signal z 2 is supplied to the multiplex element MUX4.1 and the multiplex element MUX4.0 in the subcircuit UEB as the second multiplexer input signal to be selected.
  • Table 2 can be represented as a logic operation according to FIG. 9 d , is supplied in the sub-circuit UEB to the multiplex element MUX4.1 and the multiplex element MUX4.0 as the third multiplexer input signal to be selected.
  • the selection of the multiplexer input signals takes place in the multiplex elements MUX4 in such a way that the binary digits supplied in each case, that is on the one hand for 2 0 , 2 1 for the multiplex element MUX4.0 and on the other hand for 2 3 , 2 2 for
  • Specify multiplexer element MUX4.1 as a two-digit binary number, which number of the four multiplexer input signals must be selected.
  • the multiplier element MUX4.0 is given as the low-order binary number if dis dis binary number 2 1 of the link signal m, and as the higher-order binary number, the binary number 2 0 of the link signal m is given for selection control.
  • the multiplexer element MUX4.1 is entered as the low-value binary digit dis binary digit 2 2 of the link signal m, and the binary digit 2 3 of the link signal m is entered as the higher-order binary digit for selection control.
  • the first through fourth multiplexer input signals are selected in accordance with the two-digit binary numbers 00 through 11.
  • the selected signals are received as a transfer signal y (1) from the multiplexer element MUX4.0 and on the other hand as a transfer signal y (2) from the multiplexer element
  • transfer signals y (1) and y (1) are accordingly selected in accordance with Table 5 already explained, specifically as a function of the binary digits supplied in each case, by means of which the signal link m to be specified in a definable manner is defined in each case.
  • the binary digits agreed by definition for the respective variable signal combination m to be specified are given in Table 2 already explained.
  • Reconstruction signal r the input signal x 1 is used.
  • the reconstruction signal r and the two transfer signals y (1) and y (2) are fed to a reconstruction element REK, which is the same as that of FIG. 1 and which forms a multiplexer element MUX2.
  • the output signal a (m) is generated by the reconstruction element REK, which is formed according to the variably to be predetermined combination m of the input signals x 1 and x 2 .
  • Table 5 already explained, lists which of the multiplexer input signals according to
  • a (m) y (1) .x 1 + y (2) . 1 ; Wis already based on
  • the output signal a (m) can be variably specified according to the following table 9 as its truth table.
  • FIG. 4 shows, a number K of logical input signals is provided in a third circuit, and a logical output signal a (m) is generated in accordance with a logic combination which can be predetermined.
  • Linking is carried out according to the table 6 explained above in the form of a link signal m by means of a binary number
  • 2 L , 2 L-1 , ..., 2 1 , 2 0 ; L 2 K-1 ; can be entered as binary control signals.
  • These binary digits are supplied in groups of four each to one of the provided sub-circuits UEB, which are the same as those in FIG. 3 and whose number N is 2 K-2 .
  • a circuit component ZWB which is the same as that of FIG. 3, combines the two input signals x K-1 and x K to generate four intermediate signals, which are fed to each of the sub-circuits UEB, as well as the sub-circuit UEB shown in FIG.
  • the next subcircuits UEB are the logical signals of the next four Higher-order binary digits are supplied in the same way from the link that can be variably specified according to Table 6. Accordingly, the logic signals of the binary digits according to 2 L , 2 L-1 , 2 L-2 , 2 L-3 are fed to the last subcircuit UEB.N from the logic combination which can be variably specified according to Table 6.
  • circuit component ZWB and the sub-circuits UEB.n; n 1, ... N; form a circuit block BB2N.
  • Reconstruction elements REK.n; n 1, 2, ... N; supplied to the reconstruction circuit REKS.K-1. Likewise, each of these reconstruction elements REK.n is supplied with the input signal x K-1 as a reconstruction signal. Each of these reconstruction elements REK.n consequently generates a further transfer signal, the number of which is equal to N, as the output signal. These become a further reconstruction circuit REKS.K-2
  • Each of these reconstruction elements REK.n is also the input signal x K-2 as a reconstruction signal
  • Each disser reconstruction element REK.n consequently generates a further transfer signal as an output signal. These are fed to a further reconstruction circuit, etc.
  • the penultimate of these reconstruction circuits that is to say the reconstruction circuit REKS.2, is therefore four
  • each of the reconstruction elements REK.1, REK.2 is supplied with the input signal x 2 as a reconstruction signal.
  • Each of the reconstruction elements REK.1, REK.2 accordingly generates as
  • This reconstruction element REK generates the output signal a (m) .
  • the output signal a (m) is generated by the reconstruction circuit REKS.1 using the input signal x 1 as a reconstruction signal from two transfer signals as follows:
  • a (m) y (1) .x 1 + y (2) . 1 ;
  • the transfer signals y (1) , y (2) are transfer signals of a first order. Each of these is before the reconstruction circuit REKS.2 from js two more
  • y (1,1) , y (1,2) , y (2, 1) , y (2, 2) of the second order is made by one of the reconstruction circuits from each of two transfer signals from a third order with the aid of one of the input signals as a reconstruction signal generated, etc.
  • the respective characteristics of one of the transfer signals are like follows when indexed indexes are listed for better
  • the reconstruction circuit REKS.K-1 generates transfer signals of an order K-1 from the transfer signals of an order K-1:
  • the transfer signals of order K-1 used in this process are sent to the reconstruction circuit REKS.K-1 by the circuit block
  • FIG. 5 shows a fourth circuit for generating a logical output signal a (m) from a number K of logical input signals x 1 , x 2 , ... x K , according to a variably predeterminable logical signal combination. It is a circuit block
  • the transfer signals y (n) are fed with the input signals x 1 to X K-2 used as reconstruction signals to a reconstruction block REKON.YZ. This has its own AND gate for each transfer signal y (n)
  • AND.YZ is such a variation of the inversions for the input signals x 1 to x K-2 provided in accordance with the ascending order for n to form all combinations, so that according to the order of the input signals x 1 to x K-2 for the first supplied input signal x 1 is least varied, and more frequently for the next following one, and for the last one supplied
  • Input signal x K-2 the inversion is most often varied.
  • the inversions are shown as inverting inputs from the AND logic elements.
  • OR.YZ which generates the logical output signal a (m) in accordance with an OR logic operation.
  • the generated output signal a (m) is accordingly generated as follows.
  • One of each of the reconstruction element REK.n is thus two supplied signals selected, either y (n, 1) or y (n, 2) , and forwarded. This selection is controlled by the input signal x K-1 supplied to the reconstruction element REK.n as a control signal, the signal value of which as one
  • the reconstruction element REK thus selects one of two as a multiplexer element
  • Input signal as a supplied binary digit.
  • a multiplexer element MUXN can therefore be used as the reconstruction block REKON.YZ.
  • FIG. 6 shows a fifth circuit for generating a logical output signal a from a number K of logical input signals in accordance with a variably predeterminable logical combination.
  • Transfer signals y (n) ; n 1, ... 2N; in a manner which has already been explained with reference to FIG. 4, generated by a circuit block BB2N.
  • Transfer signals y are converted into a reconstruction with the input signals x 1 to x K-1 used as reconstruction signals. block REKON.RS fed. For each of the transfer signals y (n), this has its own AND gate AND.RS.n;
  • n 1.2, ... 2N; on which one is different
  • UND.RS.n are according to their ascending order for n starting with the transfer signal y (1) for the AND logic element AND.RS.1 and then with the transfer signal y (2) for the
  • a transfer signal y (n) is supplied so that the last AND logic element AND.RS.2N is supplied with the transfer signal y (2N) .
  • a multiplexer element MUX2N can be used as a reconstruction block REKON. Therefore, a multiplexer element MUX2N can be used.
  • FIG. 7 shows a sixth circuit for generating a logical output signal according to a variably predeterminable logical combination.
  • the output signal a (m) is made by means of a single large multiplexer element MUX4N as a reconstruction block REKON.
  • M generates, which in each case selects a binary digit from a number 4N of supplied binary digits of the linking signal m and passes it on as output signal a (m) , in each case depending on the train-led signal values of the input signals x 1 to x K.
  • the link signal m is as a 4N tuple of its singular binary digits.
  • only half the multiplexer element MUX2N is required due to the generated transfer signals.
  • FIG. 8 shows, a seventh circuit has been assigned
  • Disser contains a circuit component ZW0 for generating 16 intermediate signals z 0 , z 1 ... z 15 . These are entered into each of two MUX16 multiplexer elements, each one of which Select 16 intermediate signals and forward them as transfer signals y (1) and y (2) .
  • the two multiplexer elements MUX16 form a subcircuit UEC.
  • Circuit components ZWC form the circuit block BC2.
  • Each of the MUX16 multiple elements is controlled by four control lines, each of which is used as a control signal
  • Binary digits are entered, which, when put together to form a binary number, result in the logical link to be specified for the input link signal m.
  • the binary digits for 2 4 , 2 5 , 2 0 , 2 1 of the binary number for the link signal m are input to the first multiplex element MUX16.1, which is in accordance with one of the input binary digits
  • MUX16.1 is. The binary digits for 2 7 , 2 6 , 2 3, 2 2 from the
  • Multiplexer element MUX16.2 entered, which according to a further binary number fixed by these entered binary digits therefrom as the transfer signal y (2) that of
  • y (1) is selected from ... (z 0 , z 2 , z 1 , z 3 , z 0 , z 2 , z 1 , z 3 , z 0 , z 2 , z 1 , z 3 , z 0 , z 2 , z 1 , z 3 , z 0 , z 2 , z 1 , z 3 , z 8 , z 10 , z 9 , z 11 , z 8 , z 10 , z 9 , z 11 , z 8 , z 10 , z 9 , z 11 , z 8 , z 10 , z 9 , z 11 , z 8 , z 10 , z 9 , z 11 , z 8 , z 10 , z 9 , z 11 , z 4 , z 10 , z 9 , z 11 ,
  • the two transfer signals y (1) and y (2) and, as a reconstruction signal, the input signal x 2 as are fed to a reconstruction element REK, which is the same as that of FIG. 1, to generate the output signal a (m) .
  • the intermediate signals z i are generated by the circuit component ZWC in accordance with Table 12 below.
  • the intermediate signals z i are generated in accordance with the logic operations in the circuit component ZWC shown in Table 12 on the right.
  • a tuple (y (1) , y (2) ) is generated from the Zwix signals in Table 12 as a form of representation of the output signal a (m) and is selected as follows:
  • FIG. 1 An example of a circuit component ZWC is shown in FIG.
  • the input signals x 2 and x 1 become one
  • EXOR logic element EXOR leads to the generation of a
  • Intermediate signals z 1 are intermediate signals z 1 .
  • the intermediate signal z 0 is always generated according to logic ZERO.
  • An AND logic element AND.2 the signal x 2 ⁇ x 3 is input in inverted form and the input signal x 1 is input for the ore generation of the intermediate signal z 2 .
  • Intermediate signals z 4 are input to an OR logic element 0R.5 to generate the
  • Intermediate signals z 5 are input to an OR gate 0R.6 to generate the
  • Intermediate signals z 6 are input to an OR logic element 0R.7 in order to generate the
  • Intermediate signal z 7 inverted to generate the intermediate signal z 8 .
  • the intermediate signal z 6 is inverted by an inverter INV.9 to generate the intermediate signal z 9 .

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Abstract

Un nuplet de signaux logiques de transfert est généré comme forme de représentation d'un enchaînement logique de signaux à partir de signaux logiques d'entrée. Les signaux de transfert peuvent par exemple être générés par une sélection de signaux logiques intermédiaires préparés dans cette intention. Les nuplets de signaux de transfert peuvent être enchaînés afin de former d'autres nuplets de signaux de transfert. En outre, des composants de circuit peuvent être utilisés pour détecter et corriger des erreurs. Par exemple, dans des applications ayant des éléments logiques sensibles aux perturbations ou ayant un grand nombre d'éléments logiques, on peut augmenter de manière déterminante la protection contre des défaillances par correction des erreurs. Un nuplet de signaux de transfert peut être enchaîné avec des signaux de reconstruction afin de générer un signal de sortie.
EP19910914123 1990-10-26 1991-08-01 Procede et circuit generateur de signaux logiques de sortie a partir de signaux logiques d'entree selon des enchainements logiques de signaux Withdrawn EP0554259A1 (fr)

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EP90120591 1990-10-26
EP90120591 1990-10-26

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US6913745B1 (en) 1997-12-02 2005-07-05 Neuralab Limited Passive immunization of Alzheimer's disease

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US3458240A (en) * 1965-12-28 1969-07-29 Sperry Rand Corp Function generator for producing the possible boolean functions of eta independent variables
JPH01116690A (ja) * 1987-10-30 1989-05-09 Fujitsu Ltd 論理演算回路

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