EP0554259A1 - Process and circuit for generating a logic output signal from logic input signals in accordance with a logic signal concatenation - Google Patents

Abstract

A tuple of transfer logic signals is generated as a representation of a logical flow of signals from input logic signals. Transfer signals can for example be generated by a selection of intermediate logic signals prepared for this purpose. The transfer signal tuples can be strung together to form other transfer signal tuples. In addition, circuit components can be used to detect and correct errors. For example, in applications having logic elements sensitive to disturbances or having a large number of logic elements, protection against failures can be decisively increased by error correction. A tuple of transfer signals can be chained with reconstruction signals to generate an output signal.

Description

 Method and circuit for generating a logical

 Output signals from logical input signals according to a logical signal combination.

The invention relates to a method and a circuit for carrying out the method for generating logic

Signals from logical input signals, so that a logical output signal can be generated by means of these signals, which corresponds to a logical signal combination of logical input signals assigned to this output signal. A logical signal combination of logical signals is known. It is known that logical signal combinations can be represented with the aid of logical signals, so-called Boolean signals, whose value set has only a logical ONE and a logical ZERO in many applications. Boolean algebra can be defined in a known manner. It is known that a logical signal combination for all combinations of logical input signal values can be represented in a table form, in a so-called truth table. It is known that two different signal combinations result in the same result if and only if their two defense tables are the same. Signals for a logical ONE and a logical ZERO can be defined in particular in the electronic field, as well as in many other fields, for example optical, pneumatic, mechanical, etc. fields. These defined logic signals can be used as input signals for a large number of definable logic signal combinations. The following forms of representation are known. A logical signal according to a logical variable can be represented. Logical signals and logical variables are to be designated as such by using lower case letters. A logical signal combination of one or more logical signals can be designated according to a logical function of logical variables. Logical functions are to be designated as such by using capital letters and a list of their variables given in brackets. The logic signal generated according to a logic signal combination, like any other logic signal, can be represented as a single logic signal. A single logical signal can be generated by a logical signal combination. As with logical variables and logical functions, a notation is used to designate logical signal combinations. A omitted point immediately between two logical variables denotes an AND operation of these two variables. A plus sign immediately between two logical variables denotes an OR operation. A slash above a logical variable indicates its inversion or negation. A logical variable can also be specified as a parenthesis expression, which contains a logical combination of logical variables. A plus sign within a circle denotes one

EXCLUSIVE-OR operation (EXOR). An equal sign denotes an identical truth table for the respective expressions on the left and right thereof. A AND element can contain a 1 element as a neutral element, so that, for example, a.1 = a. As a logical function, "1" denotes a truth table consisting of logical ONE throughout. As a neutral element can be in a

OR operation can contain an O element, so that, for example, a + 0 = a. As a logical function, "0" denotes a truth table consisting consistently of logical ZERO. An AND operation takes precedence over an OR operation, so that, for example, a + bc = a + (bc). A negation of an AND operation of two variables is equal to an OR operation of the inverted variables, so that for example the following applies from = A negation of an OR combination of two variables is equal to one

 AND operation of the inverted variables, so that

for example = a An AND operation of a Variables with the inverted variable always result in logical ZERO, so for example a. a = 0. An OR combination of a variable with the inverted variable always gives a logical ONE, so that, for example, a + a applies = 1. One

 ANDing a variable with a 0 element always results in logic ZERO, so that, for example, a.0 = 0. ORing a variable with a 1 element always results in logic ONE, so that, for example, a + 1 = 1 An AND operation of a first variable with an OR operation of a second and a third variable is equal to an OR operation of an AND operation of the first and second variables with an AND operation of the first and third variables, so that, for example, a . (b + c) = ab + ac An AND combination of a first and a second variable is equal to an AND combination of the second and the first variable, so that, for example, a.b = b.a. An OR combination of a first and a second variable is equal to an OR combination of the second and the first variable, so that, for example, a + b = b + a.

In a known manner, additional logic signals can be generated in order to be able to recognize errors in the storage or transmission of several individual logic signals. Parity bits are generated, for example, by an EXOR combination of several individual signals to be checked. With the aid of Hamming coding, errors can be recognized and also corrected from a plurality of such parity bits by using a parity bit additionally generated by them

 Syndrome word is generated, which is used for error correction.

The object of the invention is to provide a further method and a circuit for carrying out this method for generating logical signals from logical input signals, so that a logical output signal can be generated by means of these signals, which is a logical

Signal linkage of the input signals corresponds. This object is achieved by a method with the features of claim 1 and by a circuit with the features of claim 14. Preferred embodiments and developments of the invention result from the subclaims.

The invention is based on the knowledge that a tuple of logical transfer signals can be generated from the logical input signals as a form of representation of a

logical signal combination. Transfer signals can be generated, for example, by means of a selection from logical intermediate signals prepared for this purpose. Transfer signal tuples can be linked to form additional transfer signal tuples. In addition, circuit components can be used for error detection as well as for error correction.

For example, in the case of applications with fault-prone logic switching elements and in the case of a large number of logic switching elements, failure safety can be decisively increased in accordance with the error corrections. A tuple of transfer signals can be linked to reconstruction signals

Generation of an output signal. For such tuples from

Transfer signals can be defined as an algebra logical connections corresponding to the logical connections already explained. It can be shown that this can be achieved by using transfer signals which can be generated for a respectively assigned reconstruction signal,

 Scatter signal, arbitrary signal. Relations as regulations, which are to be observed, can be specified in a general manner as well as for preferred embodiments. The designation input signal, transfer signal, output signal refers to a circuit for generating a logic signal combination. For the time being, it does not seem sensible that to generate a single output signal from a number of input signals according to a logical signal combination, first several signals in the form of a tuple of transfer signals

should be generated. That this brings advantages is sometimes not immediately recognizable. The finding of suitable reconstruction signals whose pairwise AND combination is always logical ZERO and whose combined OR combination is always logical ONE is carried out by

 Use of tuples to represent these signals in

 Dependency on all combinations of input signal values advantageously facilitated.

A logical demonstration signal should be considered to explain the notation used. This is to be generated by a logical signal combination from two logical input signals. The demonstration signal generated is to be represented as a logical variable d. The two input signals should be represented as logical variables x ₁ and x ₂ . The logical signal combination is to be represented as a logical function D (x ₂ , x ₁ ) of the two variables x ₁ and x ₂ . Hence d = D (x ₂ , x ₁ ). Depending on the input signals, one is generated according to the given logical signal combination

Obtained demonstration signal value of the demonstration signal as an output signal. By means of indexing, these are to be distinguished from a respective combination of logical input signal values of the two input signals in accordance with the following definition d ₁ = D (1,1); d ₂ = D (0.1); d ₃ = D (1.0); d ₄ = D (0.0); Accordingly, a truth table for listing all output signal values as a function of all possible combinations of input signal values can be represented as table 1 for the given logical signal combination.

Table 1

Different logical signal combinations with one

same truth table are considered equivalent. to

Differentiation of output signals should therefore appear in the corresponding truth table

 Output signal values are checked. In the case of the same truth table, an equality should apply, which should be expressed by an equal sign in the representation.

For example, if the two are ORed

The following applies to input signals: d = D (x ₂ , x ₁ ) = x ₂ + x ₁ ;

d ₁ = D (1,1) = 1; d ₂ = D (0.1) = 1; d ₃ = D (1.0) = 1;

d ₄ = D (0.0) = 0; Different forms of representation are used for a representation of the demonstration signal

Identification of its given logical signal combination.

On the one hand, the respective demonstration signal values for all combinations of input signal values are combined in one

Number tuples summarized according to the following definition:

(d ₄ , d ₃ , d ₂ , d ₁ ) = d = (D (0.0), D (1.0), D (0.1), D (1.1));

The considered OR operation can also be represented by definition by the following tuple (d ₄ , d ₃ , d ₂ , d ₁ ) = (0,1,1,1);

On the other hand, the respective demonstration signal values for all combinations of input signal values can be combined in a binary number as their binary digits according to the following definition: (d ₄ d ₃ d ₂ d ₁ ). = (0111) _b = 0111 _b ; For better identification as a binary number in this notation

 Binary digit values, which are indicated by a parenthesis

 can be summarized by a subscript "b" marked as binary digits of a binary number. Number tuples and binary numbers are therefore by definition an equivalent form of representation of an output signal of a given one

logical signal combination of input signals. A decimal number with the same numerical value can be specified as an equivalent form of representation for the binary number, ie 0111 _b = (7) _d ; For better identification as a decimal number, this one

 Notation Decimal digit values, which are indicated by a omitted

Brackets can be summarized, marked as such by a subscript "d". Within the bracketed expressions marked by the subscript "d", there are always definitions, multiplications, Potentiations, etc. to be carried out according to the known

Calculation rules for numbers. It can be seen from Table 1 that a truth table for a logical signal combination of two input signals contains four output signal values. 2 ⁴ different truth tables are thus possible for 2 ⁴ different predeterminable logic signal combinations. As already explained, these can be identified by their associated decimal number. For example, the output signal values of the demonstration signal d in question can be represented in the form of a number tuple (d ₄ , d ₃ , d ₂ , d ₁ ) and in the form of a binary number (d ₄ d ₃ d ₂ d ₁ ) _b as well as in the form of representation as the associated one Identify the decimal number (m) _d , as well as the logical function D (x ₂ , x ₁ ) in the representation form, the respective logical signal combination. Accordingly, a number of 2 ⁴ = 16 different logical signal combinations can be represented. to

Differentiation of these individual logical signal links are marked by a preferably superscript

Indicator, which should be given within brackets. This decimal number is to be used as this indicator, the numerical value of which is equal to that binary number, the binary digits of which correspond to the numbers of the number tuple, and whose binary digits, as already explained, can be found in the respective truth table from the logical signal combination considered in each case. This will be explained in more detail using Table 2.

Table 2 1

 2

Table 2 lists among them 2 ⁴ = 16 number tuples according to the form of representation explained:

(d ₄ ^(m) , d ₃ ^(m) , d ₂ ^(m) , d ₁ ^(m) ) = D ^(m) (x ₂ , x ₁ ) = d ^(m) ; d ₄ ^(m) = D ^(m) (0.0); d ₃ ^(m) = D ^(m) (1.0); d ₂ ^(m) = D ^(m) (0.1);

d ₁ ^(m) = D ^(m) (1,1);

 The following also applies, for example

d ⁽⁸⁾ = d ⁽⁷⁾ ; d ⁽⁹⁾ = d ⁽⁶⁾ ; etc., or d ^{(8 + i)} = ^(7-i) ;

 The same applies

d ⁽³⁾ = d ⁽²⁾ + d ⁽¹⁾ ;

d ⁽⁵⁾ = d ⁽⁴⁾ + d ⁽¹⁾ ; d ⁽⁶⁾ = d ⁽⁴⁾ + d ⁽²⁾ ; d ⁽⁷⁾ = d ⁽⁴⁾ + d ⁽³⁾ ;

Easier generation can be derived from this. Above each number of the number tuples listed one below the other in Table 2, the logical input signal values are given for x ₁ and x ₂ for determining the respective number of the number tuple according to Table 1 as a truth table. In addition, a form of representation equivalent to the respective number tuple as a binary number is listed below one another in Table 2. Furthermore, an equivalent representation as a decimal number is listed next to each other in Table 2. Likewise listed in Table 2 is a symbolic representation of the given logical signal combination.

 And finally, table 2 shows an associated name for the respective demonstration signal. So in Table 2 they are

Demonstration signal values listed for all different truth tables for the respective logical signal combination of two input signals x ₁ and x ₂ . For a larger number K of input signals x _k ; k = 1, ... K; this can be expanded. The respective truth table contains, in each case, a number T = 2 ^K of output signal values, for example for a signal signal considered for this purpose, in accordance with all combinations of logical input signal values for the respectively predetermined logical signal combination of the input signals

Demonstration signal d = D (x _K , ... x ₁ ); For the output signal values of the demonstration signal is by indexing

the following definable:

d _T = D (0.0.0, ... 0.0.0);

d _T-1 = D (1.0.0, ... 0.0.0);

d _T-2 = D (0.1.0, ... 0.0.0);

d _T-3 = D (1.1.0, ... 0.0.0); d ₄ = D (0,0,1, ... 1,1,1);

d ₃ = D (1,0,1, ... 1,1,1);

d ₂ = D (0.1.1, ... 1.1.1);

d ₁ = D (1,1,1, ... 1,1,1);

With these indexed output signal values, the truth table according to Table 3 is obtained. Table 3

There is an associated logical to this truth table

Signal linkage, by definition, can be represented as the following number tuple (d _T , d _T-1 , d _T-2 , ... d ₃ , d ₂ , d ₁ ); Based on this

 According to the definition of the truth table, the assigned logical signal combination can be represented as the following binary number

(d _T d _T-1 d _T-2 ... d ₃ d ₂ d ₁ ) _b . For this binary number, the given logical signal combination can be represented by definition using a decimal number with the same numerical value

(m) _d = D (x _K , x _K-1 , ... x ₂ , x ₁ ) = d; This number m is intended for this

 are used, the different predeterminable

 Mark truth tables for logical signal combinations as a superscript indicator

d ^(m) = D ^(m) (x _K , ... x ₁ ) = (m) _d ; A number equal to 2 ^T from different truth tables can be specified

Definition of a logical signal combination to be specified from a number K of input signals x _k ; k = 1, ... K. The

The numerical value of the number m is therefore in this case from a range from 0 to M = 2 ^T -1. Each demonstration signal d ^(m) can therefore be optionally represented by definition - either as a number tuple (d _T ^(m) , d _T-1 , ..., d ₁ ^(m) ), or as a binary number (d _T ^(m) . .. d ₁ ^(m) ) _b ,

- or as a decimal number (m) _d ,

- or as a logical function D ^(m) (x _K , x _K-1 , ... x ₁ ). If you now look at Table 2 again, they are

Demonstration signals d ^{(m) shown} for K = 2. For each demonstration signal d ^(m) there are demonstration signal values d _t ^(m) ; t = 1, ... T; the number of which is equal to T = 2 ^K = 4. The number of demonstration signals d ^(m) ; m = 0.1, ... M; is equal to 1 + M = 2 ^T = 16; The numbering of the demonstration signals m = 0.1, ... 15 was carried out in such a way that their number m is equal to the decimal number for representing the demonstration signal, ie d ^(m) = (m) _d . In these

Forms of representation of logical signals as a result of a given logical combination, these logical signals can be linked and represented in further logical combinations. For example, the input signal x _{1 can} always be represented by the demonstration signal d ⁽³⁾ , and that

Input signal x ₂ can always also be represented by the demonstration signal d ⁽⁵⁾ , as can be seen from Table 2. The input signals, for example x ₁ and x ₂ , can therefore also be represented in the form of number tuples, ie x ₁ = (0,0,1,1); x ₂ = (0,1,0,1); Accordingly, each logical link can be represented and checked in a clear representation, for example in that of the number tuples, for example

x ₁ ⊕ ₂ = (0,0,1,1) ⊕ (1,0,1,0) = (1,0,0,1); The number tuples can also be used as logical vectors, for example

to be viewed as. At each position the number of

Number tuples, for example, as an output signal to one

certain combination of input signal values considered.

This number is linked to that number of the number tuple at the same position, which corresponds to the same combination of input signal values, to the respective number of the

Number tuples in exactly the same position as the result of the respective logical link. One of the demonstration signals, for example d ⁽⁹⁾ , can be represented by linking other demonstration signals, or by by definition associated number tuple, or by

binary numbers by definition, or by

associated decimal numbers by definition, or by a logical combination of these or by a logical function of these:

d ⁽⁹⁾ = D ⁽⁹⁾ (d ⁽⁵⁾ , d ⁽³⁾ ) = d ⁽³⁾ ⊕ ⁽⁵⁾ = d ⁽³⁾ ⊕ d ⁽¹⁰⁾ =

= (0,0,1,1) ⊕ (1,0,1,0) = (1,0,0,1) = 1001 _b = 0011 _b ⊕ 1010 _b =

= 3 _d ⊕ 10 _d = 9 _d = D ⁽⁹⁾ (5 _d , 3 _d ); In this way, logical signals and their logical links

be clearly displayed. With those considered

For demonstration signals, the associated decimal digit as a superscript number also serves to identify the associated truth table. This is not necessarily the case with other logic signals. Generally serves a

Superscript mark only for identification, for example in the form of a number for numbering logical signals. According to the invention, for a number K of input signals x _k ; k = 1, ... K; 2 K; another number N of

Reconstruction signals r ⁽ⁿ⁾ ; n = 1, ... N; 2 N 2 ^k ;

be specified so that their pairwise AND combination always gives a logical zero r ⁽ⁿ¹⁾ .r ⁽ⁿ²⁾ = 0; n1 ≠ n2; and so that their combined OR combination always gives a logical ONE r ^(N) + r ^(N-1) + ... + r ⁽²⁾ + r ⁽¹⁾ = 1;

Reconstruction signals of this type are easier to find and check, particularly in their form of representation as a number tuple. For example, the following reconstruction signals r ^{(n) can be} specified for K = 2 and N = 3

r ⁽¹⁾ = (0,0,1,1) = 3 _d ; r ⁽²⁾ = (0,1,0,0) = 4 _d ;

⁽³⁾

r = (1,0,0,0) = 8 _d ; Their pairing of AND operations is particularly based on the reconstruction signal values r _t ⁽ⁿ⁾

Logical number tuples make it easier to check: n1 ≠ n2; r ⁽ⁿ¹⁾ .r ⁽ⁿ²⁾ ₌ = (r ₄ ⁽ⁿ¹⁾ , r ₃ ⁽ⁿ¹⁾ , r ₂ ⁽ⁿ¹⁾ , r ₁ ⁽ⁿ¹⁾ ). (r ₄ ⁽ⁿ²⁾ , r ₃ ⁽ⁿ²⁾ , r ₂ ⁽ⁿ²⁾ , r ₁ ^{(n2 )} ) = = r ₃

(r ₄ ⁽ⁿ¹⁾ . r ₄ ⁽ⁿ²⁾ , ⁽ⁿ¹⁾ . r ₃ ⁽ⁿ²⁾ , r ₂ ⁽ⁿ¹⁾ . r ₂ ⁽ⁿ²⁾ , r ₁ ⁽ⁿ¹⁾ . r ₁ ⁽ⁿ²⁾ ) = = ( 0,0,0,0) = 0 _d = 0; Your summarized OR link can also be checked, for example with the help of

Number tuples r ⁽¹⁾ + r ⁽²⁾ + r ⁽³⁾ =

= (r ₄ ⁽¹⁾ + r ₄ ⁽²⁾ + r ₄ ⁽³⁾ , r ₃ ⁽¹⁾ + r ₃ ⁽²⁾ + r ₃ ⁽³⁾ ,

, r ⁽¹⁾ + r ⁽²⁾ + r ₂ ⁽³⁾ , r ₁ ⁽¹⁾ + r ₁ ⁽²⁾ + r ₁ ⁽³⁾ ) =

= (1,1,1,1) = 15 _d = 1; Assigned to each

Reconstruction signal r ⁽ⁿ⁾ according to the invention, for example, the following scatter signals can be specified s ⁽¹⁾ = (1,0,0,0) = 8 _d ;

s ⁽²⁾ = (0,0,0,1) = 1 _d ; s ⁽³⁾ = (0,0,0,0) = 0 _d ; Your

AND linkage with the assigned reconstruction signal is always logic zero. This can also be checked using number tuples. n = 1,2,3; r ⁽ⁿ⁾ . s ⁽ⁿ⁾ =

= (r ₄ ⁽ⁿ⁾ , r ₃ ⁽ⁿ⁾ , r ₂ ⁽ⁿ⁾ , r ₁ ⁽ⁿ⁾ ).

(s ₄ ⁽ⁿ⁾ , s ₃ ⁽ⁿ⁾ , s ₂ ⁽ⁿ⁾ , s ₁ ⁽ⁿ⁾ ) = = (r ₄ ⁽ⁿ⁾ . s ₄ ⁽ⁿ⁾ , r ₃ ⁽ⁿ⁾ .s ₃ ^{(n )} , r ₂ ⁽ⁿ⁾ .s ₂ ⁽ⁿ⁾ , r ₁ ⁽ⁿ⁾ . s ₁ ⁽ⁿ⁾ ) =

= (0, 0, 0, 0) = 0 _d ; Associated with each reconstruction signal

(n) According to the invention, the following arbitrary signals b (n) can be selected as desired:

b ⁽¹⁾ = (1,1,1,1) = 15 _d ; b ⁽²⁾ = (1,1,0,1) = 13 _d ;

b ⁽³⁾ = (0,1,1,1) = 7 _d ; Assigned to everyone

In this case, according to the invention, the reconstruction signal, the transfer signals are to be determined as follows:

y ⁽¹⁾ = ar ⁽¹⁾ + b ⁽¹⁾ .s ⁽¹⁾ = a.3 _d + 15 _d .8 _d = a.3 _d + 8 _d ;

y ⁽²⁾ = ar ⁽²⁾ + b ⁽²⁾ .s ⁽²⁾ = a.4 _d + 13 _d .1 _d = a.4 _d + 1 _d ;

y ⁽³⁾ = ar ⁽³⁾ + b ⁽³⁾ .s ⁽³⁾ = a.8 _d + 7 _d .0 _d = a.8 _d ; For the

Output signal a is not yet a logical to be specified

Signal linkage A (x ₂ , x ₁ ) explicitly defined. The

 Output signal a is intended as a logical signal combination

A (x ₂ , x ₁ ) of the input signals x ₁ and x _{2 are} specified, for example on the basis of a truth table to be specified, which can be specified as table 4 as follows. Table 4

The output signal a is accordingly represented by the number tuple ar s = A (x ₂ , x ₁ ) = (a ₄ , a ₃ , a ₂ , a ₁ ); In this case, the transfer signals can be represented as follows:

y ⁽¹⁾ = (a ₄ , a ₃ , a ₂ , a ₁ ) .3 _d + 8 _d = (1, 0, a ₂ , a ₁ );

y ⁽²⁾ = (a ₄ , a ₃ , a ₂ , a ₁ ) .4 _d + 1 _d = (0, a ₃ , 0, 1);

y ⁽³⁾ = (a ₄ , a ₃ , a ₂ , a ₁ ) .8 _d = (a ₄ , 0, 0, 0);

 Due to the number tuple of these three transfer signals

y ⁽¹⁾ = (1,0, a ₂ , a ₁ ); y ⁽²⁾ = (0, a ₃ , 0.1); y ⁽³⁾ = (a ₄ , 0,0,0);

 a regulation is established. Such a rule for generating, using and linking the transfer signals can be formulated and specified as in algebra. Since such a rule is preferred as algebra for linking logical tuples of numbers

can be formulated, it is referred to as BOOT algebra, as an abbreviation for "boolean tuple algebra". According to the number N of transfer signals, it is referred to as a BOOT _N algebra. This will be explained in more detail below. For example, by means of the demonstration signals explained above, logical signal combinations of input signals can be defined by definition. Any logical

 Signal linkage of input signals, which in turn can each be represented as one of the demonstration signals, always delivers one of the output signals

 Demonstration signals. So any logical one

Function can be represented and in turn can be linked. According to the invention, a so-called BOOT _N is to be a tuple of a number N of logical functions, which are to be used in each case to generate the transfer signals. By means of these logical functions of the tuple, it should be possible to determine that logical function which is used to generate the output signal is to be applied. To the number N of the following logical ones

Functions y ⁽ⁿ⁾ (x _K , ... x ₁ ); n = 1, ... N; the BOOT according to the invention is _N (Y ⁽¹⁾ (x _K , ... x ₁ ), ..., Y ^(N) (x _K , ... x ₁ ));

According to the invention, according to these functions, transfer signals are to be generated which, for example, can be represented in the form of a number tuple or as a binary number or as a decimal number. According to the invention, a tuple is used which contains the output signal which can be generated therefrom and the signal combination of the input signals associated with this output signal

is assigned, consisting of a number of logical transfer signals which are generated in such a way that each of these transfer signals has an OR combination of an AND combination of the output signal with a reconstruction signal assigned to the transfer signal and an AND combination of an OEM transfer signal each assigned arbitrary signal with a respective scatter signal assigned to the transfer signal, and that each AND operation of each of the reconstruction signals with another of the reconstruction signals is always logically ZERO, and that an OCER operation of all

Reconstruction signals is always logically ONE, and that each AND operation of each of the reconstruction signals with the respectively assigned scatter signal is always logically ZERO, so that the output signal is based on this tuple

 Transfer signals by means of an OR link from all

AND operations of each of the transfer signals with the respective assigned transfer signal

Reconstruction signal can be generated.

The previously explained transfer signals y ⁽¹⁾ = (1,0, a ₂ , a ₁ ); y ⁽²⁾ = (0, a ₃ , 0.1); y ⁽³⁾ = (a ₄ , 0,0,0); can also be specified as the following BOAT ₃ :

(y ⁽¹⁾ , y ⁽²⁾ , y ⁽³⁾ ) = ((1.0, a ₂ , a ₁ ), (0, a ₃ , 0.1), (a ₄ , 0.0, C ));

The following logical combination can be given for the output signal, for example: a = A (x ₂ , x ₁ ) = (a ₄ , a ₃ , a ₂ , e ₁ ) = (0,1,1,0) = 0110 _b = 6 _d = x ₁ ⊕ x ₂ ; Accordingly, in this case, the following handover signals are obtained y ⁽¹⁾ = (1,0, a ₂ , a ₃ ) = (1,0,1,0); y ⁽²⁾ = (0, a ₃ , 0.1) = (0,1,0,1); y ⁽³⁾ = (a ₄ , 0,0,0) = (0,0,0,0); In this case, the BOOT ₃ under consideration is as follows: (y ⁽¹⁾ , y ⁽²⁾ , y ⁽³⁾ ) =

= ((1.0, 1.0), (0.1, 0.1), (0.0, 0.0)) =

- = (1010 _b , 0101 _b , 0000 _b ) = (10 _d , 5 _d , 0 _d );

According to the invention, the output signal is to be a combined OR combination of all AND combinations

can be generated from the associated transfer signals and reconstruction signals:

a - y ⁽¹⁾ .r ⁽¹⁾ + y ⁽¹⁾ .r ⁽²⁾ + y ⁽³⁾ .r ⁽³⁾ ;

This can be checked more easily, for example, in the representation form of the number tuples.

 (1,0,1,0). (0,0,1,1) + (0,1,0,1). (0,1,0,0) +

 + (0,0,0,0). (1,0,0,0) =

= (0,0,1,0) + (0,1,0,0) + (0,0,0,0) = (0,1,1,0) = 6 _d ;

The predefined signal linkage of the input signals for

Generation of the output signal can therefore be represented as the BOOT ₃ according to (10 _d , 5 _d , 0 _d ) by definition. For another logical signal combination of the input signals, for example for x ₁ + ₂ = 11 _{d the} following BOOT ₃ (11 _d , 1 _d , 8 _d ) can be used to define an output signal _that can be generated. These two output signals should be linkable as logic signals, for example by an AND link. For better distinction, there is an indexing in the form of a subscript, which is given in brackets a ₍₁₎ = A ₍₁₎ (x ₂ , x ₁ ) = D ⁽⁶⁾ (x ₂ , x ₁ ) = x ₁ ⊕ x ₂ ; a ₍₂₎ = A ₍₂₎ (x ₂ , x ₁ ) = D ⁽¹¹⁾ (x ₂ , x ₁ ) = x ₁ + ₂ ; a ₍₃₎ = A ₍₃₎ (a ₍₂₎ , a ₍₁₎ ) = D ⁽¹⁾ (a ₍₂₎ , a ₍₁₎ ) = a ₍₁₎ a ₍₂₎ = = D ⁽¹⁾ (D ⁽¹¹⁾ (x ₂ , x ₁ ), D ⁽⁶⁾ (x ₂ , x ₁ )) = (x ₁ ⊕ x ₂ ). (X ₁ + ₂ );

To determine the truth table, for example, the number tuples of a ₍₁₎ and a _{(2) are} linked. a ₍₃₎ = D ⁽¹⁾ (D ⁽¹¹⁾ (x ₂ , x ₁ ), D ⁽⁶⁾ (x ₂ , x ₁ )) =

= D ⁽¹⁾ ((1,0,1,1), (0,1,1,0)) = (1,0,1,1). (0,1,1,0) =

= (0,0,1,0) = 2 _d = x ₁ . ₂ ;

The transfer signals for the linked output signal a ₍₃₎ can be specified in accordance with

= a ₍₃₎ .r ⁽¹⁾ + b ⁽¹⁾ .s ⁽¹⁾ ; = a ₍₃₎ .r ⁽²⁾ + b ⁽²⁾ .s ^(2); = a ₍₃₎ .r ⁽³⁾ + b ⁽³⁾ .s ⁽³⁾ ;

The linked output signal a ₍₃₎ can be generated from it in accordance with:

a ₍₃₎ = y

, r ⁽¹⁾ + y

, r ^(r) + y () ⁾ .r ⁽³⁾ ;

For example, using truth tables or, for example, using number tuples, it can be shown that the transfer signals for the linked output signal a _{(3) can be} obtained by the same logical combination:

= A ₍₃₎ ( _11d , _10d ); = A ₍₃₎ ( _1d , _5d ); = A ₍₃₎ (8 _d , 0 _d );

And you can see that a BOOT ₃ for the linked output signal a _{(3) can also be} obtained by linking:)

= A ₍₃₎ ((11 _d , 1 _d , 8 _d ), (10 _d , 5 _d , 0 _d )) =

= (A ₍₃₎ (11 _d , 10 _d ), A ₍₃₎ (1 _d , 5 _d ), A ₍₃₎ (8 _d , 0 _d )) =

= (D ⁽¹⁾ (11 _d , 10 _d ), D ⁽¹⁾ (1 _d , 5 _d ), D ⁽¹⁾ (8 _d , 0 _d )) =

= (10 _d , 1 _d , 0 _d ); Every logical signal can therefore be represented, like that one

Demonstration signal with the same truth table as an output signal according to a predetermined signal combination of input signals. This link is used to define transfer signals. From these transfer signals, a BOOT belonging to the logic signal is put together, from whose transfer signals the logic signal can be generated. To link such logical signals that can be generated from transfer signals, it is therefore sufficient to link the transfer signals according to the BOOTs. For example, a logic switching mechanism can be constructed which uses a BOOT of transfer signals instead of a single logic signal and which links these BOOTs of transfer signals with one another. For example, for only one output, the logical signal to be output is to be reconstructed and generated from the respective BOOT of transfer signals. Since it is not a single signal, for example in the form of the output signal, but a BOOT of transfer signals according to the invention that is used, these can be checked among themselves and during their generation for errors, for example by using test circuits from which additional test signals are generated. Circuit components can also be provided for generating

Test signals by means of which an incorrectly generated

 Transfer signal is correctable. The regulation according to the invention for generating the transfer signals results in special linking rules by means of which the test circuits and the test signals can be used.

This opens up new ways of building circuits and introducing new types of circuits. For example, applications for

 Error detection, error correction and general safety aspects can be included a priori in circuit designs. For example, applications for encrypting signals can also be achieved and checked as a result.

For example, for applications in programmable logic switchgears (PLAs), an improvement in the form of error detection and error correction is achievable. Particularly in preferred embodiments of the invention, as formulated in the subclaims, there are particular advantages depending on the application.

A preferred embodiment of the invention is characterized in that at least one of the transfer signals can be generated in accordance with an OR combination of all AND combinations of further logical reconstruction signals associated with this transfer signal and one

 Further tuples of this logical transfer signal associated with further transfer signals which are generated in such a way that each of the further transfer signals corresponds in each case to an OR operation of two AND operations, on the one hand of the assigned transfer signal with one of the further ones

 Reconstruction signals and, on the other hand, a further logical arbitrary signal assigned to the further transfer signal with a further logical scatter signal assigned to the further transfer signal, its AND combination with the further reconstruction signal always results in logic ZERO, and that each AND combination of one of the further ones

Reconstruction signals with a different one of the others

Reconstruction signals always result in logic ZERO, and that an OR operation of all the other logic

Reconstruction signals always result in a logical ONE, and that each AND operation of one of the further reconstruction signals with the reconstruction signal associated with the transfer signal does not result in a logical ZERO for all combinations of input signal values, so that the output signal

can be generated by means of an OR link of all

AND operations of the mutually assigned reconstruction signals and transfer signals, with such an AND operation for each of the further transfer signals consisting of the further transfer signal, the further reconstruction signal and the reconstruction signal which is assigned to the assigned transfer signal. For example, consider the BOOT ₃ already explained, the logical functions of which are identified as such by capital letters: Y ⁽¹⁾ (x ₂ , x ₁ ) = A (x ₂ , x ₁ ) .R ⁽¹⁾ (x ₂ , x ₁ ) + B ⁽¹⁾ (x ₂ , x ₁ ) .S ⁽¹⁾ ( x ₂ , x ₁ );

Y ⁽²⁾ (x ₂ , x ₁ ) ₌ A (x ₂ , x ₁ ) .R ⁽²⁾ (x ₂ , x ₁ ) + B ⁽²⁾ (x ₂ , x ₁ ) .S ⁽²⁾ ( x ₂ , x ₁ );

Y ⁽³⁾ (x ₂ , x ₁ ) = A (x ₂ , x ₁ ) .R ⁽³⁾ (x ₂ , x ₁ ) + B ⁽³⁾ (x ₂ , x ₁ ) .S ⁽³⁾ ( x ₂ , x ₁ ); with the following predefined functions:

R ⁽¹⁾ (x ₂ , x ₁ ) = D ⁽³⁾ (x ₂ , x ₁ ) = x ₁ ;

R ⁽²⁾ (x ₂ , x ₁ ) = D ⁽⁴⁾ (x ₂ , x ₁ ) = _1st x ₂ ;

R ⁽³⁾ (x ₂ , x ₁ ) = D ⁽⁸⁾ (x ₂ , x ₁ ) = _{1st 2} ;

S ⁽¹⁾ (x ₂ , x ₁ ) = D ⁽⁸⁾ (x ₂ , x ₁ ) = x ₁ . ₂ ;

S ⁽²⁾ (x ₂ , x ₁ ) = D ⁽¹⁾ (x ₂ , x ₁ ) = x ₁ .x ₂ ;

S ⁽³⁾ (x ₂ , x ₁ ) = D ⁽⁰⁾ (x ₂ , x ₁ ) = 0;

B ⁽¹⁾ (x ₂ , x ₁ ) = D ⁽¹⁵⁾ (x ₂ , x ₁ ) = 1;

B ⁽²⁾ (x ₂ , x ₁ ) = D ⁽¹³⁾ (x ₂ , x ₁ ) = ₁ + x ₂ ;

B ⁽³⁾ (x ₂ , x ₁ ) = D ⁽⁷⁾ (x ₂ , x ₁ ) = x ₁ + x ₂ ;

the following tuple of local functions is specified:

(Y ⁽¹⁾ (x ₂ , x ₁ ), Y ⁽²⁾ (x ₂ , x ₁ ), Y ⁽³⁾ (x ₂ , x ₁ ));

With the help of these three logical functions of this tuple, any logical function A (x ₂ , x ₁ ) can be represented

A (x ₂ , x ₁ ) = Y ⁽¹⁾ (x ₂ , x ₁ ) .R ⁽¹⁾ (x ₂ , x ₁ ) +

+ Y ⁽²⁾ (x ₂ , x ₁ ) .R ⁽²⁾ (x ₂ , x ₁ ) +

+ Y ⁽³⁾ (x ₂ , x ₁ ) .R ⁽³⁾ (x ₂ , x ₁ ) =

= Y ⁽¹⁾ (x ₂ , x ₁ ). (X ₁ ) +

+ Y ⁽²⁾ (x ₂ , x ₁ ). ( ₁ .x ₂ ) +

+ Y ⁽³⁾ (x ₂ , x ₁ ). ( _{1st 2} );

 For example for the following logical function:

A (x ₂ , x ₁ ) = D ⁽⁶⁾ (x ₂ , x ₁ ) = x ₁ ⊕ x ₂ ;

 you get the following tuple of logical functions:

y ⁽¹⁾ (x ₂ , x ₁ ) =

= (x ₁ ⊕x ₂ ). (x ₁ ) + ( x ₁ . x ₂ ) = D ⁽¹⁰⁾ (x ₂ , x ₁ ) = ₂ ;

Y ⁽²⁾ (x ₂ , x1) =

= (x ₁ ⊕x ₂ ). ( ₁ .x ₂ ) + ( x ₁ + x ₂ ). (x ₁ .x ₂ ) = D ⁽⁵⁾ (x ₂ , x ₁ ) = x ₂ ;

Y ⁽³⁾ (x ₂ , x ₁ ) =

= (x ₁ ⊕x ₂ ). ( _{1st 2} ) = D ⁽⁰⁾ (x ₂ , x ₁ ) = 0; (Y ⁽¹⁾ (x ₂ , x ₁ ), Y ⁽²⁾ (x ₂ , x ₁ ), Y ⁽³⁾ (x ₂ , x ₁ )) =

= (D ⁽¹⁰⁾ (x ₂ , x ₁ ), D ⁽⁵⁾ (x ₂ , x ₁ ), D ⁽⁰⁾ (x ₂ , x ₁ )) =

= ( ₂ , x ₂ , 0); With the help of these logical functions of this tuple, the logical function x ₁ ⊕x ₂ just considered can be formed as follows:

A (x ₂ , x ₁ ) = ( x ₂ ). (x ₁ ) + (x ₂ ). ( x ₁ .x ₂ ) + (0). ( x ₁ . ₂ ) =

= x ₁ . x ₂ + x ₁ . x ₂ = x ₁ ⊕x ₂ ;

 It can thus be seen that any logical function can be determined and determined by a tuple of logical functions. This is used when defining transfer signals, from which an output signal can always be generated. It is now to be shown how such a tuple can be expanded, for example by one of the logical ones

Functions of the tuple can be replaced by a tuple of other logical functions. It is also intended to show how a tuple can be reduced, for example by replacing some of the logical functions of the tuple with a single logical function. This will first be explained using transfer signals. For example for the BOOT already considered

(Y ⁽¹⁾ (x ₂ , x ₁ ), Y ⁽²⁾ (x ₂ , x ₁ ), Y ⁽³⁾ (x ₂ , x ₁ )); can the

following tuples of transfer signals (y ⁽¹⁾ , y ⁽²⁾ , y ⁽³⁾ );

y ⁽¹⁾ = ax ₁ + x _{1 2} ; y ⁽²⁾ = a ₁ x ₂ + x ₁ x ₂ ; y ⁽³⁾ = a ₁ x ₂ ; be generated. As already explained, these transfer signals can also be represented as logical tuples of numbers based on the truth tables y ⁽¹⁾ = (1,0, a ₂ , a ₁ ); y ⁽²⁾ = (0, a ₃ , 0.1);

y ⁽³⁾ = (a ₄ , 0,0,0); The tuple of the transfer signals can also be represented, as already explained, as a tuple of logical number tuples:

(Y ⁽¹⁾ , y ⁽²⁾ , y ⁽³⁾ ) = ((1,0, a ₂ , a ₁ ), (0, a ₃ , 0,1), (a ₄ , 0,0,0 ));

If, for example, the transfer signal y ^{(1) is considered} , it should be explained in more detail how further transfer signals can be generated for this transfer signal by using this transfer signal y ⁽¹⁾ as an intermediate that can be generated

Output signal is to be considered, and as such is assigned to the other transfer signals. To identify the signals belonging to the transfer signal y ⁽¹⁾ , the identifier is expanded by a comma and an additional additional identifier, for example in the form of a numbering, within the identifying superscript bracket. For example, two further reconstruction signals r ^(1,1) and r ^{(1,2) should be} specified for a considered transfer signal y ⁽¹⁾ and its associated reconstruction regional r ⁽¹⁾ . A paired AND link should always be logically zero

r ^(1,1) + r ^(1,2) = 0; An OR operation should always result in a logical ONE r ^(1,1) + r ^(1,2) = 1; At least one of AND operations of the associated with the considered transfer signal

Reconstruction signal r ⁽¹⁾ with one of the other reconstruction signals r ^{(l, j)} ; j = 1, 2; should be different from always logically zero: r ^{(l, j)} .r ⁽¹⁾ ≠ 0; j = 1, 2; In addition, for each of these further reconstruction signals r ^{(l, j)} ; j = 1, 2; a further scatter signal s ^{(l, j)} ; j = 1.2; be specified, the AND operation of which is always logically ZERO with the associated further reconstruction signal

r ^{(l, j)} .s ^{(l, j)} = 0; j = 1, 2; In addition, an arbitrarily definable further arbitrary signal is to be specified for each of these additional reconstruction signals b ^{(l, j)} ; j = 1.2; With these predetermined further signals r ^{(l, j)} ; s ^{(l, j)} ; b ^{(l, j)} ; j = 1.2; a further transfer signal can be defined for each further reconstruction signal such as fclct:

y ^(1,1) = y ⁽¹⁾ .r ^(1,1) + b ^(1,1) .s ^(1,1) ;

y ^(1,2) = y ⁽¹⁾ .r ^(1,2) + b ^(1,2) .s ^(1,2) ;

For example, the considered transfer signal y ⁽¹⁾

can be generated by means of the following further reconstruction signals r ^(1,1) ₌ (0,0,1,0) = 2 _d ; r ^(1,2) = (1,1,0,1) = 13 _d ; With

the following regulation for the formation of associated transfer signals y ^(1,1) = y ⁽¹⁾ .r ^(1,1) + b ^(1,1) .s ^(1,1) ;

r ^(1,2) = y ⁽¹⁾ .r ^(1,2) + b ^(1,2) .s ^(1,2) ;

 so that applies

y ⁽¹⁾ = y ^(1,1) .r ^(1,1) .r ⁽¹⁾ + y ^(1,2) .r ^(1,2) .r ⁽¹⁾ ;

If, for example, according to always logic ZERO, the following further scatter signals and further arbitrary signals are specified s ^(1,1) = s ^(1,2) = b ^(1,1) = b ^(1,2) = 0 _d ; instead of the previous three handover signals, the following four are obtained y ^(1.1) = (0.0, a ₂ , 0);

y ^(1,2) = (1,1,0, a ₁ );

y ⁽²⁾ = (0, a ₃ , 0.1);

y ⁽³⁾ = (a ₄ , 0,0,0);

 While according to the previous three handover signals that

 Output signal can be generated according to

a = y ⁽¹⁾ .r ⁽¹⁾ + y ⁽²⁾ .r ⁽²⁾ + y ⁽³⁾ .r ⁽³⁾ =

= (1.0, a ₂ , a ₁ ) .3 _d + (0, a ₃ , 0.1) .4 _d + (a ₄ , 0.0.0) .8 _d =

= (a ₄ , a ₃ , a ₂ , a ₁ );

this is how it is according to the four handover signals now available

Output signal can be generated according to

a = y ^(1,1) .r ^(1,1) .r ⁽¹⁾ + y ^(1,2) .r ^(1,2) .r ⁽¹⁾ +

+ y ⁽²⁾ .r ⁽²⁾ + y ⁽³⁾ .r ⁽³⁾ =

= (0.0, a ₂ , 0) .2 _d .3 _d + (1.1.0, a ₁ ) .13 _d .3 _d +

+ (0, a ₃ , 0.1) .4 _d + (a ₄ , 0.0.0) .8 _d = (a ₄ , a ₃ , a ₂ , a ₁ ); When selecting and checking, in particular, the reconstruction signals and scatter signals, the number tuples of

Table 2 can be used. In the transition from the tuple of the three transfer signals (y ⁽¹⁾ , y ⁽²⁾ , y ⁽³⁾ ) to the tuple of the four transfer signals (y ^(1,1) , y ⁽¹ ' ²⁾ , y ⁽²⁾ , y ^{( 3)} ) the new transfer signals y ^(1,1) and y ^{(1,2 ) are} to be generated from the replaced transfer signal y ⁽¹⁾ as follows:

y ^(1,1) = y ⁽¹⁾ .r ^(1,1) + b ^(1,1) .s ^(1,1) = y ⁽¹⁾ .2 _d ;

y ^(1,2) = y ⁽¹⁾ .r ^(1,2) + b ^(1,2) .s ^(1,2) = y ⁽¹⁾ .13 _d ;

Here y ⁽¹⁾ need not be generated explicitly, because the following applies y ⁽¹⁾ = a.3 _d + 8 _d ; This can be taken into account:

y ^(1,1) = (a.3 _d + 8 _d ) .2 _d = a.2 _d ;

y ^(1,2) = (a.3 _d + 8 _d ) .13 _d = a.1 _d + 8 _d ;

And vice versa, the transition from the tuple of the four transfer signals (y ^(1,1) , y ^(1,2) , y ⁽²⁾ , y ⁽³⁾ ) to the tuple of the three

Transfer signals (y ^(1), y ^(2), y ⁽³⁾⁾ the new handover signal y ⁽¹⁾ from the replaced transfer signals y ^(1,1) and y are generated as follows ^(1,2): y ⁽¹⁾ =

= y ^(1,1) .r ^(1,1) .r ⁽¹⁾ + y ^(1,2) .r ^(1,2) .r ⁽¹⁾ =

= y ^(1,1) .2 _d .3 _d + y ^(1,2) .13 _d .3 _d =

= y ^(1.1) .2 _d + y ^(1.2) .1 _d ; As already explained, for example, the output signal under consideration can be generated in accordance with the following tuple of three transfer signals (y ⁽¹⁾ , y ⁽²⁾ , y ⁽³⁾ ) = (10 _d , 5 _d , 0 _d )

a = y ⁽¹⁾ .r ⁽¹⁾ + y ⁽² ) .r ⁽²⁾ + y ⁽³⁾ .r ⁽³⁾ =

= 10 _d .3 _{d +} 5 _d .4 _d + 0 _d .8 _d = 2 _d + 4 _d + 0 _d = 6 _d ;

By replacing the transfer signal y ⁽¹⁾ with two further transfer signals by:

y ⁽¹ ' ¹⁾ = y ⁽¹⁾ .2 _d = 10 _d .2 _d = 2 _d ;

y ^(1,2) = y ⁽¹⁾ .13 _d = 10 _d .13 _d = 8 _d ;

a tuple of four transfer signals can be generated from the tuple of the three transfer signals:

(y ^(1,1) , y ^(1,2) , y ⁽²⁾ , y ⁽³⁾ ) = (2 _d , 8 _d , 5 _d , 0 _d );

from which the considered signal a = 6 _d can be generated as follows:

a = y ^(1,1) .r ^(1,1) .r ⁽¹⁾ + y ^(1,2) .r ^(1.2) .r ⁽¹⁾ +

+ y ⁽²⁾ .r ⁽²⁾ + y ⁽³⁾ .r ⁽³⁾ =

= y ^(1,2) .2 _d .3 _d + y ^(1,2) .13 _d .3 _d + y ⁽²⁾ .4 _d + y ⁽³⁾ .8 _d =

= y ^(1,1) .2 _d + y ^(1,2) .1 _d + y ⁽²⁾ .4 _d + y ⁽³⁾ .8 _d =

= 2 _d .2 _d + 8 _d .1 _d + 5 _d .4 _d + 8 _d .0 _d = 2 _d + 0 _d + 4 _d + 0 _d = 6 _d ;

As a result, the definitions for BOOT ₃

Y ⁽¹⁾ (x ₂ , x ₁ ) = A (x ₂ , x ₁ ) .x ₁ + x ₁ .x ₂ ;

Y ⁽²⁾ (x ₂ , x ₁ ) = A (x ₂ , x ₁ ) .x ₁ . x ₂ + x ₁ .x ₂ ;

Y ⁽³⁾ (x ₂ , x ₁ ) = A (x ₂ , x ₁ ). x ₁ , x ₂ ;

replaced by the following definitions for a BOOT ₄

Y ^(1,1) (x ₂ , x ₁ ) = A (x ₂ , x ₁ ) .x ₁ , x ₂ ;

Y ^(1,2) (x ₂ , x ₁ ) = A (x ₂ , x ₁ ) .x ₁ . x ₂ + x ₁ .x ₂ ;

Y ⁽²⁾ (x ₂ , x ₁ ) = A (x ₂ , x ₁ ) .x ₁ . x ₂ + x ₁ .x ₂ ;

Y ⁽¹⁾ (x ₂ , x ₁ ) = A (x ₂ , x ₁ ). x ₁ , x ₂ ;

 by instead of the definition

Y ⁽¹⁾ (x ₂ , x ₁ ) = A (x ₂ , x ₁ ) .x ₁ + x ₁ . x ₂ ;

 the two definitions

Y ⁽¹ ' ¹⁾ (x ₂ , x ₁ ) = A (x ₂ , x ₁ ) .x ₁ , x ₂ ;

Y ⁽¹ ' ²⁾ (x ₂ , x ₁ ) = A (x ₂ , x ₁ ) .x ₁ . x ₂ + x ₁ .x ₂ ;

have kicked. In the reverse procedure when replacing the definitions, the BOOT _{4 can} be replaced by the BOOT ₃ . A few special cases will be considered below. For example, for a BOOT _N , the transfer signals of which are the same as the respectively associated reconstruction signals, the logical signal represented thereby is always logical

ONE, so that such a BOAT can be used as a 1 element. (y ⁽¹⁾ , y ⁽²⁾ , ... y ^(N) ) = (r ⁽¹⁾ , r ⁽²⁾ , ... r ^N) ) = 1;

For example, the logic signal shown is always logic ZERO for a BOOT _N , the transfer signals of which are each the same as the respectively assigned scatter signals, so that such a BOOT can be used as an O element.

(s ⁽¹⁾ , s ⁽²⁾ , ... s ^(N) ) = 0; For example, the logical signal shown is always logically ZERO for an AND operation of a BOOT _N consisting of all associated

Reconstruction signals with a BOOT _N likewise consist of all reconstruction signals, but the respective order of the reconstruction signals in each of the BOOTs is a non-identical permutation.

(r ^(p1) , x ^(p2) , ... r ^(pN) ). (r ^(q1) , r ^(q2) , ... r ^(qN) ) = 0;

The following definitions serve to represent the different permutations:

p1, p2, ..., pn, ..., pN = permutation of 1,2, ..., n, ..., N;

q1, q2, ..., qn, ..., qN = permutation of 1,2, ..., n, ..., N;

pn ≠ qn for n = 1, 2, ... N; These are special cases

for example for applications in test circuits

Verification of the reconstruction signals can be used.

For example, based on its truth table for input signals x _k ; n = 1, ... K- a logic signal w can be represented as a BOOT _T for T = 2 ^K ; in that all scatter signals are always given logically ZERO, and in which each reconstruction signal for each column of the truth table, for example according to Table 3, is specified as an AND operation from all input signals, in which all those input signals are contained in inverted form, the input signal value of which is in the respective one is column of the truth table with a logical ZERO angegeten so that the BOOT _T the signal values w _t; t = 1,2, ... T; to form a logical number tuple w = (w _T , W _T-1 , ... w ₂ , w ₁ ) for the signal w according to its Truth table can be adopted

s ⁽¹⁾ = s ⁽²⁾ = ... = s ^(T) = 0;

r ^(T) = x ₁ x2 ... x _{K -1} x _K ;

r ^(T-1) = x ₁ x ₂ ... x _K-1 x _K ; r ⁽²⁾ = x ₁ x ₂ ... x _K-1 x _K ;

r ⁽¹⁾ = x ₁ x ₂ ... x _K-1 x _K ;

For example, the demonstration signals from Table 2 can be represented by the number tuples given in Table 2 as a BOOT ₄ , in which all scatter signals are specified with a logic ZERO and the following reconstruction signals are specified: s ⁽¹⁾ = s ⁽²⁾ = s ^{(3 )} = s ⁽⁴⁾ = 0;

r ⁽¹⁾ = (1,0,0,0) = 8 _d = _{1 2} ; r ⁽²⁾ = (0,1,0,0) = 4 _d = ₁ .x ₂ ; r ⁽³⁾ = (0,0,1,0) = 2 _d = x ₁ . x ₂ ; r ⁽⁴⁾ = (0,0,0,1) = 1 _d = x ₁ .x ₂ ; In the following, further special features will be explained. At each position of a BOOT, a BOOT can again be provided as an element of this BOOT as a form of representation for this element, the reconstruction signals of which can also be specified differently in terms of number and definition. For example, as already explained, a transfer signal y ⁽¹⁾ from a BOOT ₃ by two further transfer signals y ^(1,1) and y ^(1,1) as a BOOT ₂ according to

(y ^(1,1) ), y ⁽¹ ' ²⁾ ).

(y ⁽¹⁾ , y ⁽²⁾ , y ⁽³⁾ ) = ((y ⁽¹ ' ¹⁾ , y ⁽¹ ' ²⁾ ), y ⁽²⁾ , y ⁽³⁾ ); In this case, the represented by the generation

 Output signals to take into account the respective reconstruction signals.

(( ^{y (1,1)} , y ^(1,2) ), y ⁽²⁾ , ^{y (3)} ) =

= (y ^(1,1) .r ^(1,1) + y ^(1,2) .r ^(1,2) , y ⁽²⁾ , y ⁽³⁾ ) =

= y ^(1,1) .r ^(1,1) .r ⁽¹⁾ + y ^(1,2) .r ^(1,2) .r ⁽¹⁾ + y ⁽²⁾ .r ⁽²⁾ +

+ y ⁽³⁾ .r ⁽³⁾ ;

 It can therefore be shown that the following applies:

((r ^(1,1) , r ^(1,2) ), r ⁽²⁾ , r ⁽³⁾ ) = (1, r ⁽²⁾ , r ⁽³⁾ ) = 1; A logical signal can be represented by this BOOT ₃ , in which an element is represented as a BOOT ₂ . The four transfer signals y ^(1,1) , y ⁽¹ ' ²⁾ , y ⁽²⁾ , y ^{(3) of} this BOOT ₃ containing a BOOT ₂ are in the process of generating this shown signals assigned the respective reconstruction signals as follows. The reconstruction signals r ^(1,1) , r ^{(1,2) are} assigned for the BOOT ₂ , so that the following applies:

(r ^(1,1) , r ^(1,2) ) = 1; The reconstruction signals r ⁽¹⁾ , r ⁽²⁾ , r ^{(3) are} assigned for the BOOT ₃ , so that the following applies: (r ⁽¹⁾ , r ⁽²⁾ , r ⁽³⁾ ) = 1;

When extending BOOT ₃ using BOOT ₂ to BOOT ₄ (y ^(1,1) , y ^(1,2) , y ⁽²⁾ , y ⁽³⁾ ); are the following four reconstruction signals, r ^(1,1) . r ⁽¹⁾ , r ^(1,2) .r ^(1,2) .r ⁽¹⁾ , r ^(2), r ⁽³⁾ , so that the following applies:

_(r (1,1) .r ⁽¹⁾ , r ^{(1, 2)} .r ⁽¹⁾ , r ⁽²⁾ , r ⁽³⁾ ) = 1; r ^(1,1) .r ⁽¹⁾ .r ⁽²⁾ = 0; r ^(1,2) .r ⁽¹⁾ .r ⁽³⁾ = 0; r ^(1,2) .r ⁽¹⁾ .r ⁽²⁾ = 0;

r ^(1,2) .r ⁽¹⁾ .r ⁽³⁾ = 0; Regardless of the associated reconstruction signals, it can be shown that the following always applies (1,1, ... 1) = 1; (0.0, ... 0) = 0; As a result, a neutral BOOT in particular can be defined on the one hand as a neutral 1 element for AND operations of BOOTs and on the other hand as a neutral O element for

OR operations of BOOTs.

A further preferred embodiment of the invention is characterized in that a transfer signal can be generated, correspondingly continued further tuples of generated further transfer signals and further reconstruction signals. If, for example, with a larger number K of

Input signals a certain BOOT _N1 is present, this is it

BOOT _{N1 can be} expanded to a BOOT _N2 , whereby N1 applies / - N2 / A

2 ^K ; by continuously generating one of the other transfer signals in such a way that the number of transfer signals continues to increase as a result. The number of transfer signals that can be generated in this way is limited. The limitation depends on the number K of input signals, from the combination of which the

Reconstruction signals for the respective BOOT must always be defined in such a way that their pairs AND operation is always logical ZERO, on the one hand, and

on the other hand, that an OR combination of all is always logically ONE. For this reason, only a number less than or equal to 2 of such reconstruction signals can be defined. BOOTs can therefore only be expanded to a limited extent. While any transfer signal of a considered BCOT can be represented at any time by further transfer signals of, for example, another BOOT, an executable extension of the BOOT by means of the further transfer signals depends on whether the reconstruction signals associated with the further transfer signals with the reconstruction signals of the considered BOOT fulfill the stated relations that their AND combination in pairs is always logically ZERO and an OR combination of all is always logically ONE. To identify those other transfer signals that represent a transfer signal, the superscript and bracketed identifier should be supplemented by a comma and an additional identifier attached to it, for example in the form of a numbering for the other transfer signals. The reconstruction signals assigned to the transfer signals,

Scatter signals and arbitrary signals should also be identified. For example, consider the following BOOT _N :

(y ^(N) , ..., y ⁽ⁿ⁾ , ... y ⁽¹⁾ );

y ⁽ⁿ⁾ = ar ⁽ⁿ⁾ + b ⁽ⁿ⁾ .s ⁽ⁿ⁾ ; n = 1.2, ... N;

r ⁽ⁿ⁾ .s ⁽ⁿ⁾ = 0; n = 1, ... N;

r ⁽ⁿ¹⁾ .r ⁽ⁿ²⁾ = 0; 1 L n1 n2 LN;

r ^(N) + r ^(N-1) + ... + r ⁽ⁿ⁾ + ... + r ⁽¹⁾ = 1;

a = y ^(N) .r ^(N) + ... + y ⁽ⁿ⁾ .r ⁽ⁿ⁾ + ... y ⁽¹⁾ .r ⁽¹⁾ ;

 From this BOAT a certain transfer signal,

for example y ⁽ⁿ⁾ , are represented by further transfer signals, by means of which the following further BOOT _J can be formed to represent y ⁽ⁿ⁾ :

(y ^{(n, J)} , y ^{(n, J-1)} , ..., y ^{(n, j)} , ... y ^{(n, 1)} );

y ^{(n, j)} = y ⁽ⁿ⁾ .r ^{(n, j)} + b ^{(n, j)} .s ^{(n, j)} ; j = 1,2, ... J;

r ^{(n, j)} .s ^{(n, j)} = 0; j = 1,2, ... J;

r ^{(n, j1)} .r ^{(n, j2)} = 0; 1 L j1 j2 J;

r ^{(n, J)} + ... + r (n, j) + ... r ^{(n, 1)} = 1;

y ⁽ⁿ⁾ = y ^{(n, J)} r ^{(n, J)} + ... + y ^{(n, j)} r ^{(n, j)} + ... + y ^{(n, 1)} .r ^{(n, 1)} ; From this BOOT, a specific transfer signal, for example y ^{(n, j)} , can be represented by further transfer signals, by means of which a further BOOT can be formed to represent y ^{(n, j)} . From this further BOOT, a specific transfer signal can be represented by further transfer signals, by means of which a further BOOT can be formed, etc. The additional identifiers added in each case can be identified, for example, by a superscript in brackets, which indicates how many changes regarding the form of presentation. For example, if the form of representation according to i = 1,2, ... I;

changed, you get the following BOOTs.

The following primary BOOT (y ^(N) , ..., y ⁽ⁿ⁾ , ... y ⁽¹⁾ ) is used to represent the output signal a _;

To represent the transfer signal y ^{(n) of} this BOOT as an intermediate output signal, the following additional BOOT serves as a change of representation i = 1:

(y ^{n, J} ), ..., y ^{(n, j)} , ... y ^{(n, 1)} ); 1 = j ⁽¹⁾ = J ⁽¹⁾ ,

The transfer signal y ⁽ⁿ⁾ can be represented as follows:

y ⁽ⁿ⁾ = y ) .r ⁽ ) + ...

... + y ^{(n, j (1)} ) .r ^{(n, j (1)} ) + ...

... + y ^{(n, 1)} .r ^{(n, 1)} ; The following additional BOOT is used to represent the addition signal y (n ^, j ⁽¹⁾ ) of this BOOT as a change of representation i = 2 (y ( ^{n, j} ), ... y

^{(n, j (1), j (2)} ), ... y ^{(n, j (1), 1)} ); y ^{(n, j (1)} ) =

= y ^{(n, j (1)} , J. ⁽²⁾ ) .r ^{(n, j ()} , J ⁽²⁾ ) + ... ... + y ^{(n, j (1)} , ⁽²⁾ ) .r ^{(n j (2)} ) + ...

... + y ^{(n, j , 1)} .r ^{(n, j ), 1)} ; The following is used to represent the transfer signal y ^{(n, j (1), j (2)} ) as a further intermediate output signal

BOOT as a change of presentation i = 3:

(y ^{(n, j (1), j (2), J. (3))} , .. y ^{(n, j (}

1 ^{), j (2), j (3))} , .. y ^{(n, j}

( ^{1), j (2), 1))}

And so on. The following BOOT is provided as a change of representation i = I:

(

... ,) y ^{(n, j, ..., j), j)} , ....) j; 1 j ^(I) J ^(I) ; This BOOT is used to display a transfer signal from that BOOT of the display change i = I - 1:

y ^{(n, j (1), ... j (I-1))} = = y ^{(n, j , ... j ( ), j )}

.r ^{(n, j), ... j, j)} ; j ⁽¹⁾ = 1, ... J ^(I)

As an abbreviation for a multiple

 As with the summation, the OR operation can do this

Sum sign be used. The reconstruction ^signals for each of these changes of representation i should fulfill the following relations: r ^{(n, j, ..j1 )} .r ^{(n, j , .. j2 )} = 0; j1 ≠ j2 , ^{(), ... j (i 1) j (i))} = 1;

r ^{(n, j}

j ⁽ⁱ⁾ = 1, ... J ⁽ⁱ⁾ Each time the form of representation i changes, a different number J ⁽ⁱ⁾ of transfer signals can be defined. Each time the form of representation changes i, a number J ⁽ⁱ⁾ of further transfer signals should therefore be generated instead of one transfer signal. Overall, the number of all transfer signals to be generated thus increases by J ⁽ⁱ⁾ less that which is represented and replaced by the further transfer signals. The first time the form of representation changes, i.e. i = 1, the total number of transfer signals N - 1 + J ⁽¹⁾ must be generated. When the form of representation changes i = I, the number of total transfer signals to be generated is the same in this case:

N - I + J ⁽¹⁾ + J ⁽²⁾ + ... + J ⁽ⁱ⁾ + ... + J ^(I) ;

A further preferred embodiment of the invention is characterized in that each of the transfer signals of a primary tuple can be generated, corresponding to a respective further tuple of generated further transfer signals and further reconstruction signals. For example, in the event of a change in the form of representation, each primary transfer signal y ^{(n) can be made up} of a number N of transfer signals from a primary BOOT by an equal number J of others

Transfer signals y ^{(n, j)} ; j = 1, ... J; n = 1, ... N; are represented with respectively assigned further reconstruction signals r ^{(n, j)} ; j = 1, ... J; n = 1, ... N; Thus we have: y ^{(n, j)} = y ⁽ⁿ⁾ .r ^{(n, j)} + b ^{(n, j)} .s ^{(n, j)} ;

y ⁽ⁿ⁾ = y ^{(n, J)} .r ^{(n, J)} + ... + y ^{(n, 1)} .r ^{(n, 1)} ;

In this case, for all n = 1, ... N; so that a total of N times 3 of further transfer signals y ^{(n, j)} instead of all previous transfer signals y ⁽ⁱ⁾ of the number N is to be generated after this change of representation. For example, the other reconstruction signals for displaying one of the previous transfer signals can also be used unchanged for displaying the other previous transfer signals, so that the following applies:

r ^{(1, j)} = r ( ^{2, j)} = ... r ^{(N, j)} . A further change in the form of representation can take place in the manner explained. It can thus consist of a primary BOOT of transfer signals of a first one

Order another BOOT of further transfer signals of a second order, as it explains, are formed by a change of representation. A further change in the form of representation can be used to form a further BOOT of further transfer signals of a third order in the manner explained. And so on. The respective order i = 1, ... I of the BOOTs, as well as their transfer signals, reconstruction signals, scatter signals, arbitrary signals can be identified, for example, by a superscript and in

 Index indicated in parentheses, which should be added to the respective identifier of these signals. For the primary.

 Signals can, for example, have their characteristics n = 1, ... N;

formally replaced by j ⁽¹⁾ = 1, ... j ⁽¹⁾ ; J ⁽¹⁾ = N;

according to their first order, so that: y ^{(j (1))} = ar ^{(J (1))} + ^{b (j (1))} .s ^{(j (1))} ;

a = y ^{(J (1))} .r ^{(J (1))} + .. + ^{y (J (1,)} .r ^{(J (1))} + .. + y ⁽¹⁾ .r ⁽¹⁾ ;

For a second-order BOOT, the following should therefore apply: y ^{(j (1), j (2))} = y ^{(j (1))} r ^{(j (1), j (2))} + b ^{(j (1), j (2))} s ^{(j (1), j (2))} ;

For a BOOT of an order i, the following applies (j ⁽ⁱ⁾ = 1, ... J ⁽ⁱ⁾ ): y ^{(j (1)} , ... ^{j (i-1), j (i))} =

= y ^{(j (1), .. .j (i-1))} .r ^{(j (1), .. .j (i-1), j (i))} + + b ^{(j (1), ... j (i-1), j (i))} .s ^{(j (1), ... .j (i-1), j (i))} ;

The number of transfer signals of this BOOT is therefore equal to J ⁽¹⁾ times J ⁽²⁾ times ... times J ⁽ⁱ⁾ .

Another preferred embodiment of the invention is characterized by paired inverted reconstruction signals. Such reconstruction signals can be generated more easily. In addition, there is an advantageous clarity of the concept. A further preferred embodiment of the invention is characterized by inverted scatter signals assigned to the reconstruction signals. For example, the scatter signals can be generated more easily in this way. Further advantages result in particular in the case of suitably predetermined arbitrary signals. This will be explained in the following. For a BOOT ₂ , for example, both arbitrary signals are always specified according to logical ONE.

y ⁽¹⁾ = ar + b ⁽¹⁾ . = ar + ; y ⁽²⁾ = a. + b ⁽²⁾ .r = a. + r; In this case, the reconstruction signals are not required to generate the output signal, since the output signal can be generated as an AND operation of the two transfer points. y ⁽¹⁾ . y ⁽²⁾ = (ar + ). (a. + r) = a. + ar = a;

 In addition, for the two transfer signals is theirs

OR operation can always be checked according to ONE, for example for error detection:

y ⁽¹⁾ + y ⁽²⁾ = ar + + a. + r = a + 1 = 1;

 On the other hand, for example, the two arbitrary signals according to the inverted intermediate output signals

given, you get the following BOAT:

y ⁽¹⁾ = ar + b ⁽¹⁾ . = ar + = a ⊕ ;

y ⁽²⁾ = a. + b ⁽²⁾ .r = a. + .r = a ⊕ r; In this case, the parity can be checked for the two transfer signals, for example for error detection: y ⁽¹⁾ = ⁽²⁾ ; y ⁽¹⁾ ⊕ y ⁽²⁾ = 1; On the other hand, if, for example, the two arbitrary signals are always given a logical ZERO, y ⁽¹⁾ = ar is obtained; y ⁽²⁾ = a. ; In this case too, the generation of

Output signals do not require the reconstruction signals, since the output signal can be generated as an OR operation of the two transfer signals y ⁽¹⁾ + y ⁽²⁾ = ar + a. = a; The output signal can also be generated without reconstruction signals as an EXOR combination of the two transfer signals

y ⁽¹⁾ ⊕ y ⁽²⁾ = ar ( + r) + ( a + ) .a. = ar + a. = a;

In addition, for the two transfer signals is theirs

 AND operation can always be checked according to ZERO, for example for error detection.

A further preferred embodiment of the invention is characterized by at least one arbitrary signal, which is the logical combination of the output signal to be assigned, but from at least one inverted input signal

equivalent. This results in further advantages, which are to be shown using another BOOT, in which, for example, the same arbitrary signals are used. b ⁽¹⁾ = b ⁽²⁾ = b = B (x ₂ , x ₁ ) = A ( ₂ , ₁ );

y ⁽¹⁾ = ar + b. ; y ⁽²⁾ = a. + br;

y ⁽¹⁾ = (y , y , y , y ); y ⁽²⁾ =

 By inverting the input signals, the order of the signal values according to the truth table in the number tuple

 vice versa.

A (x ₂ , x ₁ ) = (a ₄ , a ₃ , a ₂ , a ₁ ) = a;

A ( ₂ , ₁ ) = (a ₁ , a ₂ , a ₃ , a ₄ ) = (b ₄ , b ₃ , b ₂ , b ₁ ) = b;

r = (r ₄ , r ₃ , r ₂ , r ₁ ); = y ⁽¹⁾ = (a ₄ , a ₃ , a ₂ , a ₁ ) (r ₄ , r ₃ , r ₂ , r ₁ ) + (a ₁ , a ₂ , a ₃ , a ₄ ) ( r ₄ , r ₃ , r ₂ , r ₁ ) y ⁽²⁾ = (a ₄ , a ₃ , a ₂ , a ₁ ) (r ₄ , ₃ , _{2 1} ) + (a ₁ , a ₂ , a ₃ , a ₄ ) (r ₄ , r ₃ , r ₂ , r ₁ ) y = a ₄ .r ₄ + a _{1 4} ; y ₃ = a ₃ .r ₃ + a ₂ . ₃ ;

y ₂ = a ₂ .r ₂ + a ₃ . ₂ ; y ₁ = a ₁ .r ₁ + a ₄ . ₁ ;

y ₄ = a ₄ . ₄ + a ₁ .r ₄ ; y ₃ = a ₃ . ₃ + a ₂ .r ₃ ;

 = a

_{2nd 2} + a ₃ .r ₂ ; ₁ = a _{1st 1} + a ₄ .r ₁ ;

For example, in the case of a special predetermined reconstruction signal, for which the following applies r ₁ = r ₄ ; r ₂ = r ₃ ;

r = (r ₁ , r ₂ , r ₂ , r ₁ ); this reconstruction signal can only be one of the following four logical signals:

(0, 0, 0, 0) = 0 _d ; for r ₁ = r ₂ = 0;

(0, 1, 1, 0) = 6 _d ; for r ₁ = 0; r ₂ = 1;

(1, 0, 0, 1) - 9 _d ; for r ₁ = 1; r ₂ = 0;

(1, 1, 1, 1) = 15 _d ; for r ₁ = r ₂ = 1;

 In this case, the following transfer signal values are obtained

.r

1 + a ₁ .r ₁ ; y ₃ = a

₃ .r ₂ + a ₂ .

a ₂ .r ₂ + a ₃ . ₂ ; y ₁ = a ₁ .r ₁ + a _{4 1} ;

= a

4.r ₁ + a ₁ .r ₁ ; y ₃ = a

_3rd a ₂ .r ₂ ;

₂ = a ₂ . ₂ + a ₃ .r ₂ ; y ₁ = a + a ₄ .r ₁ ;

 The following applies

 "y

y ⁽¹⁾ = Y ⁽¹⁾ (x ₂ , x ₁ ) = Y ⁽²⁾

 With reconstruction signals predefined in this way, the transfer signals can therefore be generated more easily. This is useful.

Another preferred embodiment of the invention is characterized in that one of the reconstruction signals is equal to one of the input signals. \

This results in further advantages, for example to be explained for r = x ₁ and a = A (x ₂ , x ₁ )

y ⁽¹⁾ = ax ₁ + b ⁽¹⁾ . ₁ ;

y ⁽²⁾ = a. ₁ + b ⁽²⁾ .x ₁ ;

y ⁽¹⁾ = (a ₄ , a ₃ , a ₂ , a ₁ ) .3 _d + .12 _d ;

y ⁽²⁾ = (a ₄ , a ₃ , a ₂ , a ₁ ) .12 _{d +} ( .3 _d ; y ⁽¹⁾ = ^, a ₂ , a ₁ ); y ⁽²⁾ = (a ₄ , a ₃ ,

If arbitrary signals are now specified, for example, as follows b ⁽¹⁾ = b ⁽²⁾ = b = A ( ) = (a ₁ , a ₂ , a ₃ , a ₄ );

so follows

y ⁽¹⁾ = (a ₁ , a ₂ , a ₂ , a ₁ ); y ⁽²⁾ = (a ₄ , a ₃ , a ₃ , a ₄ ); Each transfer signal can only be one of four signals

y ⁽¹⁾ from (0 _d , 6 _d , 9 _d , 15 _d ); y ⁽²⁾ from (0 _d , 6 _d , 9 _d , 15 _d ); The output signal is generated in accordance with

a = y ⁽¹⁾ .x ₁ + y ⁽²⁾ . ₁ ; It is therefore sufficient to generate only four different signals as intermediate signals, which in this case are to be marked with Roman numerals:

y ^I = 0 _d ; y ^II = 6 _d ; y ^III = 9 _d ; y ^IV = 15 _d ;

From these four transfer signals, y ⁽¹⁾ and y ^{(2) are} to be selected for the generation of the output signal. This can be done, for example, by means of a selection switching mechanism. For programmable logic switchgear (PLA's), for example, this can result in simplifications for the architecture and the above-mentioned concept. For example, not all different output signals need to be generated as intermediate signals. For example, it is sufficient to generate those four intermediate signals and use them to select the respective transfer signals for the BOOT. The output signal can be generated from these selected transfer signals by means of the reconstruction signals. It can be specified which two

Intermediate signals are to be selected as transfer signals for a given logical combination (a ₄ , a ₃ , a ₂ , a ₁ ) in order to generate the output signal. The transfer signal y ⁽¹⁾ is to be selected as follows

y ⁽¹⁾

(0 _d , 9 _d , 6 _d , 15 _d , 0 _d , 9 _d , 6 _d , 15 _d , 0 _d , 9 _d , 6 _d , 15 _d , 0 _d , 9 _d , 6 _d , 15 _d )

according to m + 1 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16; Depending on m + 1, the in brackets

lined up signals according to a counting the signal concerned. The transfer signal y ⁽²⁾ is to be selected as follows

y ⁽²⁾

(0 _d , 0 _d , 0 _d , 0 _d , 6 _d , 6 _d , 6 _d , 6 _d , 9 _d , 9 _d , 9 _d , 9 _d , 9 _d , 15 _d , 15 _d , 15 _d , 15 _d )

according to m + 1 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16;

These two transfer signals can also be selected as a BOOT of logical signals (y ⁽¹⁾ , y ⁽¹⁾ )

(y ⁽¹⁾ , y ⁽²⁾ ) from ((0 _d , 0 _d ), (9 _d , 0 _d ), (6 _d , 0 _d ), (15 _d , 0 _d ), (0 _d , 6 _d ), (9 _d , 6 _d ), (6 _d , 6 _d ), (15 _d , 6 _d ), (0 _d , 9 _d ), (9 _d , 9 _d ), (6 _d , 9 _d ) , (15 _d , 9 _d ), (0 _d , 15 _d ), (9 _d , 15 _d ), (6 _d , 15 _d ), (15 _d , 15 _d )) according to m + 1 = 1.2, 3,4,5,6,7,8,9,10,11,12,13,14,15,16;

Depending on m + 1, from the BOOTs of logical signals lined up in brackets, the BOOT of logical signals concerned is taken over in accordance with a payment.

For example, one of four processed intermediate signals can be generated by means of a selection circuit, which is activated depending on m, for example

0, x ₁ ⊕x ₂ , x ₁ ⊕ ₂ , 1; as the respective handover signal

to be selected. This use case for K = 2; N = 2; r ⁽¹⁾ = ⁽¹⁾ = s ⁽¹⁾ = x ₁ = 3

_d ; r ⁽²⁾ = ⁽¹⁾ = s ⁽¹⁾ =

₁ = 12 _d ; b ⁽¹⁾ = b ⁽²⁾ = A ^(m) ( ₂ , ₁ ); a = A ^(m) (x ₂ , x ₁ ); is in the

shown in Table 5 below.

Table 5

For example, in the application case K = 2; N = 2;

r ⁽¹⁾ = ⁽²⁾ = s ⁽²⁾ = x ₂ = 5 _d ; r ⁽²⁾ = ⁽¹⁾ = s ⁽¹⁾ = ₂ =

10 _d ; b ⁽¹⁾ = b ⁽²⁾ = A ^(m) ( ₁ ); a = A ^(m) (x ₂ , x ₁ );

a = (a ₄ , a ₃ , a ₂ , a ₁ ); b = (a ₁ , a ₂ , a ₃ , a ₄ ); a = y ⁽¹⁾ x ₂ + y ⁽²⁾ ₂ ; y ⁽¹⁾ = ax ₂ + b. ₂ = (a ₁ , a ₃ , a ₃ , a ₁ );

y ⁽²⁾ = a. ₂ + bx ₂ = (a ₄ , a ₂ , a ₂ , a ₄ );

(y ⁽¹⁾ , y ⁽²⁾ ) from ((0 _d , 0 _d ), (9 _d , 0 _d ), (0 _d , 6 _d ), (9 _d , 6 _d ),

(6 _d , 0 _d ), (15 _d , 0 _d ), (6 _d , 6 _d ), (15 _d , 6 _d ), (0 _d , 9 _d ), (9 _d , 9 _d ), (0 _d , 15 _d ), (9 _d , 15 _d ), (6 _d , 9 _d ), (15 _d , 9 _d ), (6 _d , 15 _d ), (15 _d , 15 _d )) according to m + 1 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16;

 Depending on m, the transfer signals can be one of four

Intermediate signals 0, x ₁ ⊕x ₂ , x ₁ ⊕ ₂ , 1; to be selected. For example, in the application case K = 2; N = 2;

r ⁽¹⁾ = ⁽²⁾ = s ⁽²⁾ = x ₁ = r ⁽²⁾ = ⁽¹⁾ = s ⁽¹⁾ = ₁ =

12 _d ; b ⁽¹⁾ = b ⁽²⁾ = A ^(m) (x ₂ , ₁ ); a = A ^(m) (x ₂ , x ₁ );

a = (a ₄ , a ₃ , a ₂ , a ₁ ); b = (a ₂ , a ₁ , a ₄ , a ₃ ); a = y ⁽¹⁾ x ₁ + y ⁽²⁾

₁ ; y ⁽¹⁾ = ax ₁ + b. ₁ = (a ₂ , a ₁ , a ₂ , a ₁ );

y ⁽²⁾ a. ₁ + bx ₁ = (a ₄ , a ₃ , a ₄ , a ₃ );

(y ⁽¹⁾ , y ⁽²⁾ ) from ((0 _d , 0 _d ), (5 _d , 0 _d ), (10 _d , 0 _d ), (15 _d , 5 _d ), (0 _d , 5 _d ), (5 _d , 5 _d ), (10 _d , 5 _d ), (15 _d , 5 _d ), (0 _d , 10 _d ), (5 _d , 10 _d ), (10 _d , 10 _d ) , (15 _d , 10 _d ), (0 _d , 15 _d ), (5 _d , 15 _d ), (10 _d , 15 _d ), (15 _d , 15 _d )) according to m + 1 = 1.2, 3,4,5,6,7,8,9,10,11,12,13,14,15,16;

Depending on m, the transfer signals can be one of four

Intermediate signals 0, x ₂ , ₂ , 1; be selected.

For example, in the application case K = 2; N = 2;

r ⁽¹⁾ = ⁽²⁾ = s ⁽²⁾ = x ₂ = 5 _d ; r ⁽²⁾ = ⁽¹⁾ = s ⁽¹⁾ =

₂ = 10 _d ; b ⁽¹⁾ = b ⁽²⁾ = A ^(m) ( x ₂ , x ₁ ); a = A ^(m) (x ₂ , x ₁ );

a = (a ₄ , a ₃ , a ₂ , a ₁ ); b = (a ₃ , a ₄ , a ₁ , a ₂ ); a = y ⁽¹⁾ x ₂ + y ⁽²⁾

₂ ; y ⁽¹⁾ = ax ₂ + b. ₂ = (a ₃ , a ₃ , a ₁ , a ₁ );

y ⁽²⁾ = a. ₂ + bx ₂ = (a ₄ , a ₄ , a ₂ , a ₂ );

(y ⁽¹⁾ , y ⁽²⁾ ) from ((0 _d , 0 _d ), (3 _d , 0 _d ), (0 _d , 3 _d ), (3 _d , 3 _d ), (12 _d , 0 _d ), (15 _d , 0 _d ), (12 _d , 3 _d ), (15 _d , 3 _d ), (0 _d , 12 _d ), (3 _d , 12 _d ),

(0 _d , 15 _d ), (3 _d , 15 _d ), (12 _d , 12 _d ), (3 _d , 15 _d ), (12 _d , 15 _d ), (15 _d , 15 _d )) according to m +1 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16;

 Depending on m, the transfer signals can be one of four

Intermediate signals 0, x ₁ , ₂ , 1; to be selected. For example, in the case of a higher number of input signals, BOOTs of higher orders can each

Associated pair of reconstruction signals, the first of which is equal to one of the input signals x _i , and the second of which is the same but inverted input signal, ie is equal to x _i . r ^{(j ())} from (x _i , x ₁ ) according to j ⁽ⁱ⁾ = 1.2;

For example, the scatter signals can be predefined in accordance with the respectively assigned inverted reconstruction signals. s

 For example, the arbitrary signals can in each case according to the respectively assigned signal link to form the

respective intermediate output signals, however, can be predetermined from, for example, all inverted input signals.

b ⁽¹⁾ = b ⁽²⁾ = A ( _{K 1}

b ⁾ (x _K , ... x ₁ );

So that the following applies

y ⁽¹⁾ = ax ₁ + A ( _K , ..., x ₁ ). ₁ ;

y ⁽²⁾ = a. ₁ + A ( x _K , ..., ₁ ). x ₁ ; y ^(1,1) = y ⁽¹⁾ .x ₂ + Y ⁽¹⁾ ( x _K , ..., ₁ ). ₂ ; y ^(1,2) = y ⁽¹⁾ . ₂ + Y ⁽¹⁾ x _K , ..., ₁ ) .x ₂ ; y ^(2,1) = y ⁽²⁾ .x ₂ + Y ⁽²⁾ (x _K , ..., ₁ ). ₂ ; y ^(2,2) = y ⁽²⁾ . x ₂ + Y ⁽²⁾ ( _K , ..., ₁ ) .x ₂ ;

^; ( _K , .. ₁ ). _i ; ) ( _K , ..

₁ ) .x _i ; ( _K , .., ₁ ). _K-1 ;

 ) =

 K

(x _K , ..,

x ₁ ) .x _K-1

For example, according to Table 6 below

logical links to be specified can be represented. The logical values of the output signal can be combined depending on the input signals x ₁ to x _K on the one hand into a tuple, which is shown in Table 6, and

on the other hand to a binary number, which is identified as such by a subscript "b", _b ; whose numerical value can be represented as a decimal number equal to m, ie equal to (m) _d , which is identified as a decimal number by a subscript "d". The number of all different combinations of logical signal values of the input signals x ₁ to x _K is therefore equal to 2 ^K , so that the following applies: 1 + L = 2 ^K ; The number of all tuples to be listed, which are shown in Table 6, is therefore equal to 2 ^{1 + L} , so that the following applies: 0 m M; For

M = 2 ^{1 + L} - 1;

Table 6

The reconstruction signals as well as their logical combination, which in the case under consideration is equal to one of the Input signals or an inverted input signal can be represented as a decimal number. x _k = (; x _k = (

1 ;

 Within those marked with a subscript "d"

Parentheses are always used when calculating numbers

To carry out summations, multiplications and exponentiations according to the known calculation rules for numbers.

The primary defined transfer signals are therefore t = 1, .., T1, T2, .., T; T1 = 2 ^K-1 ; T2 = 2 ^K-1 ; T = 2 ^K ; y ⁽¹⁾ =

y ⁽²⁾ =

The secondary defined transfer signals are therefore t = 1, .., T11, T12, .. T1, T2, .., T21, T22, .., T;

T = 2 ^K ; T11 = 2 ^K-2 -1; T12 = 2 ^K-2 ; T1 = 2 ^K-1 -1; T2 = 2 ^K-1 ;

T21 = T2 + T11; T22 = T2 + T12; y ^(1,1) =

y ^(1,2) =

, ¹ = (, 2)

For this second-order BOOT, the output signal can be generated as follows: a = y ^(1,1) x ₁ x ₂ + y ^(1,2) x ₁ x ₂ + y ^(2.1) x ₁ x ₂ + y ^(2.2) x =

= (y ^(1.1) x ₁ + y ^(2.1 ₁ ) x ₂ + (y ^(1.2) x ₁ + y ^(2.2) ₁ ) x ₂ = = (y ^(1,1) (2

-1) _d + y ^{(2 '1)} ((2 ^{2K 1} -1) 2 ) _d ) x ₂ + (y ^(1,2) (2 ^2K-1 -1) _d ^{2K-1 2K-1} x

 From this one recognizes the possibility of forming signals which have symmetrical peculiarities regarding parts of their truth table. It can be seen that a variety of such symmetrical

 Peculiarities in other applications can be achieved, for example, in that a different sequence can be provided for each of which is used as a reconstruction signal

 Input signals. Likewise, the signal linkage assigned as an intermediate output signal can be used, for example, to form the arbitrary signals, but not all of them inverted

 Input signals, but only be provided from a few inversions of the input signals, so that also

 With regard to the number and distribution of inverted and non-inverted input signals for the respectively assigned signal combination, a large variety results for the derivable symmetrical peculiarities of transfer signals.

Likewise, in order to form the arbitrary signals in the signal linkage assigned as an intermediate output signal, in addition to any inversions of input signals, for example, an interchange in a sequence of input signals as variables for function formation within the list of variables can also be provided. Likewise, instead of at least one, for example the variables have a fixed logic value, for example logic 0 or logic 1. Likewise can

for example, a logical function of at least one of the variables can also be provided instead of at least one of the variables. Function formation from several input signals is also possible to form the reconstruction signals. In this way, the transfer signals can additionally facilitate and support the achievement of symmetrical peculiarities for the truth tables. A large variety can thus be achieved for symmetrical peculiarities of transfer signals. The advantages that can be derived from this will be explained in more detail on the basis of the case considered above.

In the previously considered case, the following BOOT is new

Transfer signals definable.

From this follows for the generation of the output signal

 The number tuples used in this definition can be combined from smaller number tuples as follows:

= A ^(m) (x _K , ..., x ₃ , 0.0) = a ^I ; = A ^(m) (x _K , ..., x ₃ , 1.0); = A ^(m) (x _K , ..., x ₃ , 0.1); = A ^(m) (x _K , ..., x ₃ , 1.1) = a ^IV ; = A ^(m) (x _K , ..., x ₃ , 0.0); = A ^(m) (x _K , ..., x ₃ , 0.1) = a ^III ;

 After a reshaping, the transfer signals can be represented using these smaller number tuples, which are to be named using Roman numerals.

A further simplification of the representation of the number tuples is obtained with a BOOT, the definition of which can preferably be found on the basis of the output signal.

( ^{1,1, .., 1,1)} x ₁

a = y ^{(1,1, .., 1,2)} x ₁ x ₂ ..... x _K-3 x _K-2 +

+ yx ₂ ..... x _K-3 x _K-2 +

( ^{1.1, .., 2.1)} x ₁

+ y ^{(1,1, .., 2,2)} x ₁ x ₂ ..... x _K-3 x _K-2 +

+ yx ₂ ..... x _{K-3 K-2} +

( ^{1,2, .., 1,1)} x ₁

+ y ₂ ..... x _K-3 x _K-2 +

( ^{1,2, .., 2,2)} x ₁

+ yx ₂ ..... x _K-3 x _K-2 +

( ^{2.1, .., 1.1)} x ₁

+ yx ₂ ..... x _K-3 x _K-2 +

( ^{2.1, .., 2.2)} x ₁

+ yx ₂ ..... _{K-3 K-2} +

( ^{2.2, .., 1.1)} x

+ y x ₂ ..... x _K-3 x _K-2 +

( ^{2.2, .., 2.2)} x

+ y ₂ ..... x _K-3 x _K-2 ;

 The order of the links is reordered

Links of x _K-2 on the one hand and

_K-2 on the other hand. a = ^{(1,1, .., 1,1)} x ₁

= (yx ₂ ..... x _K-3 +

( ^{1.1, .., 2.1)} x ₁

+ yx ₂ ..... x _{K -3} + ( ^{2.2, .., 1.1)} x ₁

₊ y ..... x _K-3 +

( ^{2.2, .., 2.1)} x ₁

yx ₂ ..... x _K-3 ) .x _K-2 +

+ ^{(1.1, .., 1.2)} x ₁

+ (y ^{(1,1, .., 2,2)} x ₁ x ₂ ..... x _K-3 +

+ yx ₂ ..... x _-3 +

( ^{2.2, .., 1.2)} x ₁

+ y ..... x _K-3 +

( ^{2.2, .., 2.2)} x ₁

+ y x ..... x _K-3 ) .x _K-2 ; New transfer signals can be defined as follows ^* = (y ^{(1,1, .., 1,1)} x ₁ x ₂ ... x _K-3 + ...

... + y ^{(2,2, ..} ' ² ' ¹⁾ ₂ ... _K-3 ) .x _K-2 ; ^* = (y ^{(1,1, .., 1,2)} x ₁ x ₂ ... x _K-3 + ...

... + y ^{(2,2, ..} ' ² ' ²⁾ ... _K-3 ). _K-2

From this follows for the generation of the output signal _2nd

It can be seen that the combined AND operations of the input variables x ₁ to x _K-3 each address four numbers of the number tuple. These numbers are each formed, for example, according to the truth table, by varying the input signal values for the input signals x _K-1 and x _K , so that the respective group of four numbers of the number tuple can be recognized as a power of 16 when represented as a dual number. This also applies to the decimal display. = y ^{(1,1, .., 1,1)} .

... + y ^{(........, 1)} .

... + y ^{(2.2, .., 2.1)} .

y ^{(2) R *} = y ^{(1,1, .., 1,2)} .

... + y ^{(........, 2)} .

... + y ^{(2.2, .., 2.2)} . _d ; j = 1, ..., J; J = ^2K-3 ; Or in a more simplified form y ^{(1) R *} = y ^{(1, .., 1,1)} . (15. (16) ⁰ ) _d + ...

... + y ^{(......, 1)} . (15. (16) ^2j-2 ) _d + ...

... + y ^{(2, .., 2} ' ¹⁾ . (15. (16) ^2J-2 ) _d ; y ^{(1) R *} = y ^{(1, .., 1,2)} . (15. (16) ¹ ) _d + ...

... + y ^{(......, 2)} . (15. (16) ^2j-1 ) _d + ...

... + y ^{(2, .., 2,2)} . (15. (16) ^2J-1 ) _d ;

It can be seen that tuples of numbers of a reduced betrayal of values can be introduced, which can be distinguished, for example, by means of Roman numbers. There should be a symbol

Zi can be defined as a Roman number, which can be obtained explicitly in the following way

Zi from (I, II, III, IV, V, VI, VII, VIII, IX, X, XI, ...) according to i = 1,2,3,4,5,6,7,8,9, 10.11, ...

 With this symbol the number tuples can be given in a simplified way

y ^Zi from (0 _d , 1 _d , 2 _d , 3 _d , 4 _d , 5 _d , 6 _d ,... 14 _d , 15 _d )

 This can also be represented as a tuple

y ^Zi = = (y ^Zi ) _d = Y ^Zi (x _K , x _K-1 )

The transfer signals are accordingly, j = 1, ... J; J = ^2K-3 ; y = ((y ^Z1 ) _d . (16) ⁰ ) _d + ((y ^Z3 ) _d . (16) ² ) _d + ...

... + ((y ^Z2J-1 ) _d . (16) ^2j-2 ) _d + ...

... + ((y ^Z2J-1 ) _d . (16) ^2j-2 ) _d ; = ((y ^Z2 ) _d . (16) ¹ ) _d + ((y ^Z4 ) _d . (16) ³ ) _d + ...

... + ((y ^Z2J-1 ) _d . (16) ^2j-1 ) _d + ...

... + ((y ^Z2J-1 ) _d . (16) ^2j-1 ) _d ; A comparison with the truth table for the logical combination of the output signal to be specified from the input signals in a form of representation as a number tuple

a = A (x _K , ..., x ₁ ) = (a _{1 + M} , a _M , a _M-1 , a _M-2 , a _M-3 , a _M-4 , a _M-5 , a _M-6 , ...

..., a ₇ , a ₆ , a ₅ , a ₄ , a ₃ , a ₂ , a ₁ ) = \ y

shows that this BOOT of transfer signals could have been primarily defined without going through the new definition. y ^{(1) R *} = (((y ^Z2J-1 ) _d (16) ^2J-2 ) _d + ... + ((y ^Z1 ) _d (16) ⁰ ) _d ) .x _K-2 y ^{(1 ) R *} = (((y ^Z2J ) _d (16) ^2J-1 ) d + ... + ((y ^Z2 ) d (16) ¹ ) _d ) .x _K-2

In this case, arbitrary signals and scatter signals are always logically ZERO. It is not necessary. Each BOOT can always be redefined using reconstruction signals, arbitrary signals and scatter signals. Likewise, every BOOT can also be viewed as a primarily defined BOOT. A BOCT can also be expanded several times, for example. The resulting advantages will be explained below. Based on the transfer signals already explained = x _K , _{K 1} )

= ((y ^Z2J-1 ) _d (16) ^Z2J-2 ) _d + ... + ((y ^Z3 ) _d (16) ² ) _d + (y ^Z1 ) _d ; y ^{(1) R *} = (x _K , x _K-1 ) =

= ((y ^Z2J ) _d (16) ^2J-1 ) _d + ... + ((y ^ZA ) _d (16) ³ ) _d + ((y ^Z2 ) _d .16) _d y ^Zi = Y ^Zi (x _K , x _K-1 ) = (

this BOOT can be redefined as follows

Based on this, further transfer signals are defined

 It is preferably redefined based on the output signal

 And you get the following extremely surprising result, which can be better recognized by redefining number tuples from a reduced set of values.

i = 1, ..., I; I = 2J; J = ^2K-3 ; y ^RZi from (0 _d , 6 _d , 9 _d , 15 _d );

y ^SZi from (0 _d , 6 _d , 9 _d , 15 _d );

y ^{(1) RRR *} = (((y ^RZI ) _d (16) ^I-1 ) _d + ... + ((y ^RZi ) _d (16) ^i-1 ) _d + ... ... + ((y ^R22 ) d ^{(16) 1} ) _d + ((y ^RZ1 ) _d ^{(16) 0)} d) _d ;

 *

= (((y ^SZI ) _d (16) ^I-1 ) _d + ... + ((y ^SZi ) _d (16) ^i-1 ) _d + ... ... + ((y ^SZ2 ) d ^{( 16) 1} ) _d + ((y ^SZ1 ) _d ^{(16) 0)} d) _d ;

 In this case, only four transfer signals have to be generated for the reduced number of four links between two input signals. For each tuple of numbers, one of these four transfer signals is to be selected by means of a selection circuit, for example. These selected transfer signals can be linked in the manner already explained with the assigned reconstruction signals to generate the output signal. As a result, all logical combinations of the input signals are particularly simple using the selection circuit

Can be generated as output signals.

a = y ^RZ1 .x ₁ .x ₂ . ... .x _K-3 .x _K-2 .x _K-1 +

+ y ^SZ1 .x ₁ .x ₂ . ... .x _K-3 .x _K-2 .x _K-1 +

+ y ^RZ2 .x ₁ .x ₂ . ... .x _K-3 .x _K-2 .x _K-1 +

+ y ^SZ2 .x ₁ .x ₂ . ... .x _K-3 .x _K-2 .x _K-1 +

+ y ^RZ3 .x ₁ .x ₂ . ... .x _K-3 .x _K-2 .x _K-1 +

+ y ^SZ3 .x ₁ .x ₂ . ... .x _{K -3} .x _K-2 .x _K-1 +

+ y ^RZI-1 . _2nd ... .x _K-3 .x _K-2 .x _K-1 +

+ y ^SZI-1 .x ₁ x ₂ . ... .x _K-3 .x _K-2 .x _K-1 +

+ y ^RZI .x ₁ x ₂ . ... .x _K-3 .x _K-2 .x _K-1 +

+ y ^SZI . x ₁ x ₂ . ... .x _{K -3} .x _K-2 .x _K-1 + y ^RZi = Y ^RZi (x _K , x _K-1 ) from (0d, 6d, 9d, 15d);

y ^SZi = Y ^SZi (x _K , x _K-1 ) from (0d, 6d, 9d, 15d); Another preferred embodiment of the invention is characterized in that one of the reconstruction signals is equal to an EXOR combination of at least two input signals. This results, for example, in the case of a specific selection of arbitrary signals and scatter signals

special advantages, which will be explained in more detail below, for example for a BOOT with two input signals. y ⁽¹⁾ = a. (x ₁ ⊕ x ₂ ) + b ⁽¹⁾ . (x ₁ ⊕ ₂ );

y ⁽²⁾ = a. (x ₁ ⊕ ₂ ) + b ⁽¹⁾ . (X ₁ ⊕ x ₂ ); y ⁽¹⁾ = (a ₄ , a ₃ , a ₂ , a ₁ ) .6 _d + y ⁽²⁾ = (a ₄ , a ₃ , a ₂ , a ₁ ) .9 _d +

y ⁽¹⁾ =, a ₃ , a ₂

y ⁽²⁾ = (a ₄ ,)

;

If the arbitrary signal is specified, for example, that b ⁽¹⁾ = b ⁽²⁾ = b = A (x ₂ , x ₁ ) = (a ₃ , a ₄ , a ₁ , a ₂ ); so follows

y ⁽¹⁾ = (a ₃ , a ₃ , a ₂ , a ₂ );

y ⁽²⁾ = (a ₄ , a ₄ , a ₁ , a ₁ );

and one recognizes that each transfer signal can only take up a limited number of number tuples.

y ⁽¹⁾ from (0 _d , 3 _d , 12 _d , 15 _d );

y ⁽²⁾ from (0 _d , 3 _d , 12 _d , 15 _d );

 The output signal is generated in accordance with

a = y ⁽¹⁾ . (x ₁ ⊕ x ₂ ) + y ⁽²⁾ . (x ₁ ⊕ ₂ );

It is therefore sufficient to generate four different intermediate signals: y ^I = 0 _d ; y ^II = 3 _d ; y ^III = 12 _d ; y ^IV = 15 _d ;

 These four intermediate signals are used to generate the

Select output signals y ⁽¹⁾ and y ⁽²⁾ . This can be done for example by means of a selection circuit. This can be used, for example, for programmable logic

 Switchgear (PLA's) result in significant simplifications for the architecture and the concept. Table 7 is intended to show which two transfer signals each for a predeterminable logical

Linkage of both input signals to generate the output signal must be selected. Table 7

The transfer signals y ⁽¹⁾ and y ⁽²⁾ are to be selected as follows

y ⁽¹⁾

(0 _d , 0 _d , 3 _d , 3 _d , 12 _d , 12 _d , 15 _d , 15 _d , 0 _d , 0 _d , 3 _d , 3 _d , 12 _d , 12 _d , 15 _d , 15 _d ) according to m + 1 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16; y ⁽²⁾

(0 _d , 3 _d , 0 _d , 3 _d , 0 _d , 3 _d , 0 _d , 3 _d , 12 _d , 15 _d , 12 _d , 15 _d , 12 _d , 15 _d , 12 _d , 15d) according to m +1 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16; Depending on m + 1, the in brackets

 lined up signals according to a payment the relevant

Signal accepted. These two transfer signals can also be represented as a BOOT of logical signals (y ⁽¹⁾ , y ⁽²⁾ ) and selected:

(y ⁽¹⁾ , y ⁽²⁾ )

((0 _d , 0 _d ), (0 _d , 3 _d ), (3 _d , 0 _d ), (3 _d , 3 _d ), (12 _d , 0 _d ), 12 _d , 3 _d ),

(15 _d , 0 _d ), (15 _d , 3 _d ), 0 _d , 12 _d ), (0 _d , 15 _d ), (3 _d , 12 _d ), (3 _d , 15 _d ), (12 _d , 12 _d ), (12 _d , 15 _d ), (15 _d , 12 _d ), (15 _d , 15 _d ))

 according to m + 1 = 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16;

With a higher number of input signals, the following BOOT of a higher order can be defined, for example. ; out

((x _i ⊕x _{i + 1} ), (x _i ⊕ _{i + 1} ))

according to ....... j ⁽ⁱ⁾ = 1.2; i = 1, .., K-1; j ⁽ⁱ⁾ = 1.2;

0 m 2 ^K-1 -1; j ^{(i) *} = mod ₂ (j ⁽ⁱ⁾ +1);

(x _K , .., x _{i +1} , x _i , x _{i -1} , .., x ₁ ) .r ( (x _K , .., x _{i +1} , x _i , x _{i -1} , .., x ₁ ). r

In this case too, as always, the BOOT can be redefined, for example for locating, converting, modifying or as a starting point for extensions. According to the invention, in particular through the definition of transfer signals, novel circuits, circuit architectures, circuit concepts, etc., can be found and checked. Logical combinations of, in particular, many input signals are thereby significantly facilitated. A further preferred embodiment of the invention is characterized in that the transfer signals are generated at one location and are transferred to another location where the output signal is generated from the transfer signals. Reconstruction signals may be required to generate the output signal. In some use cases this can

Output signal can also be generated without a reconstruction signal and solely by linking transfer signals. Instead of reconstruction signals that have already been generated, those input signals that are required to generate these reconstruction signals can also be transmitted. Depending on the application, the reconstruction signals or some of the input signals or only some of the reconstruction signals and some of the input signals can therefore be provided during the transmission in addition to the required transfer signals. For example, in the case of encryption or similar applications, it may be necessary, for example from confidentiality requirements, input signals and

Not to pass on reconstruction signals, so that only BOOTs from transfer signals arrive at the decoding. For example, there may be a frequent change in the generation of the BOOTs, that is to say with regard to input signals, and their links for the formation of reconstruction signals, scatter signals, arbitrary signals. A great variety can be achieved through this change. When decoding, the primary coding is to be used when generating the passed on

 Transfer signals to be known. If this primary coating is largely unknown, i.e. the one used

 changing BOOT generation is not known, especially with its input signals and reconstruction signals, successful decoding can be significantly more difficult. This BOOT generation can be agreed, for example, by means of a so-called second information channel. For example, a generator can generate a number of

Input signal values must be agreed so that their change can be determined in accordance with the agreement. Logical links for the formation of reconstruction signals should be agreed with this generator for input signals, so that these can be determined in particular during the decoding. When coding, scatter signals assigned to these reconstruction signals are to be generated, so that the reconstruction signals and the scatter signals always fulfill the relations according to the invention. In addition, arbitrary signals can be generated, for example, from the input signals. The signal to be encrypted is to be used as the output signal to be specified, for which the following BOOT is to be generated during coding: y ⁽ⁿ⁾ = a. r ⁽ⁿ⁾ + b ⁽ⁿ⁾ . s ⁽ⁿ⁾ ; n = 1, 2, ... N,

As agreed, the reconstruction signals are to be generated during the decoding. For example, the

Agreed generator generate input signal values from which these reconstruction signals can be formed according to agreed, for example, changing logic operations. These can be used to decode the BOOT transferred as follows:

a = y ⁽¹⁾ .r ⁽¹⁾ + y ⁽²⁾ .r ⁽²⁾ + ... + y ^(N) .r ^(N) ; In the

Decoding does not need to be known either the scatter signals used in the coding or the arbitrary signals used. Only the respectively agreed reconstruction signals or their agreed generation are necessary for the successful decoding. Effective encryption can be achieved, particularly in the case of frequently changing scatter signals and random signals. A further preferred embodiment of the invention is characterized in that the transfer signals are stored at one point in time and in that the output signal is generated from read out transfer signals at another point in time. As with the aforementioned transmission of transfer signals, the confidentiality requirements can also decisively determine the respective application of the invention when storing transfer signals. The modifications mentioned also apply to the storage of

Transfer signals. Another preferred embodiment of the invention is characterized in that a transfer signal is selected from such a range of a number of processed intermediate signals so that an AND operation of the

respective output signals with that reconstruction signal which is assigned to this transfer signal is the same as an AND operation of this reconstruction signal with that of these intermediate signals which is to be selected as the transfer signal in each case. In the case of programmable logic switchgears (FLAs), for example, these intermediate signals result in a

Reduction in hardware expenditure achievable.

Another preferred embodiment of the invention is characterized in that for a further intended logical combination of individual output signals for

Formation of a linked output signal with in each case a tuple generated for each of the individual output signals from a respective number of transfer signals for which a same reconstruction signal is assigned at a same position within the respective tuple, a further tuple with the same number of linked signals

further transfer signals are generated from the transfer signals in such a way that each of the linked transfer signals correspond to their position in the tuple according to the intended logical

However, the link is generated instead of the individual output signals from those transfer signals which are in turn provided at the same position in the tuple.

 To explain these linking rules for tuples from

 Transfer signals which, like in a Boolean algebra, for example for an AND operation, a

 OR operation, a negation can be defined, it can be shown that the following applies, for example, for N = 2, K = 2

For example, by linking the output signals that can be generated by means of these tuples, it can be shown that r ⁽¹⁾ .r ⁽²⁾ = 0; r ⁽¹⁾ .r ⁽²⁾ = 0; r ⁽¹⁾ + r ⁽²⁾ = 1; r ⁽¹⁾ = r ⁽²⁾ ;

For example, with the help of a neutral 1 element in an AND operation, the following can be shown

; It can thus be seen that transfer

signals with different scatter signals and arbitrary signals are equivalent. This can also be shown with the help of an O element that is neutral in an OR operation.

 As a result, as with algebra, linking rules can be defined for BOOTs. A switching mechanism can be constructed in which individual signals can be generated in the form of tuples from transfer signals and linked as tuples. A further preferred embodiment of the invention is characterized in that a circuit block is provided, to which at least one of a number of the input signals is supplied, and from which a tuple which is assigned to the output signal which can be generated therefrom and to the signal combination of the input signals which is associated with this output signal, generated from a number of transfer signals, which are generated so that each of these transfer signals each an OR operation of one hand

 AND linkage of the output signal with a reconstruction signal and assigned to the transfer signal

 on the other hand, an AND operation of an arbitrary signal assigned to the transfer signal corresponds to a scatter signal assigned to the transfer signal, and that each AND operation of one of the reconstruction signals with another of the reconstruction signals is always logically ZERO, and that an OR operation of all Reconstruction signals is always logically ONE, that each AND operation of one of the reconstruction signals with each

 assigned scatter signal is always logically ZERO, so that the output signal can be generated on the basis of this tuple of the transfer signals by means of an OR link of all AND links of one of the transfer signals each with the reconstruction signal assigned to this transfer signal. On

 Such a circuit block can be used modularly.

A further preferred embodiment of the invention is characterized in that at least one circuit component is provided in the circuit block for processing at least one offer of a number of intermediate signals for which an AND operation of one of these intermediate signals with one of the reconstruction signals is the same as an AND operation of this reconstruction signal with the output signal. Such a circuit component can be used in a modular manner in circuit blocks for generating a plurality of tuples of transfer signals.

Another preferred embodiment of the invention is characterized in that the circuit component four

 Intermediate signals processed, and a first

Intermediate signal, the signal value of which is always logically ZERO, a second intermediate signal, the signal value of which is equal to one of the input signals, a third intermediate signal, the

Signal value is inverted to the second intermediate signal, a fourth intermediate signal, the signal value to the first

Intermediate signal is inverted. Such

 Circuit component can be used advantageously, for example, as already explained with reference to Table 7.

Another preferred embodiment of the invention is characterized in that the circuit component four

Intermediate signals processed, namely a first intermediate signal; whose signal value is always logically ZERO, a second intermediate signal whose signal value is equal to an EXOR combination of two of the input signals, a third intermediate signal whose signal value is inverted to the second intermediate signal, a fourth intermediate signal whose signal value is the first

Intermediate signal is inverted. Such a circuit component can, for example, be used advantageously, as already explained with reference to Table 5.

A further preferred embodiment of the invention is characterized in that the circuit component processes sixteen intermediate signals, specifically a first intermediate signal, the signal value of which is equal to an AND operation of one of the input signals and an EXOR operation of two further of the input signals, a second intermediate signal, whose signal value is equal to an AND operation of one of the input signals with an inverted EXOR combination of the two further of the input signals, a third intermediate signal, the signal value of which is equal to an OR combination of the first and second intermediate signals, a fourth

 Intermediate signal whose signal value is equal to an AND operation from the inverted one of the input signals with a

EXOR operation of the two further of the input signals is a fifth intermediate signal, the signal value of which is equal to an OR operation of the third and second intermediate signals, a sixth intermediate signal, the signal value of which is equal to an OR operation of the fourth and second intermediate signals seventh intermediate signal, whose signal value is equal to an OR operation of the fourth and third intermediate signals, an eighth intermediate signal, whose signal value is equal to the inverted seventh intermediate signal, a ninth intermediate signal, whose signal value is equal to the inverted sixth intermediate signal, a tenth intermediate signal, whose signal value is equal to the inverted fifth intermediate signal, an eleventh intermediate signal whose signal value is equal to the inverted fourth intermediate signal, a twelfth

Intermediate signal whose signal value is equal to the inverted third intermediate signal, a thirteenth intermediate signal whose signal value is equal to the inverted second intermediate signal, a fourteenth intermediate signal whose signal value is equal to the inverted first intermediate signal, a fifteenth intermediate signal whose signal value is always logically ONE, a sixteenth Intermediate signal, the signal value of which is always logically ZERO. Such a circuit component can, as will be explained in the following with reference to Table 18, be used advantageously. By a larger number of processed

 Intermediate signals may require a smaller number of tuple transfer signals. This is useful, for example, for BOOTs of higher orders.

A further preferred embodiment of the invention is characterized in that at least one circuit part is provided in the circuit block for generating at least one of the transfer signals by means of a selection of one of the Intermediate signals of the processed offer. Such a circuit part can be programmable, for example

 be hard-wired. If, for example, the logical link to be specified is changed due to maintenance, the programmable hard-wired circuit connections can be modified in a simple manner. This can also be provided with optical means, for example. For example, a

 Variably predeterminable logic signal links can be provided in this way.

Another preferred embodiment of the invention is characterized in that a variably predetermined

Logical signal combination, by means of which the output signal can be generated from the input signals, is input in the form of a combination signal, which is composed of a number of logical signals, the signal value of which, as binary digits, corresponds to a truth table for the output signal. A link signal which can be input in this form in accordance with a variably predeterminable signal link can preferably be used for control signals from multiplexer elements.

Another preferred embodiment of the invention is characterized in that the circuit part two

 Has multiplexer elements, which are each the four

Intermediate signals of the circuit component are supplied as multiplexer input signals, and to which two of four binary digits of the link signal are input as control signals, with a most significant of these binary digits as a higher-order control signal and a least significant one of these binary digits as a low-order control signal for one of the multiplexer elements, and with a more significant one the remaining two of these binary digits as a higher-order control signal and a lower-order of these two remaining of these binary digits as a lower-order control signal for the other of the multiplexer elements. Such control of

Multiplexer elements are preferred, as can already be explained with reference to Table 7. Another preferred embodiment of the invention is characterized in that the circuit part two

Has multiplexer elements, which are each the four

Intermediate signals of the circuit component are supplied as multiplexer input signals, and to which two of four binary digits of the combination signal are input as control signals, with a most significant of these binary digits as a higher-order control signal and a most significant of the remaining three of these binary digits as a low-order one

 Control signal for one of the multiplexer elements, and with a higher-order of the two remaining of these binary digits as a lower-order control signal and a lower-order of these two remaining of these binary digits as a higher-order control signal for the other of the multiplexer elements. Such a circuit part can be used advantageously, for example, as already explained with reference to Table 5.

Another preferred embodiment of the invention is characterized in that the circuit block

 Has circuit component and a number of the circuit parts, each of which the four intermediate signals

Circuit component and four each of the binary digits of the link signal are supplied. Such one

 Circuit block is for example for generating

 Transfer signals for BOOTs of higher orders can be used.

Another preferred embodiment of the invention is characterized in that the circuit block two

Circuit components, each of which generates four intermediate signals, and has a circuit part which has two multiplexer elements, with the four intermediate signals which are generated by one of the circuit components and which are supplied to the one of the multiplexer elements as multiplexer input signals, and with the four intermediate signals which are generated by the other of the circuit components and which are fed to the other of the multiplexer elements as multiplexer input signals, and with a higher-order control signal for one of the multiplexer elements as a most significant binary digit of four binary digits of the combination signal supplied to the circuit part and with a higher-order control signal for the other of the multiplexer elements than a least significant binary digit of the four supplied binary digits of the combination signal, and with a low-order control signal for one of the multiplexer elements as a lower-order binary digit of the two remaining binary digits of the link signal, and with a low-order control signal for the other of the multiplexer elements as a higher-order binary digit from these two remaining binary digits of the link signal. Such a circuit block can be used advantageously, for example, as will be explained in the following with reference to Table 18.

A further preferred embodiment of the invention is characterized in that the circuit block has at least one logic element which has a first, a second, a third AND logic element and an OR logic element, with one of the input signals which is the first AND logic element at a non-inverting input, and the second AND gate at one

Is fed inverting input, and with one of the control signals which the first AND gate at an inverting input, the second AND gate at a non-inverting input, and the third

AND gate is fed to a non-inverting input, and with another of the control signals, which the first AND gate at a non-inverting input, the second AND gate at an inverting input, and the third AND gate at a non Is fed inverting input, as well as with one of the transfer signals, which is generated by the OR logic element from the signals supplied to it, which are generated by the three AND logic elements. On

such a circuit block is cheap, for example

regarding a signal runtime to form the transfer signals. Another preferred embodiment of the invention is characterized in that the circuit block has at least one logic element, which has a first, a second, a third, a fourth, a fifth AND logic element and an OR logic element, with one of the input signals, which the first AND gate at a non-inverting input, the second AND gate at an inverting input, the third

AND gate is fed to a non-inverting input, and the fourth AND gate is fed to an inverting input, and with a further one of the

Input signals, which is fed to the first AND gate at an inverting input, the second AND gate at a non-inverting input, the third AND gate at a non-inverting input, and the fourth AND gate at an inverting input, and with one of the control signals which the first AND gate on an inverting

Input, the second AND gate at an inverting input, the third AND gate at a non-inverting input, the fourth AND gate at a non-inverting input, and the fifth

AND gate is fed to a non-inverting input, as well as with another of the control signals, which the first AND gate is not at one

inverting input, the second AND gate at a non-inverting input, the third AND gate at an inverting input, the fourth

AND logic element at an inverting input, and the fifth AND logic element is fed to a non-inverting input, and with one of the transfer signals, which is generated by the OR logic element from the signals supplied to it, which are generated by the five AND logic elements are. Such a circuit block is advantageous, for example, with regard to a runtime for forming the transfer signals. Another preferred embodiment of the invention is characterized in that the circuit block has at least one circuit part to which two of the input signals and four of the control signals are fed. Such a circuit block is, for example, inexpensive

regarding a signal runtime to form the transfer signals.

A further preferred embodiment of the invention is characterized in that the circuit part has a first and a second logic element, with a higher-order control signal for the second logic element equal to a least significant of the four control signals supplied to the circuit part and with a lower-order one

Control signal for the second logic element is equal to a next higher value of the four control signals supplied to the circuit part and with a lower quality control signal for the first logic element is equal to a next higher quality of the four control signals supplied to the circuit part

Control signals and with a higher-order control signal for the first logic element equal to a most significant of the four control signals supplied to the circuit part. Such a circuit block is, for example, inexpensive

regarding a signal runtime to form the transfer signals.

Another preferred embodiment of the invention is characterized in that the output signal generated is checked in a test circuit. Test signals can be generated from the generated transfer signals, from which the output signal to be generated can also be generated, so that it can be checked.

Another preferred embodiment of the invention is characterized in that the generated transfer signals are checked in a test circuit. It can from the

generated transfer signals test signals are generated, from which the transfer signals to be generated in addition

can be generated so that they can be checked.

A further preferred embodiment of the invention is characterized in that the transfer signals can be corrected in accordance with test signals which are generated by a circuit component. Test signals can be generated, by means of which an incorrectly generated transfer signal can be corrected, so that such errors can be coped with.

This results in particular advantages, for example, for applications with fault-prone logic switching elements. The invention is explained in more detail with reference to the figures, in which exemplary embodiments are contained.

FIG. 1 shows a first circuit for generating a logical output signal from two logical input signals in accordance with a variably assignable logical link.

FIG. 2 shows a multiplexer element which is used in the circuits in FIGS. 1, 3, 14, 20, 21, 26, 27. FIG. 3 shows a second circuit for generating a logical output signal from two logical input signals in accordance with a logical combination which can be predetermined.

FIG. 4 shows a third circuit for generating a logical output signals from a number of logical input signals according to a variably predeterminable logical link.

FIG. 5 shows a fourth circuit for generating a logical output signal from a number of logical input signals in accordance with a variably predeterminable logical combination.

FIG. 6 shows a fifth circuit for generating a logical output signal from a number of logical input signals in accordance with a variably predeterminable logical combination.

FIG. 7 shows a sixth circuit for generating a logical output signal from a number of logical input signals in accordance with a variably predeterminable logical combination.

FIG. 8 shows a seventh circuit for generating a logical output signal from three logical input signals in accordance with a variably predeterminable logical one

Shortcut.

FIG. 9 shows an embodiment for a circuit component which is used in the circuit of FIG. 8.

FIG. 10 shows a further embodiment for the same circuit component from FIG. 8.

FIG. 11 shows a multiplexer element which is used in the circuit of FIG. 8. FIG. 12 shows an eighth circuit for generating a logical output signal from two logical input signals in accordance with a programmable, hard-wired logic combination. FIG. 13 shows a ninth circuit for generating a logical output signal from two logical input signals according to a programmable, hard-wired logic link.

FIG. 14 shows a tenth circuit for generating two output signals from three input signals in accordance with a programmable, hard-wired logic

Shortcut.

FIG. 15 shows an eleventh circuit for generation

a logical output signal from a number of logical input signals.

FIG. 16 shows a twelfth circuit for generating a logical output signal according to three variably predeterminable signal combinations. FIG. 17 shows a thirteenth circuit for generating a logical output signal according to three variably predeterminable signal combinations.

FIG. 18 shows a fourteenth circuit for generating logical transfer signals in accordance with a variably predeterminable signal combination from input transfer signals.

FIG. 19 shows a fifteenth circuit for generating logical transfer signals in accordance with three signal links which can be predetermined.

FIG. 20 shows a test circuit for checking the transfer signals of FIG. 19. FIG. 21 shows a sixteenth formwork for generating correctable transfer signals according to a variable signal link.

FIG. 22 shows a circuit component for correction the transfer signals of Figure 21.

FIG. 23 shows a circuit component for generating test signals from FIG. 21.

FIG. 24 shows a circuit component for generating test signals for use in connection with the

 Circuits of Figures 14 and 26.

FIG. 25 shows a circuit component for generating test signals for use in connection with the

 Circuits of FIGS. 14 and 26. FIG. 26 shows a seventeenth circuit for generating correctable transfer signals in accordance with programmable, hard-wired, logic operations.

FIG. 27 shows an eighteenth circuit for generating a logical output signal from two input signals in accordance with a variably predeterminable signal combination.

FIG. 28 shows a further embodiment for a circuit block from FIG. 1.

FIG. 29 shows a further embodiment for a circuit block which is used in FIGS. 3, 16, 17, 18, 19. FIG. 30 shows a further embodiment for one

Circuit block used in Figures 4, 5, 6, 21.

FIG. 31 shows a test element for the circuit of FIG. 18,

As FIG. 1 shows, two logic input signals x ₁ and x _{2 are} provided in a first circuit. A logical output signal a ^{(m) is} generated in accordance with a variably predeterminable logical combination. The respective one is variable The logical link to be specified is in accordance with the previously

Table 2 explained as a logic signal m entered according to a binary number, the binary digits according to 2, 2, 2, 2 can be entered as binary signals, so that they are binary

Signals form a link signal m. The input signals x ₁ and x ₂ , as well as the logic signal m, are input to a circuit block BA2, from which a BOOT _{2 is} generated by overcab signals y ⁽¹⁾ and y ⁽²⁾ . A circuit element RSA is provided for generating a reconstruction signal r from the two input signals. The reconstruction signal r and the two transfer signals y ⁽¹⁾ and y ⁽²⁾ are fed to a reconstruction element REK, from which the output signal a ^{(m) is} generated by the following combination of these three signals a ^(m) = y ⁽¹⁾ .r + y ⁽²⁾ . ; The circuit element RSA

Reconstruction signal r is generated by supplying the two input signals x ₁ and x ₂ , from which the reconstruction signal r is generated by EXOR operation by the following

Linking the two input signals: r = x ₁ . ₂ + x ₁ .x ₂ ; In the circuit block BA2 there is a circuit component ZWA

provided for generating four intermediate signals z ₁ , z ₂ , z ₃ and z ₄ . The intermediate signal z ₁ is generated so that it is always logic ZERO. The intermediate signal z ₄ is generated so that it is always logically ONE. The circuit component ZWA is supplied with the input signal x ₁ , which is forwarded as the intermediate signal z ₂ . The input signal x _{1 is} inverted by an inverter INV.O. This inverted input signal x ₁ , that is ₁ , is passed on as the intermediate signal z ₃ .

 The following intermediate signals are thus generated and

wsitered: z ₁ = D ⁽⁰⁾ (x ₂ , x ₁ ) = 0 = 0 _d ;

z ₂ = D ⁽³⁾ (x ₂ , x ₁ ) = x ₁ = 3 _d ; z ₃ = D ⁽¹²⁾ (x ₂ , x ₁ ) = ₁ = 12 _d ;

z ₄ = D ⁽¹⁵⁾ (x ₂ , x ₁ ) = 1 = 15 _d ; These four intermediate signals are fed to a sub-circuit UEA, in which two

 Multiplexer elements MUX4.0 and MUX4.1 are provided. Each of the multiplexer elements MUX4 are all four

Intermediate signals z ₁ , z ₂ , z ₃ , z ₄ supplied. In each of the

 Multiplexer elements MUX4 is a selector switch

 provided, one of each of the four supplied

Intermediate signals are selected and forwarded as each generated transfer signal. The transfer signal y ^{(1) is} generated and forwarded by the multiplexer element MUX4.0. from

Multiplexer element MUX4.1, the transfer signal y ^{(2) is} generated and forwarded. The selection switch of the multiplexer element MUX4 is supplied with two logic control signals, which are input as a low-order binary digit and a higher-order binary digit, which are combined as

Specify binary numbers 00, 01, 10, 11 which of the intermediate signals z ₁ , z ₂ , z ₃ , z _{4 is} to be selected, in the order just given. The multiplexer element MUX4.0 is as low value binary number, the binary digit 2 einpegeben the link signal m, and when the high-order binary digit binary number is input 2 ² of the linkage signal m. The multiplexer element MUX4.1 is entered with the binary digit 2 of the link signal as the low-order binary digit, and the binary digit 2 of the link signal m is entered as the higher-order binary digit. The transfer signals y ⁽¹⁾ and y ⁽²⁾ are accordingly generated, as indicated in table 7 already explained.

The multiplexer input signals are selected in the multiplex elements MUX4 in such a way that the binary digits supplied in each case, that is to say on the one hand for 2 ² , 2 ¹ at

Specify multiplex element MUX4.0 and, on the other hand, for 2 ³ , 2 ⁰ for multiplex element MUX4.1, as a two-digit binary number, how many of the four multiplexer input signals mentioned are to be selected. The first to fourth multiplexer input signals are selected in accordance with the two-digit binary numbers 00 to 11. These selected signals are emitted as a transfer signal y ⁽¹⁾ by the multiplexer element MUX4.0 on the one hand and on the other hand as a transfer signal y ⁽²⁾ by the multiplexer element MUX4.1. These transfer signals y ⁽¹⁾ and y ⁽²⁾ are accordingly selected in accordance with Table 7, specifically as a function of the binary digits supplied in each case, by means of which the signal link m to be assigned is determined in each case. The binary digits agreed by definition for the respective signal combination m to be specified are given in Table 2 previously explained. The reconstruction signal r is generated by an EXOR logic element EXOR as the circuit element RSA by EXOR logic of the two input signals x ₁ and x ₂ . In the logic element EXOR, an AND logic element AND.1 is provided, to which the input signal x ₁ on the one hand and on the other hand that inverted by an inverter INV.1

Input signal x ₂ , so ₂ , and which of these two signals x ₁ and ₂ generates a further signal according to an AND operation, which one

OR gate OR.1 is supplied. As a second signal, this OR logic element OR.1 is supplied with a further signal which is generated by an AND logic element AND.2. The AND logic element AND.2 receives, on the one hand, the input signal x ₂ and, on the other hand, the input signal x ₁ inverted by a further inverter INV.2 ₁ , fed to form the AND link. That from

OR logic element 0R.1 generated signal is forwarded as the reconstruction signal r generated by the EXOR logic element EXOR, which can be represented according to the following formula r = x ₁ . x ₂ + ₁ .x ₂ = x ₁ ⊕ x ₂ ; The reconstruction signal r and the two transfer signals y ⁽¹⁾ and y ⁽²⁾ become one

 Reconstruction element supplied REK. The specified one is

The sequence for the supplied transfer signals must be observed. An AND logic element AND.4 is provided for linking the reconstruction signal r and the transfer signal y ⁽¹⁾ . A further AND logic element AND.3 is provided for linking the transfer signal y ⁽²⁾ and that of one

Inverter INV.3 inverted reconstruction signal r, that is. The signals generated by the two AND logic elements AND.3 and UND.4 are linked by an OR logic element OP .4 to form the output signal a ^(m) . As a result, the reconstruction element REK forms a multiplexer element

MUX2, which selects one of two supplied signals y ⁽¹⁾ or y ⁽²⁾ , depending on one supplied as a control signal

Reconstruction regional. The table 7 explained above lists which of the intermediate signals is selected as one of multiplexer input signals in accordance with the link m to be specified by the multiplex element MUX4.0 as the transfer signal y ⁽¹⁾ , and which is selected by the multiplex element MUX4.1 as that

Transfer signal y ⁽²⁾ . The generated output signal a ^(m) can therefore be represented according to the following formula

a ^(m) = y ⁽¹⁾ .r + y ⁽²⁾ .r;

As FIG. 2 shows, a multiplexer element MUX4 consists of an OR logic element OR.M, which the signals generated by AND logic elements UND.M.0, UND.M.1, UND.M.2 and UND.M.3 be fed. Each of these AND logic elements AND.M is supplied with a multiplexer input signal ze ₀ , ze ₁ , ze ₂ , ze ₃ from one of multiplexer inputs on the one hand, and an enable signal, on the other hand

zh ₀ , zh ₁ , zh ₂ , zh ₃ , each of one of the others

AND logic elements UND.Z.0, UND.Z.1, UND.Z.2 and UND.Z.3 are each generated. These are controlled from control inputs by means of two control signals zg ₁ and zg ₀ . As a binary digit of a two-digit binary number, these control signals are used to control the selection of the one to be released

Multiplexer input signal of the respective multiplexer input, with the control signal zg ₀ being the lower-order binary digit and the control signal zg ₁ being the higher-order binary digit.

The AND gate AND.Z.0 is supplied with the control signal zg ₀ inverted by an inverter INV.M0, and the control signal zg ₁ inverted from a further inverter INV.M1 is fed so that the AND gate AND.Z .0 only releases its enable signal zh ₀ , which is used in the AND logic element AND.M.0 to enable the first multiplexer input signal ze ₀ to be selected if the two binary digits 00 are supplied by means of the control signals zg ₁ and zg ₀ . Otherwise, that is to say for the binary digits 01, 10, 11, the multiplexer input signal ze _{0 is} blocked at the AND logic element AND.M.0. Control signal zg _{0 is} supplied to AND gate AND.Z.1, and control signal zg, inverted by inverter INV.M1, is supplied, so that AND gate AND.Z.1 only releases its enable signal zh ₁ . which is used in the AND logic element AND.M.1 to enable the second multiplexer input signal ze to be selected if the two binary digits 01 are supplied by means of the control signals zg ₁ and zg ₀ . Otherwise, that is to say for the binary digits 00, 10, 11, the multiplexer input signal ze ₁ is blocked with the AND logic element AND.M.1.

The AND link AND.Z.2 is on the one hand from

Invsrtierer INV.M0 Insrtierter control signal zg ₀ fed, and andersrssits, the control signal zg, fed so that the AND gate AND.Z.2 only then releases its release signal zh ₂ , which for AND gate AND.M.2 for release of the third multiplexer input signal to be selected ze ₂ is used, the binary digits 10 by means of the

Control signals zg ₁ and zg _{0 are} routed. Otherwise, that is to say for the binary digits 00, 01, 11, the multiplexer input signal zs _{2 is} blocked at the AND logic element AND.M.2.

The two control signals zg ₁ and zg _{0 are} fed to the AND logic element AND.Z.3, so that the AND logic element AND.Z.3 only releases its release signal zh-, which is used for the AND logic element UND.M.3 Release of the visrten

selectable multiplexer input signals ze _{3 is} used if the binary digits 11 are supplied by means of the control signals zg ₁ and zg ₀ . Otherwise, that is to say for binary digits 00, 01, 10, the multiplexer input signal ze _{3 is} blocked at the AND logic element AND.M.3.

One of the four multiplexer input signals is output by the OR logic element OR.M as a multiplexer output signal zf jswsils depending on the control signals en zg ₁ and zg _{0 present in} accordance with the following table 8. Table 8

As FIG. 3 shows, two logic input signals x ₁ and x _{2 are} provided in the second circuit, from which a logic output signal a is generated in accordance with a variably inputable logic operation. The respective logical link is entered in accordance with the table 2 explained above as a link signal m according to a binary number, the binary digits of which can be entered as binary control signals according to 2 ³ , 2 ² , 2 ¹ , 2 ⁰ , so that these binary signals form the link signal m. The input signals x ₁ and x ₂ , as well as the logic signal m, are input to a circuit block BB2, from which a BOOT ₂ of the transfer signals y ⁽¹⁾ and y ^{(2) is} generated. The input signal x _{1 is} used as the reconstruction signal r. This reconstruction signal r and the two transfer signals y ⁽¹⁾ and y ⁽²⁾ are fed to a reconstruction element REK, from which the output signal a ^{(m) is} generated by the following combination of these three signals:

a ^(m) = y ⁽¹⁾ .r + y ⁽²⁾ .r; There is one in circuit block BB2

Circuit component ZWB provided for generating four intermediate signals z ₁ , z ₂ , z ₃ , z ₄ . The intermediate signal z ₁ is generated so that it is always logic ZERO. The intermediate signal z ₄ is generated so that it is always logically ONE. In the

Circuit component ZWB, an EXOR logic element EXOF is provided, which the two input signals x ₁ and x ₂

be fed. The output signal of this EXOR logic element EXOR is forwarded as the intermediate signal z ₂ . The output signal of the EXOR logic element EXOR is inverted by an inverter INV and passed on as the intermediate signal z ₃ . The following intermediate signals are thus generated and forwarded: z ₁ = D ⁽⁰⁾ (x ₂ , x ₁ ) = 0 = 0 _d

z ₂ = D ⁽⁶⁾ (x ₂ , x ₁ ) = x ₁ ⊕x ₂ = 6 _d

z ₃ = D ⁽⁹⁾ (x ₂ , x ₁ ) = x ₁ ⊕x ₂ = 9 _d

z ₄ = D ⁽¹⁵⁾ (x ₂ , x ₁ ) = 1 = 15 _d

 These four intermediate signals are fed to a sub-circuit UEB in which two multiplexer elements MUX4.0 and

MUX4.1 are provided. All four intermediate signals z ₁ , z ₂ , z ₃ and z _{4 are} supplied to each of the multiplexer elements MUX4.

The binary digits of the logic signal m are supplied to the sub-circuit UEB. In the sub-circuit UEB, the multiplex elements MUX4.0 and MUX4.1 are provided, which are the same as those in FIG. 1 and FIG. 2, and which are also controlled in each case on the basis of two of the binary digits in the form of two of the binary control signals which control the Multiplex elements MUX4 are supplied. Of the four supplied multiplexer input signals, one is selected and passed on as a multiplexer output signal. The multiplexer input signal to be selected first is intermediate signal z ₁ for both multiplex elements MUX4 dss. According to Table 2, this can be represented as a logical link according to 0 _d . The multiplexer input signal to be selected as the fourth is the intermediate signal z ₄ in both multiplex elements. Accordingly, this can be represented according to Table 2 as a logical link according to 15 _d . The EXOR logic element EXOR, which is the same as that of FIG. 1, generates the intermediate signal z ₂ by EXOR logic of the two input signals x ₁ and x ₂ . The intermediate signal z ₂ can therefore be represented according to Table 2 as a logical combination according to 6 _d . The

Intermediate signal z ₂ is supplied to the multiplex element MUX4.1 and the multiplex element MUX4.0 in the subcircuit UEB as the second multiplexer input signal to be selected. The intermediate signal z ₃ output by the inverter INV, which according to

Table 2 can be represented as a logic operation according to FIG. 9 _d , is supplied in the sub-circuit UEB to the multiplex element MUX4.1 and the multiplex element MUX4.0 as the third multiplexer input signal to be selected. The selection of the multiplexer input signals takes place in the multiplex elements MUX4 in such a way that the binary digits supplied in each case, that is on the one hand for 2 ⁰ , 2 ¹ for the multiplex element MUX4.0 and on the other hand for 2 ³ , 2 ² for

Specify multiplexer element MUX4.1 as a two-digit binary number, which number of the four multiplexer input signals must be selected. The multiplier element MUX4.0 is given as the low-order binary number if dis dis binary number 2 ^{1 of} the link signal m, and as the higher-order binary number, the binary number 2 ^{0 of} the link signal m is given for selection control. The multiplexer element MUX4.1 is entered as the low-value binary digit dis binary digit 2 ² of the link signal m, and the binary digit 2 ^{3 of} the link signal m is entered as the higher-order binary digit for selection control. The first through fourth multiplexer input signals are selected in accordance with the two-digit binary numbers 00 through 11. The selected signals are received as a transfer signal y ⁽¹⁾ from the multiplexer element MUX4.0 and on the other hand as a transfer signal y ⁽²⁾ from the multiplexer element

MUX4.1 issued.

These transfer signals y ⁽¹⁾ and y ⁽¹⁾ are accordingly selected in accordance with Table 5 already explained, specifically as a function of the binary digits supplied in each case, by means of which the signal link m to be specified in a definable manner is defined in each case. The binary digits agreed by definition for the respective variable signal combination m to be specified are given in Table 2 already explained. As

Reconstruction signal r, the input signal x _{1 is} used. The reconstruction signal r and the two transfer signals y ⁽¹⁾ and y ⁽²⁾ are fed to a reconstruction element REK, which is the same as that of FIG. 1 and which forms a multiplexer element MUX2. The output signal a ^{(m) is} generated by the reconstruction element REK, which is formed according to the variably to be predetermined combination m of the input signals x ₁ and x ₂ . Table 5, already explained, lists which of the multiplexer input signals according to

0 _d , 6 _d , 5 _d , 15 _d according to the variable Link m to be specified is selected by the multiplexer element MUX4.0 as the transfer signal y ⁽¹⁾ , and which is selected by the multiplexer element MUX4.1 as the transfer signal y ⁽²⁾ . The generated output signal a is therefore generated according to the following link by the reconstruction element REK: a ^(m) = y ⁽¹⁾ .x ₁ + y ⁽²⁾ . ₁ ; Wis already based on

As explained in Table 5, the over-oa signals y ⁽¹⁾ and y ⁽²⁾ generated by circuit block BB2 satisfy the following conditions: y ⁽¹⁾ = ar ⁽¹⁾ + b ⁽¹⁾ .s ⁽¹⁾ ; y ⁽²⁾ = ar ⁽²⁾ + b ⁽²⁾ .s ⁽²⁾ _;

a = a ^(m) = A ^(m) (x ₂ , x ₁ ); r = r ⁽¹⁾ = x ₁ ; r ⁽²⁾ = ₁ = ;

s ⁽¹⁾ = ; s ⁽²⁾ = r;

b ⁽¹⁾ = b ⁽²⁾ = b ^(m) = A ^(m) ( ₂ , ₁ );

The output signal a ^(m) can be variably specified according to the following table 9 as its truth table.

Table 9

^(m) From this, each as a number tuple according to Table 2, a

and b ^{(m) can} therefore be represented as follows:

a ^(m) =

b ^(m) = m

 The binary digits are by definition

the truth table according to Table 9 also the binary digits of the link signal m, so that these binary digits for 2 ³ , 2 ² , 2 ¹ , 2 ⁰ become the following binary number

can be put together: m = , From these

The respective truth table for y ⁽¹⁾ and y ^{(2) can also be} put together as table 10 according to the conditions: y ⁽¹⁾ = a ^(m) .r + b ^(m) . ; y ⁽²⁾ = a ^(m) . + b ^(m) .r, Table 10

From this, the respective transfer signals y ⁽¹⁾ and y ⁽²⁾ can be listed in accordance with the following table 11, depending on the respective binary digits of the logic signal m. Table 11

As FIG. 4 shows, a number K of logical input signals is provided in a third circuit, and a logical output signal a ^{(m) is} generated in accordance with a logic combination which can be predetermined. The respective logical

Linking is carried out according to the table 6 explained above in the form of a link signal m by means of a binary number

 entered, the binary digits

2 ^L , 2 ^L-1 , ..., 2 ¹ , 2 ⁰ ; L = 2 ^K-1 ; can be entered as binary control signals. These binary digits are supplied in groups of four each to one of the provided sub-circuits UEB, which are the same as those in FIG. 3 and whose number N is 2 ^K-2 . A circuit component ZWB, which is the same as that of FIG. 3, combines the two input signals x _K-1 and x _K to generate four intermediate signals, which are fed to each of the sub-circuits UEB, as well as the sub-circuit UEB shown in FIG.

Just like the sub-circuit UEB shown in FIG. 3, the first sub-circuit UEB.1 of FIG

logical signal of the least significant binary digits according to 2 ³ , 2 ² , 2 ^1, 2 ^{0 of} the variably specifiable according to Table 6

Linking signal m supplied. The next subcircuits UEB are the logical signals of the next four Higher-order binary digits are supplied in the same way from the link that can be variably specified according to Table 6. Accordingly, the logic signals of the binary digits according to 2 ^L , 2 ^L-1 , 2 ^L-2 , 2 ^L-3 are fed to the last subcircuit UEB.N from the logic combination which can be variably specified according to Table 6.

The circuit component ZWB and the sub-circuits UEB.n; n = 1, ... N; form a circuit block BB2N. In this

Circuit block BB2N generates two transfer signals from each sub-circuit UEB, and is forwarded as the ignale generated by circuit block BB2N. Circuit block BB2N thus generates a number 2N of transfer signals. These are supplied to a reconstruction circuit REKS.K-1, which is also supplied with the input signal x _K-1 . In the reconstruction circuit REKS.K-1 there is a number N of reconstruction elements REK.n; n = 1, ... N; intended. According to the order of supplied

Transfer signals regarding their ore suction in the sub-circuits UEB.n; n = 1.2, ... N; of the circuit block

BB2N, these transfer signals to the reconstruction circuit REKS.K-1 are paired to one of the

Reconstruction elements REK.n; n = 1, 2, ... N; supplied to the reconstruction circuit REKS.K-1. Likewise, each of these reconstruction elements REK.n is supplied with the input signal x _K-1 as a reconstruction signal. Each of these reconstruction elements REK.n consequently generates a further transfer signal, the number of which is equal to N, as the output signal. These become a further reconstruction circuit REKS.K-2

fed. In accordance with their sequence, these further transfer signals are paired with a reconstruction element REK.n; n = 1, 2, ... N / 2; supplied to the reconstruction circuit REKS.K-2. Each of these reconstruction elements REK.n is also the input signal x _K-2 as a reconstruction signal

fed. Each disser reconstruction element REK.n consequently generates a further transfer signal as an output signal. These are fed to a further reconstruction circuit, etc. The penultimate of these reconstruction circuits, that is to say the reconstruction circuit REKS.2, is therefore four

Transfer signals fed. According to their sequence, these are fed in pairs to one of the reconstruction elements REK.1, REK.2 of the reconstruction circuit REKS.2.

Likewise, each of the reconstruction elements REK.1, REK.2 is supplied with the input signal x ₂ as a reconstruction signal. Each of the reconstruction elements REK.1, REK.2 accordingly generates as

Output signal each a further transfer signal. These are fed to a last reconstruction circuit REKS.1. In accordance with their sequence, these are fed to a reconstruction element REK dsr reconstruction circuit REKS.1. Likewise, this reconstruction element REK is the input signal x ₁ as

Reconstruction signal supplied. This reconstruction element REK generates the output signal a ^(m) .

Based on the generated output signal, dis can each

used transfer signals are marked as follows. The output signal a ^(m) is generated by the reconstruction circuit REKS.1 using the input signal x ₁ as a reconstruction signal from two transfer signals as follows:

a ^(m) = y ⁽¹⁾ .x ₁ + y ⁽²⁾ . ₁ ; The transfer signals y ⁽¹⁾ , y ⁽²⁾ are transfer signals of a first order. Each of these is before the reconstruction circuit REKS.2 from js two more

Second order transfer signals using the

Input signals x ₂ generated as a reconstruction signal:

y ⁽¹⁾ = y ^{(1, 1)} .x ₂ + y ^{(1, 2)} . ₂ ; y ⁽²⁾ = y ^{(2, 1)} .x _{2 +} y ^{(2, 2)} ₂ ;

Each of the transfer signals used

y ^(1,1) , y ^(1,2) , y ^{(2, 1)} , y ^{(2, 2) of} the second order is made by one of the reconstruction circuits from each of two transfer signals from a third order with the aid of one of the input signals as a reconstruction signal generated, etc. The respective characteristics of one of the transfer signals are like follows when indexed indexes are listed for better

 Labelling:

j ^(l) = 1.2; j ⁽²⁾ = 1.2; ... j ⁽ⁱ⁾ 1,2; ... j ^(I) = 1.2; y; i = 1, ... I; I K - 1;

 This transfer signal beispiglswgisg from a

Order be equal to I. The respective identifier j ⁽ⁱ⁾

 is intended to indicate which of the order i summarized transfer signals can be generated therefrom.

 Each of the transfer signals of an order is wis follows from two transfer signals of the next higher order as follows:

 Thus, the reconstruction circuit REKS.K-1 generates transfer signals of an order K-1 from the transfer signals of an order K-1:

The transfer signals of order K-1 used in this process are sent to the reconstruction circuit REKS.K-1 by the circuit block

BB2N as the transfer signals generated by this, according to their order.

FIG. 5 shows a fourth circuit for generating a logical output signal a ^(m) from a number K of logical input signals x ₁ , x ₂ , ... x _K , according to a variably predeterminable logical signal combination. It is a circuit block

BB2N, which is already explained with reference to FIG. 4. The input signals x _K-1 and x _{K are} input to this, on the one hand, and on the other hand, the variable logic signal combination to be specified is input to the circuit block BB2N in the form of a combination signal m. The respective variably predeterminable logical link is entered as the link signal m, as already explained with reference to FIG. 4. As already explained with reference to Figure 4, each of the

Subcircuits UEB in the circuit block due to it

train-guided signals in pairs, each two transfer signals, which in this case with y ^{(n, 1)} , y ^{(n, 2)} ; n = 1, 2, ... N; be designated. The two of one of the sub-circuits UEB.n;

n = 1.2, ... N; generated transfer signals y ^{(n, 1),} y ^{(n, 2)} are each a separate reconstruction element REK.n; n = 1.2, ... N; fed, which is in each case the same as that in Figure 3

shown, and which as the reconstruction signal

Input signal x _K-1 is supplied in each case, and which as output signal is a transfer signal y ⁽ⁿ⁾ ; n = 1,2, ... N, generated. The transfer signals y ⁽ⁿ⁾ are generated as follows y ⁽ⁿ⁾ = y ^{(n, 1)} .x _K-1 + y ^{(n, 2)} . x _K-1 ; n = 1, ... N;

The transfer signals y ⁽ⁿ⁾ are fed with the input signals x ₁ to X _{K-2 used as} reconstruction signals to a reconstruction block REKON.YZ. This has its own AND gate for each transfer signal y ⁽ⁿ⁾

UND.YZ.n; n = 1.2, ..., N; , of which a different combination of inversions is provided for the supplied reconstruction signals. With the first AND logic element UND.YZ.1, none of the input signals x ₁ to x _{K-2 that are} fed in are integrated. With the last AND gate AND.YZ.N, all input signals x ₁ to x _{K-2 are} inverted. With the intermediate AND operation structure AND.YZ is such a variation of the inversions for the input signals x ₁ to x _K-2 provided in accordance with the ascending order for n to form all combinations, so that according to the order of the input signals x ₁ to x _K-2 for the first supplied input signal x _{1 is} least varied, and more frequently for the next following one, and for the last one supplied

Input signal x _K-2 the inversion is most often varied.

In the circuit shown in FIG. 5, the inversions are shown as inverting inputs from the AND logic elements.

Those generated by all AND logic elements UND.YZ

Signals are fed to an OR logic element OR.YZ, which generates the logical output signal a ^{(m) in} accordance with an OR logic operation. The generated output signal a ^(m) is accordingly generated as follows.

a ^(m) =

= y ⁽¹⁾ .x ₁ x ₂ ... x _K-3 X _K-2 +

+ y ⁽²⁾ .x ₁ x ₂ ... x _{K-3 K-2} +

+ y ⁽³⁾ .x ₁ x ₂ ... x _K-3 X _K-2 +

+ y ⁽⁴⁾ .x ₁ x ₂ ... x _{K-3 K-2} + + y ^(N-3) ₂ ... x _K-3 x _K-2 +

+ y ^(N-2) ₂ ... x _{K-3 K-2} +

+ y ^(N-1) ... x _K-3 x _K-2 +

+ y ^(N) . ... x _{K-3 K-2} +

 Which led to the reconstruction block REKON.YZ

Transfer signals y ⁽ⁿ⁾ ; n = 1, 2, ... N; are transfer signals of a first order. Each of these transfer signals y ⁽ⁿ⁾ is generated by a reconstruction element REK.n from two transfer signals y ^{(n, 1)} , y ^{(n, 2)} of a second order according to: y ⁽ⁿ⁾ = y ^{(n, 1)} .x _K-1 + y ^{(n, 2)} .x _K-1 ; n = 1, ... N; One of each of the reconstruction element REK.n is thus two supplied signals selected, either y ^{(n, 1)} or y ^{(n, 2)} , and forwarded. This selection is controlled by the input signal x _K-1 supplied to the reconstruction element REK.n as a control signal, the signal value of which as one

Binary digit can be considered. For x _K-1 = 1, y ^{(n, 1) is} selected and continued. For x _K-1 = 0, y ^{(n, 2) is} selected and forwarded. The reconstruction element REK thus selects one of two as a multiplexer element

supplied logic signals, controlled by the

Input signal as a supplied binary digit.

The reconstruction block REKON.YZ selects one of a number of N supplied logic signals and forwards this. This selection is controlled by the input signals x ₁ , x ₂ ,... X _K-2 , the logical signal value of which can in each case be regarded as an input binary digit. These supplied binary digits can be combined into a binary number, the most significant binary digit of which is formed by the signal value of x ₁ , followed by x ₂ , etc., until x _K-2 as the least significant binary digit. For (x ₁ x ₂ ... x _K-3 x _K-2 ) _b =

= (11 ... 11) _b is selected y ⁽¹⁾ , for (11 ... 10) _b is selected y ⁽²⁾ , etc., y ^(N-1) is selected for (00 ... 01) , is selected and y ^{(N) is} selected for (00 ... 00) _b . A multiplexer element MUXN can therefore be used as the reconstruction block REKON.YZ.

FIG. 6 shows a fifth circuit for generating a logical output signal a from a number K of logical input signals in accordance with a variably predeterminable logical combination. Transfer signals y ⁽ⁿ⁾ ; n = 1, ... 2N; in a manner which has already been explained with reference to FIG. 4, generated by a circuit block BB2N. These generated by the sub-circuits UEB, as explained

⁽ⁿ⁾

Transfer signals y are converted into a reconstruction with the input signals x ₁ to x _K-1 used as reconstruction signals. block REKON.RS fed. For each of the transfer signals y ^(n), this has its own AND gate AND.RS.n;

 n = 1.2, ... 2N; on which one is different

Combination of inversions is provided in the supplied reconstruction signals. With the first AND logic element UND.RS.l none of the input signals x ₁ to x _{K-1 are} inverted. With the last AND link AND.RS.2N, all input signals x ₁ to x _{K-1 are} inverted. In the intermediate AND logic elements UND.RS, such a variation of the inversions for the respectively supplied input signals x ₁ to x _{K-1 is} provided according to the ascending order for n to form all combinations, so that according to the order of the input signals x ₁ to x _{K-1 is} varied the least for the first input signal x ₁ supplied, and more frequently for the next input signal in each case, and the inversion is varied most frequently for the last input signal x _K-1 supplied. The AND logic gates

UND.RS.n are according to their ascending order for n starting with the transfer signal y ⁽¹⁾ for the AND logic element AND.RS.1 and then with the transfer signal y ⁽²⁾ for the

AND link AND.RS.2 according to its ascending

Sequence for n a transfer signal y ^{(n) is} supplied so that the last AND logic element AND.RS.2N is supplied with the transfer signal y ^(2N) .

Dis of all AND links AND.RS.n; n = 1.2, ... 2N; generated signals are fed to an OR logic element OR.RS, which generates the logical output signal a ^(m) according to an OR logic operation. The output signal a ^(m) is therefore generated as follows:

a ^(m) =

( ¹⁾

= y .x ₁ x ₂ ... x _K-2 x _K-1 +

( ²⁾

+ y ⁽³⁾ .x ₁ x ₂ ... x _{K-2 K-1} +

+ y .x ₁ x ₂ ... _K-2 x _K-1 +

( ⁴⁾

+ y .x ₁ x ₂ ... _K-2 x _K-1 + + y ^(2N-3) x ... x _K-2 x _K-1 +

+ y ^(2N-2) x ... x _K-2 x _-1 +

+ y ^(2N-1) x ... x _-2 x _K-1 +

+ y ^(2N) .x ... x _-2 x _-1 +

It can be seen that the R construction block REKON. RS each one of a number 2N of supplied transfer signals

is selected, depending on the signal values of the input signals x ₁ to x _K-1 . As a reconstruction block REKON. Therefore, a multiplexer element MUX2N can be used.

FIG. 7 shows a sixth circuit for generating a logical output signal according to a variably predeterminable logical combination. The output signal a ^(m) is made by means of a single large multiplexer element MUX4N as a reconstruction block REKON. M generates, which in each case selects a binary digit from a number 4N of supplied binary digits of the linking signal m and passes it on as output signal a ^(m) , in each case depending on the train-led signal values of the input signals x ₁ to x _K. For example, on the basis of a truth table, the link signal m is as a 4N tuple of its singular binary digits. For example, in the circuit of FIG. 6, only half the multiplexer element MUX2N is required due to the generated transfer signals.

For the circuits of FIGS. 4, 5, 6 and 7, the number of signals for input and output, for example when implemented as an integrated circuit for a number of pins, is K + (1 + L) + 1 = K + 2 ^K + 1;

As FIG. 8 shows, a seventh circuit has been assigned

Generation of a logical output signal from three input signals x ₁ , x ₂ and x _{3 in} accordance with a variably predeterminable logical combination on a circuit block B02. Disser contains a circuit component ZW0 for generating 16 intermediate signals z ₀ , z ₁ ... z ₁₅ . These are entered into each of two MUX16 multiplexer elements, each one of which Select 16 intermediate signals and forward them as transfer signals y ⁽¹⁾ and y ⁽²⁾ . The two multiplexer elements MUX16 form a subcircuit UEC. The UEC subcircuit and the

 Circuit components ZWC form the circuit block BC2. Each of the MUX16 multiple elements is controlled by four control lines, each of which is used as a control signal

Binary digits are entered, which, when put together to form a binary number, result in the logical link to be specified for the input link signal m. The binary digits for 2 ⁴ , 2 ⁵ , 2 ⁰ , 2 ¹ of the binary number for the link signal m are input to the first multiplex element MUX16.1, which is in accordance with one of the input binary digits

fixed binary number as the transfer signal y ⁽¹⁾ that of the intermediate signals z _i , 0 i 15, selects whose count index i is equal to this binary number for controlling the multiplex element

MUX16.1 is. The binary digits for 2 ⁷ , 2 ⁶ , 2 ^3, 2 ² from the

 Binary number for the link signal m are the second

Multiplexer element MUX16.2 entered, which according to a further binary number fixed by these entered binary digits therefrom as the transfer signal y ⁽²⁾ that of

Intermediate signals z _i , 0 i 15, whose count index i is equal to this unit number for controlling the multiplexer element

MUX16.2 is. Accordingly, y ⁽¹⁾ is selected from ... (z ₀ , z ₂ , z ₁ , z ₃ , z ₀ , z ₂ , z ₁ , z ₃ , z ₀ , z ₂ , z ₁ , z ₃ , z ₀ , z ₂ , z ₁ , z ₃ , z ₈ , z ₁₀ , z ₉ , z ₁₁ , z ₈ , z ₁₀ , z ₉ , z ₁₁ , z ₈ , z ₁₀ , z ₉ , z ₁₁ , z ₈ , z ₁₀ , z ₉ , z ₁₁ , z ₄ , z ₆ , z ₅ , z ₇ , z ₄ , z ₆ , z ₅ , z ₇ , z ₄ , z ₆ , z ₅ , z ₇ , z ₄ , z ₆ , z ₅ , z ₇ , z ₁₂ , z ₁₄ , z ₁₃ , z ₁₅ , z ₁₂ , z ₁₄ , z ₁₃ , z ₁₅ , z ₁₂ , z ₁₄ , z ₁₃ , z ₁₅ , z ₁₂ , z ₁₄ , z ₁₃ , z ₁₅ ) according to m + 1 = 1,2,3,4,5,6,7,8,9, ....., 256;

y ⁽²⁾ from ... (

z ₀ , z ₀ , z ₀ , z ₀ , z ₁ , z ₁ , z ₁ , z ₁ , z ₂ , z ₂ , z ₂ , z ₂ , z ₃ , z ₃ , z ₃ , z ₃ ,

z ₄ , z ₄ , z ₄ , z ₄ , z ₅ , z ₅ , z ₅ , z ₅ , z ₆ , z ₆ , z ₆ , z ₆ , z ₇ , z ₇ , z ₇ , z ₇ , z ₈ , z ₈ , z ₈ , z ₈ , z ₉ , z ₉ , z ₉ , z ₉ , z ₁₀ , z ₁₀ , z ₁₀ , z ₁₀ , z ₁₁ , z ₁₁ , z ₁₁ , z ₁₁ , z ₁₂ , z ₁₂ , z ₁₂ , z ₁₂ , z ₁₃ , z ₁₃ , z ₁₃ , z ₁₃ , z ₁₄ , z ₁₄ , z ₁₄ , z ₁₄ , z ₁₅ , z ₁₅ , z ₁₅ , z ₁₅

) according to m + 1 = 1,2,3,4,5,6,7,8,9, ....., 256;

The two transfer signals y ⁽¹⁾ and y ⁽²⁾ and, as a reconstruction signal, the input signal x ₂ as are fed to a reconstruction element REK, which is the same as that of FIG. 1, to generate the output signal a ^(m) . The intermediate signals z _i are generated by the circuit component ZWC in accordance with Table 12 below.

Table 12

The intermediate signals z _i are generated in accordance with the logic operations in the circuit component ZWC shown in Table 12 on the right.

A tuple (y ⁽¹⁾ , y ⁽²⁾ ) is generated from the Zwix signals in Table 12 as a form of representation of the output signal a ^(m) and is selected as follows:

(y ¹ y ⁽²⁾ ) off ....

An example of a circuit component ZWC is shown in FIG. The input signals x ₂ and x ₁ become one

EXOR logic element EXOR leads to the generation of a

Signals x ₂ ⊕x ₃ . This is done by an AND gate

AND.1 linked to the input signal x ₁ to generate the

Intermediate signals z ₁ . The intermediate signal z ₀ is always generated according to logic ZERO. An AND logic element AND.2, the signal x ₂ ⊕x _{3 is} input in inverted form and the input signal x _{1 is} input for the ore generation of the intermediate signal z ₂ . One

OR logic element 0R.3, the intermediate signals z ₁ and z _{2 are} input to generate the intermediate signal Z ₃ . One

AND logic element AND.4, the signal x ₂ ⊕x _{3 is} entered and the signal x _{1 is} entered inverted to generate the

Intermediate signals z ₄ . The intermediate signals z ₁ and z _{4 are} input to an OR logic element 0R.5 to generate the

Intermediate signals z ₅ . The intermediate signals z ₂ and z _{4 are} input to an OR gate 0R.6 to generate the

Intermediate signals z ₆ . The intermediate signals z ₃ and z _{4 are} input to an OR logic element 0R.7 in order to generate the

Intermediate signals z ₇ . This is done by an inverter INV.8

Intermediate signal z ₇ inverted to generate the intermediate signal z ₈ . The intermediate signal z _{6 is} inverted by an inverter INV.9 to generate the intermediate signal z ₉ . Of a

Inverter INV.10, the intermediate signal z _{5 is} inverted to

Generation of the intermediate signal z ₁₀ . From an inverter

INV.11, the intermediate signal z _{4 is} inverted to generate the

Intermediate signals z ₁₁ . This is done by an inverter INV.12

Intermediate signal z ₃ inverted to generate the intermediate signal z ₁₂ . The intermediate signal z _{2 is} inverted by an inverter INV.13 to generate the intermediate signal z ₁₃ . The intermediate signal z _{1 is} inverted by an inverter INV.14 to generate the intermediate signal z ₁₄ . The intermediate signal z ₁₅ is always generated according to logical ONE.

FIG. 10 shows a further example of the circuit component ZWC. The intermediate signals z _i are from transfer signals z and z; i = 0.1, ... 15; in the

Circuit components ZWC can be generated, according to z _i = zx ₁ + zx ₁ ; As indicated in table 12 on the left, these transfer signals z and z are selected in each case in the following manner from the intermediate signals z _r = 0 _d generated by the circuit component ZWB; z _II = 6 _d ; z _III = 9 _d ; z _IV = 15 _d ;

 z (i)

(0 _d , 6 _d , 9 _d , 15 _d , 0 _d , 6 _d , 9 _d , 15 _d , 0 _d , 6 _d , 9 _d , 15 _d , 0 _d , 6 _d , 9 _d , 15 _d )

 according to i = 0.1,2,3,4,5,6,7,8,9,10,11,12,13,14,15;

 z (i)

(0 _d , 0 _d , 0 _d , 0 _d , 6 _d , 6 _d , 6 _d , 6 _d , 9 _d , 9 _d , 9 _d , 9 _d , 9 _d , 15 _d , 15 _d , 15 _d , 15 _d )

 according to i = 0.1,2,3,4,5,6,7,8,9,10,11,12,13,14,15;

As indicated in Table 12 below, the intermediate signals z _{i are} each from a reconstruction element REK

generated in the circuit component ZWC. Each reconstruction element REK is the input signal x ₁ as the reconstruction signal, the first transfer signal is z and the second

Transfer signal z is supplied, which are specified as explained. The respective selection of the transfer signals z and z is provided hard-wired in the circuit component ZWC. The intermediate signals z _{i are} generated by the reconstruction elements REK in the circuit component ZWC from these transfer signals z and z, as indicated in Table 12. As FIG. 11 shows, the multiplexer element MUX16 consists of AND logic elements AND.0, UND.1, ... AND.15, which are supplied with the control signals zg ₀ , zg ₁ , zg ₂ , zg ₃ . The

AND logic elements AND each have a different combination of inverting and non-inverting inputs, so that in each case only for one of these AND logic elements AND and depending on each

supplied control signals there is a release of the respectively assigned intermediate signal z _i . The outputs of the AND logic element AND are fed to an OR logic element OR, which at its output corresponds to the respective

Control signals selected intermediate signal z _i outputs.

As with all other multiplexer elements, the signals supplied in each case are shown in FIG in an ascending order. This affects the multiplexer input signals to be selected as well as the control signals. The diagonal of the multiplexer element shown in rectangular form serves to mark the order of these signals. Starting from a marking point M, in which the diagonal is drawn, a higher-value control signal is closer to each

this marking corner. Likewise, a multplexer input signal to be selected as a higher value is shown in each case closer to the marking corner. For example, that shown in FIG. 11

Multiplex input signal z _{0 can} be selected as multiplexer output signal z _i if all control signals are ZERO.

As shown in FIG. 12, a circuit block EB2F is provided in an eighth circuit, in which a predefined logic operation is provided, in which one of the points P0, P6, P9, P15 has a line connection in a circuit element UEF and on the other hand one of Points Q0, Q6, Q9, Q15 also have a line connection, while the rest of these points none

Line connection. In this way, one of the logical signals 0 _d , 6 _d , 9 _d , 15 _{d is} selected hard-wired for the transfer signal y ⁽¹⁾ and also for the transfer signal y ⁽²⁾ . A comparison of this circuit with that of FIG. 3 shows that in the case of an otherwise identical circuit instead of the subcircuit UEB and the input of the logical logic signal m to be specified in the circuit of FIG. 12, programmably hard-wired line connections of the circuit element UEF are provided. These line connections for determining the transfer signals y ⁽¹⁾ and y ⁽²⁾ , and thus for determining the hard-wired logic operation, are to be made as explained in Table 5.

As FIG. 13 shows, a circuit block BA2F is provided in a ninth circuit, in which a logic operation to be specified is provided in a hard-wired manner, in which in FIG a circuit element UEF on the one hand one of points R0, R3, R12, R15 has a line connection and one of points S0, S3, S12, S15 also has a line connection, while the rest of these points have no line connection. In this way, one of the logical signals 0 _d , 3 _d , 12 _d , 15 _{d is} hard-wired for the transfer signal y ⁽¹⁾ and on the other hand also for the transfer signal y ⁽²⁾ . A comparison of this circuit with that of FIG. 1 shows that with an otherwise identical circuit instead of the subcircuit UEA and the input of the logic link signal m to be specified in the circuit of FIG. 13, programmable hard-wired line connections of the circuit element UEF are provided. These line connections for determining the transfer signals y ⁽¹⁾ and y ⁽¹⁾ and thus for determining the hard-wired logic to be specified

Linking as shown in Table 7, tense.

As FIG. 14 shows, in the case of a tenth circuit, a circuit block BB2F2 for generating two output signals a ₍₁₎ and a ₍₂₎ from three input signals x ₁ , x ₂ , x _{3 in} accordance with a logic combination to be specified, which is programmably hard-wired, in that a line connection is provided at points P1, P2, P3, P4 and Q1, Q2, Q3, Q4. In this way, these line connections are used to generate, from a range of intermediate signals z ₁ , z ₂ , z ₃ , z ₄ , which are generated by a circuit component ZWB, as already explained with reference to FIG. 3, from the input signals x ₂ and x ₃ . The intermediate signal that is to be used as a transfer signal for the generation of the respective output signal is selected in each case. Depending on the signal values of the input signals x ₁ and x ₂ , one of four transfer signals is selected by a multiplexer element MUX4.1 as a reconstruction block REKON.1 and passed on as a generated output signal a ₍₁₎ . The second output signal a ₍₂₎ is generated in the same way by a second multiplexer element MUX4.2 as a reconstruction block REKON.2 by one of four further transfer signals

is selected. The hard-wired logic operation is provided in this exemplary embodiment in accordance with a 1-bit full adder. The input signal x ₁ serves as an overflow input. The input signal x ₂ serves as the first summand. The input signal x ₃ serves as a second summand. The output signal a ₍₁₎ is the

Overflow outlet. The output signal a ₍₂₎ is the sum output. Using table 13 as the truth table for the output signals a ₍₁₎ and a ₍₂₎ , the logical combination is predefined for both output signals in this exemplary embodiment.

Table 13

From each of the multiplexer elements MUX4.i; i = 1.2; should be one of four transfer signals selected and forwarded as output signal a _(i) , depending on the signal values of the two input signals x ₁ and x ₂ . This is shown as a link for i = 1,2; a

The following reconstruction signals can be seen from this:

 The output signals are generated as follows

i - 1,2, a

Intermediate signals are emitted by the circuit component ZWB as follows: z ₁ = 0; z ₂ = x ₂ ⊕x ₃ ; z ₃ = x ₂ ⊕x ₃ ; z ₄ = 1;

Table 14 shows the reconstruction signals and intermediate signals as a truth table. Table 14

The determination of which of the intermediate _signals z _j ; j = 1,2,3,4; than which of the transfer signals yn = 1,2,3,4; i = 1.2;

 is selected by the respective line connection in points P1, P2, P3, P4, Q1, Q2, Q3, Q4, should be carried out and checked based on the following condition:

a _(i) .r ⁽ⁿ⁾ = z _j .r ⁽ⁿ⁾

= y .r ⁽ⁿ⁾ ;

Based on the necessary condition y .r ⁽ⁿ⁾ = a _(i) .r ⁽ⁿ⁾ ;

a _(i) .r ^{(n) should be} formed. For each of the intermediate signals, z _j .r ^{(n) should be} formed and compared with a _(i) .r ⁽ⁿ⁾ . The intermediate signal z _j for which z _j .r ^{(n) is} equal to a _(i) .r ⁽ⁿ⁾ is to be used as the transfer signal y.

The transfer signal y should be allocated in this embodiment of the intermediate signal Z ₄ , realized by the

Line connection at point P1. This should be explained and checked using Table 15. Table 15

Likewise, the transfer signal y (2) in this exemplary embodiment is to be assigned the intermediate signal z ₂ by

Point P2 the line connection is made. This should be explained and checked using Table 16.

Table 16

Likewise, the remaining required transfer signals are derived from the intermediate signals by line connections in the points mentioned, as can be seen from Table 17. Table 17

To generate the output signal a ₍₂₎ , the multiplexer element MUX4.2 is only required as additional circuitry in conjunction with the line connections in points Q1, Q2, Q3, Q4 of a circuit element UEF.2.

 A circuit component ZWB is therefore sufficient to generate the intermediate signals, even if several output signals are to be generated. A comparison with FIG. 7 also reveals that only a multiplexer element that is half as large is required.

As FIG. 15 shows, an eleventh circuit for generating a logical output signal consists of a number of logical input signals from a circuit block BOOT2 for generating the following signals: a first reconstruction signal r ⁽¹⁾ in one

 Circuit component R1 of the circuit block BOOT2

Input signals x _K , ... x ₁ according to r ⁽¹⁾ = R ⁽¹⁾ (x _K , ... x ₁ ); a second reconstruction signal r ⁽²⁾ in one

Circuit component R2 of the circuit block BOOT2

Input signals x _K , ... x ₁ according to r ⁽²⁾ = R ⁽²⁾ (x _K , ... x ₁ ); a first scatter signal s ⁽¹⁾ in one

 Circuit components S1 of the circuit block BOOT2

Input signals x _K , ... x ₁ according to s ⁽¹⁾ = S ⁽¹⁾ (x _K , ... x ₁ ); a second scatter signal s ⁽²⁾ in one

 Circuit component S2 of the circuit block BOOT2

Input signals x _K , ... x ₁ according to s ⁽²⁾ = S ⁽²⁾ (x _K , ... x ₁ ); of a first arbitrary signal b ⁽¹⁾ in one

Circuit component B1 of the circuit block BOOT2

Input signals x _K , ... x ₁ according to b ⁽¹⁾ = B ⁽¹⁾ (x _K , ... x ₁ ); of a second arbitrary signal b ⁽²⁾ in one

 Circuit component B2 of the circuit block BOOT2

Input signals x _K , ... x ₁ according to b ⁽²⁾ = B ⁽²⁾ (x _K , ... x ₁ ); and an intermediate output signal av in one

Circuit components A of the BOOT2 circuit block

Input signals x _K , ... x ₁ according to av = a = A (x _K , ... x ₁ );

According to the invention, there are only the signals generated by the circuit components R1, R2, S1, S2

r ⁽¹⁾ , r ⁽²⁾ , s ⁽¹⁾ , s ⁽²⁾ for the respective otherwise appropriate logical links of the input signals x _K , ... x ₁ dis the following restrictions, so that for these

Circuit components each generated signals always the following logic conditions apply ropes: r ⁽¹⁾ + r ⁽²⁾ = 1; r ⁽¹⁾ .r ⁽²⁾ = 0; r ⁽¹⁾ .s ⁽¹⁾ = 0; r ⁽²⁾ .s ⁽²⁾ = 0; As a check of the correct functioning of the circuit components

In this application, R1, R2, S1, S2, one OR gate and three AND gate can be provided. The OR combination of the first reconstruction signal r ⁽¹⁾ and the second reconstruction signal r ⁽²⁾ should always result in ONE. If this is not the case, there is an error in front. The AND operation of the first reconstruction signal r ⁽¹⁾ and the second reconstruction signal r ⁽²⁾ should always result in ZERO. If this is not the case, there is an error. The AND operation of the first reconstruction signal r ⁽¹⁾ and the first scatter signal s ⁽¹⁾ should always result in ZERO. If this is not the case, there is an error. The AND operation of the second reconstruction signal r ⁽²⁾ and the second scatter signal s ⁽²⁾ should always result in ZERO. If this is not the case, there is an error.

A first transfer signal y ^{(1) is} generated by a circuit component Y1 of the circuit block BOOT2 from the intermediate output signal av, the first reconstruction signal r ⁽¹⁾ , the first scatter signal s ⁽¹⁾ and the first arbitrary signal b ⁽¹⁾ , according to the following combination: y ⁽¹⁾ = av.r ⁽¹⁾ + b ⁽¹⁾ .s ⁽¹⁾ ; A second transfer signal y ^{(2) is} generated by a circuit component Y2 of the circuit block BOOT2 from the intermediate output signal av, the second reconstruction signal r ⁽²⁾ , the second scattering signal s ⁽²⁾ and the second arbitrary signal b ⁽²⁾ according to the following combination y ^{( 2)} = av.r ⁽²⁾ + b ⁽²⁾ .s ⁽²⁾ ;

The two reconstruction signals r ⁽¹⁾ and r ⁽²⁾ and the two transfer signals y ⁽¹⁾ and y ^{(2) are} generated by the circuit block BOOT2 from the input signals x _K , ... x ₁ .

For crypto-technical applications, it should be noted that

that in these four signals r ⁽¹⁾ , r ⁽²⁾ , y ⁽¹⁾ , y ⁽²⁾ in particular the output signal a is "hidden". Furthermore, the input signals x _K , ... x _{1 are} not immediately recognizable.

This also applies in particular to the case where there is a change in the timing of the respective logical connections of a number of the circuit components. The output signal a is generated by a reconstruction part REKONS from the two reconstruction signals r ⁽¹⁾ , r ⁽²⁾ and from the two transfer signals y ⁽¹⁾ , y ⁽²⁾ according to the following logical combination: a = y ⁽¹⁾ .r ⁽¹⁾ + y ⁽²⁾ . r ⁽²⁾ ; As with other applications, it can be provided that the transfer signals from a location where the

Circuit block BOOT2 is to be transferred to another location where the reconstruction block REKONS is located. Just like the handover signals, the

Reconstruction signals are transmitted. However, it can also be provided that the reconstruction signals are not

transferred, but from additional

Circuit components, for example R1 and R2 at the location of the

Reconstruction block REKONS are generated.

As with other applications, it can be provided that the transfer signals are stored at one time. At another point in time, the transfer signals can be read out later. However, it can also be provided that the reconstruction signals are not stored, but are generated by circuit components, for example R1 and R2, at a later point in time.

As FIG. 16 shows, a twelfth circuit for generating a logical output signal according to three variably predeterminable signal combinations consists of three combination circuits M1, M2, M3, and a test circuit TEST1. As already explained with reference to FIG. 3, each of these logic circuits consists of a circuit part BB2 as a circuit block BB2 and a reconstruction element REK.

The logic circuit M1 is supplied with two input signals x ₁ and x ₂ . A link signal ml is supplied as a variably predeterminable signal link. A logic signal a ^{(ml) is} generated as an output signal of the logic circuit M1, as has already been explained with reference to FIG. 3.

The logic circuit M2 is fed two input signals x ₁ and x ₂ . A link signal m2 is supplied as a variably predeterminable signal link. A logic signal a ^{(m2) is} generated as an output signal of the logic circuit ^M2 , as has already been explained with reference to FIG. 3. The logic circuit M3 is supplied with two input signals x ₁ and x ₂ . A link signal m3 is supplied as a variably predeterminable signal link. A logic signal a is generated as an output signal of the logic circuit M3, as has already been explained with reference to FIG. 3.

The two transfer signals are from the circuit part BB2.M1 of the logic circuit M1 and generated. With the input signal x ₁ as a reconstruction signal, this becomes

Signal a ^(m1) generated, according to a ^(m1) = .x ₁ + ₁ ; This

Signal is a logical link between the two

Input signals x ₁ and x ₂ can be displayed, according to

a ^(m1) = A ^(m1) (x ₂ , x ₁ );

The two transfer signals are from the circuit part BB2.M2 of the logic circuit M2 and generated. With the input signal x ₁ as a reconstruction signal, this becomes

Signal a ^(m2) generated, according to a ^(m2) = .x ₁ + This signal is a logical link between the two

Input signals x ₁ and x ₂ can be displayed, according to

a ^(m2) = A ^(m2) (x ₂ , x ₁ );

The two transfer signals are from the circuit part BB2.M3 of the logic circuit M3 and generated. With the

Signal a ^(m1) as a reconstruction signal becomes this

Output signal a generated according to a = .a ^(m1) + ^(m1) ;

This signal is a logical link between the two

Signals a and a can be represented, which in turn can be represented as a logical combination of the two input signals, so that applies

a = A ^(m3) (a ^(m2) , a ^(m1) ) =

= A ^(m3) (A ^(m2) (x ₂ , x ₁ ), A ^(m1) (x ₂ , x ₁ )) = A (x ₂ , x ₁ );

 The following transfer signals are used

= a ^(m1) .x ₁ + b ^(m1) ; = a ^(ml) . + b ^(m1) .x ₁ ; = a ^(m1) .x1 + b ^(m2) . = a ^(m2) + b ^(m2) .x ₁ ;

= aa ^(m1) + b. ^(m1) ; = aa ^(m1)

+ ba ^(m1) ;

 The following applies

a ^(m1) = A ^(m1) (x ₂ , x ₁ ) = .x ₁ + .x ₁ ;

b ^(m1) = B ^(m1) (x ₂ , x ₁ ) = A ^(m1) ;

a ^(m2) = A ^(m2) (x ₂ , x ₁ ) =

b ^(m2) = B ^(m2) (x ₂ , x ₁ ) = A ^(m2) (

a = A ^(m3) (a ^(m2) , a ^(m1) ) = A (x ₂ , x ₁ ); b = B ^(m3) (a ^(m2) , a ^(m1) ) = A ^{(m3) (m2)} , ^(m1) );

= t ⁽¹⁾ .x ₁ + t ⁽²⁾ ₁ = t ⁽³⁾ ;

For the generation of a test signal t ⁽¹⁾ from the two transfer signals and y is the transfer signal usable as reconstruction signal, according to

t ⁽¹⁾

For the generation of a test signal t ⁽²⁾ from the two

Transfer signals and y is the transfer signal usable as a reconstruction signal, according to

t ⁽²⁾ ) () ()

For the generation of a test signal t ⁽³⁾ from the two

Test signals t ⁽¹⁾ and t ⁽²⁾ , the input signal x _{1 can be used} as a reconstruction signal, according to t ⁽³⁾ = t ⁽¹⁾ .x ₁ + t ⁽²⁾ .

 The output signal a can therefore be generated, according to

a =

+

C

= t ⁽¹⁾ .x ₁ + t ⁽²⁾ . ₁ = t ⁽³⁾ ;

In this way, the output signal a can also be generated, so that it can be checked by means of the test circuit TEST1. A reconstruction element REK.1 is provided in the test circuit TEST1. The transfer signals and y

fed. The transfer signal (is supplied as the reconstruction signal. The test signal t ^{(1) is} generated. It is

a further reconstruction element REK.2 is provided. This will be the handover signals and y fed. As

Reconstruction signal becomes the transfer signal train led. The test signal t ^{(2) is} generated. It's another one

Reconstruction element REK.3 provided. The test signals t ⁽¹⁾ and t ^{(2) are} fed to the latter as transfer signals. The input signal x _{1 is} supplied as the reconstruction signal.

The test signal t ^{(3) is} generated. The tuple (t ⁽¹⁾ , t ⁽²⁾ ) of the test signals t ⁽¹⁾ and t ⁽²⁾ as the transfer signals of this tuple is therefore a form of representation for the output signal a. An EXOR logic element EXOR is provided. The output signal a and the test signal t ^{(3) are} fed to this. An error signal ERR is generated. It becomes an erroneously generated output signal a or an erroneously generated one

Test signal t ⁽³⁾ is displayed if this error signal ERR is logically ONE.

It can thus be seen that due to the use of transfer signals according to the invention by means of a simple

 Test circuit TEST1 a generated output signal a can be checked.

As FIG. 17 shows, there is a thirteenth circuit for generating a logical signal according to three veri Predeterminable signal combinations from four circuit parts

 BB2.M1, BB2.M2, BB2.Y1, BB2.Y2, from three reconstruction elements REK.Y1, REK.Y2, REK.Y3, and a test circuit TEST2.

The circuit part BB2.M1 two input signals x ₁ and x _{2 are} supplied. A link signal ml is supplied as a variably specifiable signal link. There will be two handover signals and generated, as already explained with reference to Figure 3.

The circuit part BB2.M2 the two input signals x ₁ and x _{2 are} fed. A link signal m2 is supplied as a variably predeterminable signal link. There will be two

Transfer signals and y generates, as has already been explained with reference to FIG. 3. The circuit part BB2.Y1 are the two transfer signals

and fed. Can be specified as a variable

A logic signal m3 is supplied to the signal link. Two transfer signals and are generated. This

are fed to a reconstruction element REK.Y1. As

 The transfer signal is fed to the reconstruction signal.

It will be a handover signal generated, as already explained with reference to Figure 3.

The circuit part BB2.Y2 are the two transfer signals

and fed. Can be specified as adjustable

A logic signal m3 is supplied to the signal link. There will be two handover signals and generated. This

are brought to a reconstruction element REK.Y2.

The transfer signal is used as the reconstruction signal

fed. It will be a handover signal generated, as already explained with reference to Figure 3.

The transfer signals and are fed to the reconstruction element REK.Y3. As a reconstruction signal, the

Input signal x ₁ supplied. The output signal a

generated. The output signal and the handover signals are as follows

The additional signals used can be represented as logical functions or as signal links as follows. a ^(m1) = A ^(m1) (x ₂ , x ₁ );

b ^(m1) = B ^(ml) (x ₂ , x ₁ ) = A ^(m1) (x ₂ , x ₁ )

a ^(m2) = A ^(m2) (x ₂ , x ₁ );

b ^(m2) = B ^(m2) (x ₂ , x ₁ ) = A ^(m2) (x ₂ , x ₁ )

a ^(Y1) = b ^(Y1) = B a ^(Y2) = b ^(Y2) =

a ^(m1) a ^(m2) a ^(Y1) a ^(Y2)

 The output signal a can be represented by substitution and transformation as follows:; ;

 The output signal a can therefore be generated from the four

Transfer signals by using the two signals a ^(m1) and x ₁ to form reconstruction signals. It can be shown that the output signal a can also be generated by using three signals to form

Reconstruction signals.

Accordingly, the output signal can be generated using either two or three reconstruction signals. With the two reconstruction signals a ^(m1) and x ₁ , a multiplexer element MUX4 can be used, to which the signal a ^(m1) and the input signal x _{1 are} input as the least significant binary digit to control the selection. So there are three reconstruction signals three

 Reconstruction elements REK can be used. From a first stage consisting of the two reconstruction elements REK.Y1

and REK.Y2 the two transfer signals are generated By means of these transfer signals, the output signal is generated from a second stage consisting of the reconstruction element REK.Y3 a = y

In a larger switching mechanism, for example, a logic signal in the form of a tuple of logic signals can be provided. For example, the link signal ml is a tuple of logical signals in the form of signal values, for example a truth table. Transfer signals form tuples of logic signals according to the invention. For example, the tuple of the two transfer signals and

corresponds according to the invention to the logical signal a ^(m1) ,

which is generated for example in the test circuit TEST2. The tuple of the two transfer signals and corresponds

a logic signal a ^(m1) which is not generated anywhere in the circuit of FIG. 17 and which can be generated from these two transfer signals using the input signal x ₁ as a reconstruction signal. For example, that corresponds

 Output signal a following tuple of transfer signals

y [[As already explained, the output signal can be generated from this tuple using the input signal x ₁ and the signal a ^(m1) to form reconstruction signals in accordance with

x As already explained, the output signal can also be extracted from this tuple using the

Input signals x ₁ and the transfer signals and for

 Generation of reconstruction signals according to:

(

 There is a reconstruction element in the test circuit TEST2

REK.M1 provided. The transfer signals and

 train

leads. The input signal x _{1 is used as the} reconstruction signal. The logical signal a ^{(m1) is} generated by means of a multiplexer element MUX4 as a reconstruction element REKON. This will be the handover signals

) fed. As the lowest

Control signal, the logic signal a ^{(m1) is} supplied. The input signal x _{1 is} supplied as the higher-order control signal. ^(Y3)

The test signal t is generated. An EXOR logic element EXOR is provided. The output signal a and the test signal t ^{(Y3) are} fed to this. It will be a

Error signal ERR generated. An incorrectly generated output signal a or an incorrectly generated test signal t ^(Y3) is displayed if this error signal ERR is logically ONE.

It can thus be seen that due to the use of transfer signals according to the invention by means of a simple

 Test circuit TEST2 a generated output signal a can be checked.

The two circuit parts BB2.Y1 and BB2.Y2, as well as the two reconstruction elements REK.Y1 and REK.Y2 form one

Logic circuit M3Y3. These are the input signals signals a ^(m1) and a ^(m2), each in the form of two

 Transfer signals entered. This is the tuple

the tuple for entering the signal a ^(m1) and for entering the signal a ^(m2) Can be specified as a variable

The logic signal m3 is fed to the logic circuit M3Y3. From the two input tuples of transfer signals for a ^(m1) and a ^(m2) , the logic circuit M3Y3 generates a further tuple of two transfer signals for outputting output signal a. This is the tuple of these two hand signals

each generated independently by its own logic circuit M3Y1 and M3Y2. The logic circuit M3Y1 consists of the circuit part BB2.Y1 and the reconstruction element REK.Y1. It becomes from the two handover signals ) and According to the variably predetermined signal linkage of the linkage signal m3, the transfer signal generated: ⁽ The logic circuit M3Y2 consists of the circuit part BB2.Y2 and the reconstruction element REK.Y2. It is made up of the two transfer signals and (rr2) the transfer signal () according to the variably specified signal linkage of the linkage signal m3 generates y the linkage of

two tuples of the logic circuit M3Y3 Transfer signals for a ^(m1) and a ^(m2) to generate the output tuple of transfer signals for a = A ^(m3) (a ^(m2) , s ^(m1) ); thus takes place in such a way that for each position in the tuple the transfer signal to be generated is a signal link according to the link signal m3 from the respective input transfer signals

=

 This logic circuit M3Y3 can be used, for example, in a switching mechanism whose signals to be linked are only provided in the form of tuples of transfer signals. In this case, the transfer signals and generated by the logic circuit M3Y3 are to be checked, for example

 to check the logic circuits M3Y1 and M3Y2. FIG. 18 shows a fourteenth circuit for generating logical transfer signals in accordance with a variably predeterminable signal combination. It is an evolution of the

 Logic circuit M3Y3 shown. As with that logic circuit M3Y3 of Figure 17, the two are

 Linking circuits M3Y1 and M3Y2 provided which

 have already been explained with reference to FIG. 17. Just like with

Figure 17, the handover signals

and the link signal m3 supplied. In addition, the input signal x _{1 is} supplied to the logic circuit M3Y3. 18 two additional test circuits TEST3.Y1 and TEST3.Y2 are provided. These are structured the same way and each consist of five

 Reconstruction elements REK.A, REK.B, REK.C, REK.D, REK.E, as well as one EXOR link element EXOR.

The test circuit TEST3.Y1 is considered. the

 Reconstruction elements REK.A become the handover sionals

and as well as a reconstruction signal

Input signal x ₁ supplied. The signal a is generated. The reconstruction element REK.B is also supplied with the same two transfer signals, but in the reverse order, that is and y (). The signal b ^(m1) is thus generated. The transfer signals are sent to the reconstruction element REK.C. and y and the signal a ^{(m1) is} supplied as a reconstruction signal. A test signal t ^{(1) is} generated. The reconstruction element REK.D also receives the same two transfer signals, in the same order, that is y and and the signal b ^(m1) is called

 Reconstruction signal supplied. It will be another

⁽²⁾

Test signal t generated. The test signals are transmitted to the reconstruction element REK.E as transfer signals and

and the input signal x _{1 is} supplied as a reconstruction signal. Another test signal t ^{(Y1) is} generated. The EXOR logic element EXOR is the test signal t ^(Y1) and

Transfer signal fed. An error signal ERR.Y1 is generated. The linkage signal y is generated by the logic element M3Y1, according to y

 By definition:

 Therefore:

(>

The error signal ERR.Y1 thus results in an incorrectly generated transfer signal or an incorrectly generated test signal t ^{(Y1) is} displayed if this error signal ERR.Y1 is logically ONE.

The test circuit TEST.Y2 is considered. the

 Reconstruction element REK.A are the handover signals

and as well as a reconstruction signal

Input signal x ₁ supplied. The signal a ^{(m2) is} generated. The reconstruction element REK.B also receives the same two transfer signals, but in reverse order train led, so and it

the signal b ^(m2) is thus generated. The transfer signals are sent to the reconstruction element REK.C. and supplied, and as a reconstruction signal, the signal a ^(m2) is supplied. A test signal t is generated. The reconstruction element REK.D are also

if the same two transfer signals, in the same order, that is, and y and the signal b ^(m2) becomes as

 Reconstruction signal supplied. Another test signal is generated. In recon

structural element REK.E are as

Transfer signals the test signals and as well as

Reconstruction signal pulls the input signal x ₁ . Another test signal t ^{(Y2) is} generated. The test signal t ^(Y2) and the transfer signal are fed to the EXOR logic element EXOR. An error signal ERR.Y2 is generated. from

Logic element M3Y2 the transfer signal is generated,

 By definition:

 Therefore:

() () The error signal ERR.Y2 thus results in an incorrectly generated transfer signal y

an incorrectly generated test signal t ^(Y2) is displayed,

 this error signal ERR.Y2 is logically ONE.

FIG. 19 shows a fifteenth circuit for generating a logical signal in accordance with a variably predeterminable signal combination from five combination circuits MM0, MM1, MM2, MM3, MM4, and an additional test circuit TEST4. Link signals m1, m2, m3 are entered.

These consist of a tuple of four signals, which correspond to a truth table for signals a ^(m1) , a ^(m2) , a ^(m3) according to Table 18. Table 18

Accordingly, it is called a tuple {^ ^ of four signals entered the link signal ml. The signal a ^{(m1) can be} generated from these four signals by means of

a multiplexer element MUX4, to which the input signal x _{2 is} supplied as a low-order control signal, and the input signal x ₁ as a higher-order control signal. If, for example, both control ignals are logically ZERO, the signal (l)

according to the truth table of Table 16. The logic signal ml can also be represented as a four-digit number, the binary digits of which correspond to the logical signal values of these four signals in accordance with the truth table in Table 18. The signal ai is by definition used as the binary digit for 2 0. The signal is by definition used as the binary digit for 2 ¹ . The signal is by definition used as the binary number for 2. The signal a becomes

used by definition as a binary digit for 2 ³ . Binary digits are also defined in the same way for the link signals m2 and m3.

The signals and a will

the logic circuit MM0 supplied. Circuit part BB2.0 is provided. From this the signals and two handover signals and generated in accordance with the supplied link signal m3, as has already been explained with reference to FIG. 3. These transfer signals are one

Reconstruction element supplied REK.0. The signal is used as a reconstruction signal fed. A logical signal a _{0 is} generated, according to: a ₀ = y

The signals a and are the logic circuit

MM1 fed. A circuit part BB2.1 is provided. From this the signals and two handover

signals and generated according to the supplied

 Linking signal m3, as has already been explained with reference to FIG. 3. These transfer signals are one

Reconstruction element REK.1 supplied. The signal becomes the reconstruction signal train led. It becomes a logical one

Signal a ₁ generated according to: a ₁ - y

The signals and become the logic circuit

MM2 fed. A circuit part BB2.2 is provided. From this the signals and two handover

signals and generated according to the supplied

 Linking signal m3, as has already been explained with reference to FIG. 3. These transfer signals are one

Reconstruction element supplied REK.2. The signal is supplied as a reconstruction signal. It becomes a logical one

Signal a ₂ generated, according to: a ₂ =

The signals and become the logic circuit

MM3 supplied. A switch unit part BB2.3 is provided. From this the signals and two handover

 signals and generated according to the train

 Linking signal m3, as has already been explained with reference to FIG. 3. These transfer signals are one

Reconstruction element REK.3 supplied. The signal is supplied as a reconstruction signal. It becomes a logical one

Signal a ₃ generated, according to: a ₃ =

Accordingly, a tuple of four signals is generated, which represents the output signal a to be generated, according to: a = (a ₀ , a ₁ , a ₂ , a ₃ ); The output signal a could be generated from these four signals, for example by means of a multiplexer element MUX4, which has the input signal x ₂ as the low-value control signal and the input signal x ₁ as the higher-value control signal

is fed. These four signals a ₀ , a ₁ , a ₂ , a ₃ can therefore be used as a link signal for a. And they are also supplied to the logic circuit MM4 as a logic signal. The input signals x ₁ and x _{2 are also} fed to this. From a circuit part BB2.4 of the logic circuit MM4, the input signals x ₁ and x _{2 become} two transfer signals and generates link signals for a. These transfer signals and y as well

Reconstruction signal the input signal x ₁ are one

 Reconstruction element REK.4 can be fed to generate the

 Output signals a. As already explained, switching mechanisms are possible which each work instead of individual output signals by means of tuples of transfer signals. The generation of the

Output signal a by the reconstruction element REK.4 is not required in this application. This is in the figure

19 illustrated by dashed lines. In addition, the generated reconstruction signals and y can be checked, for example for applications in such a switching mechanism

are by means of an additional test circuit TEST4.

As FIG. 20 shows, such a test circuit TEST4 consists of a multiplexer element MUX4 and two

Test components TEST4Y1A and TEST4Y2A. These two test components TEST4Y1A and TEST4Y2A have the same circuit structure. Five reconstruction elements REK.A, REK.B, REK.C, REK.D, REK.E are provided, as well as one EXOR linking element EXOR. The multiplexer element MUX4 is supplied with the input signal x ₂ as the low-value control signal and the input signal x ₁ as the higher-value control signal. As to be selected

Signals become the signals as

Binary digits for 2 ³ , 2 ² , 2 ^1, 2 ^{0 of} the logic signal ml fed to a selection in that order. According to Table 18, the signal a ^{(m1) is} generated. The test components TEST4Y1A are considered. The transfer signals are sent to the reconstruction element REK.A. and

supplied, as well as a reconstruction signal

Input signal x ₂ supplied. A test signal t ^{(A1) is} generated. The transfer signals are sent to the reconstruction element REK.B. and and the input signal x _{2 is} supplied as a reconstruction signal. It will be a

Test signal t ^(B1) generated. The handover signals and

are also the reconstruction element REK.C but in reverse order, that is and fed, as well

the input signal x _{2 is} supplied as a reconstruction signal. A test signal t ^{(C1) is} generated. The test signals t ^(A1) and t ^{(B1 ) are} fed to the reconstruction element REK.D as transfer signals, and the signal a ^(m1) as a reconstruction signal. A test signal t ^{(D1) is} generated. The test signals t ^(D1) and t ^(C1) are supplied to the reconstruction element REK.E as transfer signals, and the input signal x _{1 is} supplied as a reconstruction signal. A test signal t ^{(E1) is} generated. The

EXOR logic element EXOR, the test signal t ^(E1) and the transfer signal are supplied. It will be an error signal

ERR.Y1A generated.

The test component TEST4Y2A is considered. The reconstruction element RE K. A will ignore the transfer

 and supplied, and as a reconstruction regional

the input signal x ₂ supplied. A test signal t ^{(A2) is} generated. The transfer signals and train are the reconstruction element REK.B.

e as well as a reconstruction

tion signal, the input signal x _{2 is} supplied. A test signal t ^{(B2) is} generated. The handover signals and

are the reconstruction element REK.C in um¬

reverse order, ie and fed, as well

the input signal x _{2 is} supplied as a reconstruction signal. A test signal t ^{(C2) is} generated. The test signals t ^(A2) are transmitted to the reconstruction element REK.D as transfer signals and t ^(B2) and as a reconstruction signal

Input signal a ^(m1) supplied. A test signal t ^{(E2) is} generated. The reconstruction element REK.E are as

Transfer signals the test signals t ^(D2) and t ^(C2) fed, and the input signal x _{1 is} fed as a reconstruction signal. A test signal t ^{(E2) is} generated. The

EXOR logic element EXOR, the test signal t ^(E2) and the transfer signal are supplied. It will be an error signal

 ERR.Y2A generated.

The transfer signals y and y are generated by the circuit element BB2.A of Figure 19 as follows

(A). _{1st 1} (A). _{1st 1}

 By definition:

a = (a ₃ , a ₂ , a ₁ , a ₀ ); b = (a ₀ , a ₁ , a ₂ , a ₃ );

 Therefore:

0, a ₁ , ₁ , ₀ ; ,,, 0 x ₁ x ₂ ) ₁ ( _{1 2} x ₁ ); ₃ ( _{1 1} ) ₂ (x _{1 1} ;

The signals a ₀ , a ₁ , a ₂ , a ₃ are from the logic circuits

MM0, MM1, MM2, MM3 generated by dsr Figure 19, according to:

() () 3

 By definition, according to table 18 applies

Therefore:

 Through the error signal ERP. Y1A thus becomes an incorrectly generated transfer design or an incorrectly generated one

(E1)

 Test signal t displayed if this error signal ERR. Y1A is logical ONE is also the same:

= (t ^(A2) .a ^(m1) + t ^(B2) . a ^(m1) ) ₁ + t ^(C2) .x ₁ =

= t ^(D2) . ₁ + t ^(C2) .x ₁ = t ^(E2) ;

The ERR.Y2A error regional thus results in an incorrectly generated transfer signal or an incorrectly generated test signal t ^(E2) is displayed if this error signal

ERR.Y2A is logically ONE.

As FIG. 21 shows, a sixteenth circuit for generating an output signal according to a variably specifiable signal combination consists of a multiplexing element MUX4 as a reconstruction block REKON, from which

Circuit components CORR and PBITS, so from one

Circuit block BB4, from which three input signals x ₁ , x ₂ , x _3, four transfer signals y ⁽¹⁾ , y ⁽²⁾ , y ⁽³⁾ , y ⁽⁴⁾ 'are generated in accordance with a supplied link signal m, wis this has already been explained, for example, with reference to FIG. 6 for the application K = 3 and N = 2. The circuit block BB4 consists of a circuit component ZWB, which the

Input signals x ₂ and x _{3 are} supplied, and which generates four intermediate signals z ₁ , z ₂ , z ₃ , z ₄ , each one

Circuit part UEB.1 and UEB.2 are supplied. The

Logic signal m consists of eight signals, the logical signal value of each a binary digit to represent the Link signal m corresponds to a binary number. The signals for the binary digits according to 2 ⁰ , 2 ¹ , 2 ² , 2 ³ are fed to the circuit part UEB.1. The signals for the binary digits according to 2 ⁴ , 2 ⁵ , 2 ⁶ , 2 ⁷ are fed to the circuit part UEB.2. The transfer signals y ⁽¹⁾ and y ^{(2) are} generated by the circuit part UEB.1. The transfer signals y ⁽³⁾ and y ^{(4) are} generated by the circuit part UEB.2. The input signals x ₁ , X ₂ , x ₃ and the logic signal m are fed to the circuit component PBITS. Three test signals p ⁽¹⁾ , p ⁽²⁾ , p ^{(3) are} generated.

The transfer signals y ⁽¹⁾ , y ⁽²⁾ , y ⁽³⁾ , y ⁽⁴⁾ and the three test signals p ⁽¹⁾ , p ⁽²⁾ , p ^{(3) are} fed to the circuit component CORR. There are four correctable transfer signals ^y generated.

These correctable handover signals

y are a form of representation for the output signal a ^(m) to be generated. As already explained, switching mechanisms are possible which work instead of output signals by means of transfer signals. The generation of the output signal a, for example by means of a multiplexer element MUX4, is not necessary in this application. This is illustrated in FIG. 21 by the dashed lines.

As shown in FIG. 22, there is the circuit component

 CORR from seven AND logic elements AND.1 to AND.7, from thirteen EXOR logic elements EX.1 to EX.13, and an OR logic element OR.ERR.

The transfer signals y ⁽³⁾ and y ^{(4) are} fed to the EXOR logic element EX.11. A signal e ^{(11) is} generated. The transfer signals y ⁽²⁾ and y ^{(4) are} fed to the EXOR logic element EX.12. A signal e ^{(12) is} generated. The

EXOR node EX.13, the transfer signals y ⁽²⁾ and y ^{(3) are} supplied. Sin signal e ^{(13) is} generated. The

EXOR logic element EX.8, the transfer signal y ⁽¹⁾ and the signal e ⁽¹¹⁾ supplied. A signal e ^{(8) is} generated.

The transfer signal y ⁽¹⁾ and the signal e ^{(12) are} fed to the EXOR logic element EX.9. The signal e ^{(9) is} generated. The EXOR logic element EX.10 will

Transfer signal y ⁽¹⁾ and the signal e ⁽¹³⁾ leads. The signal e ^{(10) is} generated. The signals generated can therefore be represented as follows:

e ⁽¹¹⁾ = y ⁽³⁾ ⊕ y ⁽⁴⁾ ;

e ⁽¹²⁾ = y ⁽²⁾ ⊕ y ⁽⁴⁾ ;

e ⁽¹³⁾ = y ⁽²⁾ ⊕ y ⁽³⁾ ;

e ^{(8) (1)} ⊕ e ^{(11) (1)} ⊕ y ⁽³⁾

= y = y ⊕ y ⁽⁴⁾ ;

e ^{(9) (1)} ⊕ e ^{(12) (1)} ⊕ y ⁽²⁾

= y = y ⊕ y ⁽⁴⁾ ;

e ^{(10) (1)} ⊕ e ^{(13) (1)} ⊕ y ⁽²⁾

= y = y ⊕ y ⁽³⁾ ;

The three signals form like Hamming coding

e ⁽⁸⁾ , e ⁽⁹⁾ , e ⁽¹⁰⁾ each have an EXOR combination of three of the four

Transfer signals. These three signals e ⁽⁸⁾ , e ⁽⁹⁾ , e ⁽¹⁰⁾ are compared with the three test signals p ⁽¹⁾ , p ⁽²⁾ , p ⁽³⁾

 Error detection as well as for error correction. It will

consequently provided that the test signals p ⁽¹⁾ , p ⁽²⁾ , p ⁽³⁾ are the same as the signals e ⁽⁸⁾ , e ⁽⁹⁾ , e ⁽¹⁰⁾ in the fault-free case;

e ⁽⁸⁾ = y ⁽¹⁾ ⊕ y ⁽³⁾ ⊕ y ⁽⁴⁾ = p ⁽¹⁾ ;

e ⁽⁹⁾ = y ⁽¹⁾ ⊕ y ⁽²⁾ ⊕ y ⁽⁴⁾ = p ⁽²⁾ ;

e ⁽¹⁰⁾ = y ⁽²⁾ ⊕ y ⁽²⁾ ⊕ y ⁽³⁾ = p ⁽³⁾ ;

The EXOR logic element EX.5 leads the test signal p ⁽¹⁾ and the signal e ⁽⁸⁾ . A differential signal q ^{(1) is} generated, which is logically ONE in the case of a

different logical signal values for the signal e ⁽⁸⁾ and for the test signal p ⁽¹⁾ , and otherwise the same logical

Is zero. The test signal p ⁽²⁾ and the signal e ^{(9) are} fed to the EXOR logic element EX.6. A difference signal q ^{(2) is} generated, which is logically ONE in the case of a

different local signal values for the signal e ⁽⁹⁾ and for the test signal p ⁽²⁾ , and otherwise the same logic

Is zero. The test signal p ⁽³⁾ and the signal e ^{(10) are} fed to the EXOR logic element EX.7. A difference signal q ^{(3) is} generated which is logically ONE in the case of a different logical signal value for the signal e ⁽¹⁰⁾ and the test signal p ⁽³⁾ , and is otherwise logically ZERO.

The three logic signals q ⁽¹⁾ , q ⁽²⁾ , q ^{(3) are} fed to the AND gate AND.1. A signal f ^{(1) is} generated, which is logically ONE in the event that all three

Difference signals q ⁽¹⁾ , q ⁽²⁾ , q ⁽³⁾ are logically ONE, and are otherwise logically ZERO. Particularly in the event that the transfer signal y ^{(1) has} an incorrect signal value, all three signals e ⁽⁸⁾ , e ⁽⁹⁾ , e ⁽¹⁰⁾ accordingly also have an incorrect signal value because this transfer signal y ⁽¹⁾ in an EXOR link in these three signals

e ⁽⁸⁾ , e ⁽⁹⁾ , e ^{(10) is} included. Accordingly, if the signal f ⁽¹⁾ is logically ONE, the transfer signal y ⁽¹⁾ obviously has an incorrect signal value, which can be corrected by means of the EXOR logic element EX.1 connected subsequently. The transfer signal y ⁽¹⁾ and the signal f ^{(1) are} fed to the EXOR logic element EX.1. It will be a correctable one

Transfer signal generated. This is the same

Signal value like the supplied transfer signal y ⁽¹⁾ if the signal f ⁽¹⁾ is logically ZERO. Otherwise, ie if the signal f ⁽¹⁾ is logically ONE, the correctable transfer signal has an inverted signal value of

supplied transfer signals y ⁽¹⁾ . The AND logic element AND.2 are the difference signals q ⁽²⁾ and q ⁽³⁾ at a non-inverting input and that

Differential signal q ⁽¹⁾ fed to an inverting input. A signal f ^{(2) is} generated, which is logically the same

ONE is in the case that the difference signals q ⁽²⁾ , q ⁽³⁾ are logically ONE, and the difference signal q ⁽¹⁾ is logically

Is zero. In particular in the event that the transfer signal y ^{(2) has} an incorrect signal value, the signals e ⁽⁹⁾ and e ⁽¹⁰⁾ accordingly also have an incorrect signal value because this transfer signal y ^{(2) is} in an EXOR combination is contained in these two signals e ⁽⁹⁾ and e ⁽¹⁰⁾ . If the signal f ⁽²⁾ is consequently logically ONE, the transfer signal y ⁽²⁾ obviously has an incorrect signal value, which can be corrected by means of the EXOR logic element EX.2 connected subsequently. In the EXOR link element

EX.2 the transfer signal y ⁽²⁾ and the signal f ^{(2) are} supplied. It becomes a correctable handover signal generated.

This correctable transfer signal has the same one

Signal value like the supplied transfer signal y ⁽²⁾ if the signal f ⁽²⁾ is logically ZERO. Otherwise, ie if the signal f ⁽²⁾ is logically ONE, the correctable transfer signal has an assigned signal value of the

led transfer signals y ⁽²⁾ .

The AND logic element AND.3 is supplied with the difference signals q ⁽¹⁾ and q ⁽³⁾ at a non-inverting input and the difference signal q ⁽²⁾ at an inverting input. A signal f ^{(3) is} generated which is logically ONE in the event that the difference signals q ⁽¹⁾ and q ⁽³⁾ are logically ONE and the difference signal q ⁽²⁾ is logically ZERO. Particularly in the event that the transfer signal y ^{(3) has} an incorrect signal value, the signals e ⁽⁸⁾ and e ⁽¹⁰⁾ accordingly also have an incorrect signal value

Signal value on because this transfer signal y ⁽³⁾ in one

EXOR linkage is contained in these two signals e ⁽⁸⁾ and e ⁽¹⁰⁾ . Accordingly, if the signal f ⁽³⁾ is logically ONE, the transfer signal y ⁽³⁾ apparently has

an incorrect signal value which can be corrected using the EXOR logic element EX.3 connected below. The transfer signal y ⁽³⁾ and the signal f ^{(3) are} fed to the EXOR logic element EX.3. It will be a

correctable transfer signal generated. Correct this

bare transfer signal has the same signal value as

the supplied transfer signal y ⁽³⁾ if the signal f ⁽³⁾ is logically ZERO. Otherwise, that is, if the signal f ⁽³⁾ is logically ONE, the correctable transfer signal has an inverted signal value of the train

Transfer signals y ^{(3 (} . The AND logic element AND.4 are supplied with the difference signals q ⁽¹⁾ and q ⁽²⁾ at a non-inverting input and the difference signal q ⁽²⁾ at an inverting input. A signal f ^{(4) is} generated which is logically ONE in the event that the difference signals q ⁽¹⁾ and q ⁽²⁾ are logically ONE and the difference signal q ⁽³⁾ is logically

Is zero. Particularly in the event that the transfer signal y ^{(4) has} an incorrect signal value, the signals e ⁽⁸⁾ and e ⁽⁹⁾ accordingly also have an incorrect signal value because this transfer signal y ^{(4) has} an EXOR operation in them two signals e ⁽⁸⁾ and e ^{(9) is} included. If the signal f ⁽⁴⁾ is therefore logically ONE, then the transfer signal y ⁽⁴⁾ obviously has an incorrect signal value, which can be corrected by means of the EXOR logic element EX.4 connected subsequently. The transfer signal y ⁽⁴⁾ and the signal f ^{(4) are} fed to the EXOR logic element EX.4. A correctable transfer signal y er

testifies. This correctable transfer signal y has one

same signal value as the supplied transfer signal y ⁽⁴⁾ if the signal f ⁽⁴⁾ is logically ZERO. Otherwise, ie if the signal f ⁽⁴⁾ is logically ONE, the correctable transfer signal y has an inverted signal value of

supplied transfer signal s y ⁽⁴⁾ .

The AND logic element AND.5 is supplied with the difference signal q ⁽¹⁾ at a non-inverting input and the difference signals q ⁽²⁾ and q ⁽³⁾ at an inverting input. A signal f ^{(5) is} generated which is logically ONE in the event that the difference signal q ⁽¹⁾ is logically the same

ONE and the difference signals q ⁽²⁾ and y ^{(3) are} equally logical

Are zero. For example, if the test signal p ^{(1) has} an incorrect signal value, this occurs. It can also be the case, for example, that the two transfer signals y ⁽¹⁾ and y ⁽²⁾ each have an incorrect signal value. This

Cases cannot be distinguished, and none occur

Correction of the handover signals.

The AND gate AND.6 are the difference signal q ⁽²⁾ on a non-inverting input and dis difference signals q ⁽¹⁾ and q ⁽³⁾ fed on an inverting input. A signal f ^{(6) is} generated, which is logically ONE in the event that the difference signal q ⁽²⁾ is logically the same

Is ONE and the difference signals q ⁽¹⁾ and q ⁽²⁾ are logically ZERO. For example, if the test signal y ^{(2) has} an incorrect signal value, this occurs. It can also be the case, for example, that the two transfer signals y ⁽¹⁾ and y ^{(3) have} an incorrect signal value. These cases cannot be distinguished and there is no correction of the transfer signals.

The AND logic element AND.7 are supplied with the difference signal q ⁽³⁾ at a non-inverting input and the difference signals q ⁽¹⁾ and q ⁽²⁾ at an inverting input. A signal f ^{(7) is} generated, which is logically ONE, in the event that the difference signal q ^{(3) is the} same

is logically ONE, and the difference signals q ⁽¹⁾ and q ⁽²⁾ are logically ZERO. For example, if the test signal p ^{(3) has} an incorrect signal value, this occurs. It may also be the case, for example, that the two transfer signals y ⁽¹⁾ and y ^{(4) have} an incorrect signal value. These cases cannot be differentiated and the transmission signals are not corrected.

The signals f ⁽¹⁾ , f ⁽²⁾ , f ⁽³⁾ , f ⁽⁴⁾ , f ⁽⁵⁾ , f ⁽⁶⁾ , f ^{(7) are} fed to the OR logic element OR.ERR. It will be a

Error signal ERR generates, which is logically ONE, if at least one of these routed signals is logically ONE. This error signal indicates in this way that in particular at least one of the supplied transfer signals y ⁽¹⁾ , y ⁽²⁾ , y ⁽³⁾ , y ⁽⁴⁾ or test signals p ⁽¹⁾ , p ⁽²⁾ , p ^{(3 ) has} an incorrect signal value. An incorrect signal value from a single one of these supplied signals y ⁽¹⁾ , y ⁽²⁾ , y ⁽³⁾ , y ⁽⁴⁾ , P ⁽¹⁾ , P ⁽²⁾ , P ⁽³⁾ can thus be coped with can be corrected and it can be correct

Transfer signals y, y, y, y are passed on. As FIG. 23 shows, the circuit component PBITS has three multiplier elements MUX8.1, MUX8.2, MUX8.3, as three

Reconstruction blocks REKON.1, REKON.2, REKON.3, and four EXOR logic elements EXOR.1, EXOR.2, EXOR.3, EXOR.4, and two AND logic elements AND.1 and UND.2.

The test signals p ⁽¹⁾ , p ⁽²⁾ , p ^{(3) are} generated. The input signals x ₁ , x ₂ , x _{3 are} supplied. It will

Linking signal m supplied, which, according to a binary number for m, consists of signals for representing the binary digits for 2 ⁷ , 2 ⁶ , 2 ³ , 2 ² , 2 ¹ , 2 ⁰ . These binary digits correspond to the logical signal values for a ₇ , a ₆ , a ₅ , a ₄ , a ₃ , a ₂ , a ₁ , a ₀ for the output signal a.

By definition, the four transfer signals are generated, y ⁽¹⁾ = ₁ x ₂ x ₂ x ₁ ; y ⁽²⁾ ₁ x ₂ x ₁ ;

y ⁽³⁾ = ax ₂ x ₁ + bx ₂ x ₁ ; y ⁽⁴⁾ = ax ₂ x ₁ + bx ₂ x ₁ ;

a = A ₃ , x ₂ , ₁ ; ₃ , x ₂ , x ₁ ) (x ₃ , x ₂ , x ₁

 For signals a and b, the truth table is as shown in Table 19.

Table 19

The three test signals are generated in accordance with:

p ⁽¹⁾ = y ⁽⁴⁾ ⊕ y ⁽³⁾ ⊕ y ⁽¹⁾ ; p ⁽²⁾ = y ⁽⁴⁾ ⊕ y ⁽²⁾ ⊕ y ⁽¹⁾ ;

p ⁽³⁾ = y ⁽³⁾ ⊕ y ⁽²⁾ ⊕ y ⁽¹⁾ ;

 thus the following applies:

y ⁽¹⁾ = ⁽⁾

y ⁽²⁾ =

y ⁽³⁾ =

y ⁽⁴⁾ =

 As a result, Table 20 is the truth table.

Table 20

The signals a ₀ and a _{3 are} linked by the EXOR logic element EXOR.4. The signal generated is used as a signal and the multiplexer element MUX8.1, as well as a signal and fed to the multiplexer element MUX8.3. The signals a ₁ and a _{0 are} linked by the EXOR logic element EXOR.3. The signal generated here is called the signal and the

Multiplexer element MUX8.1, as well as additional signal and (3)

 fed to the multiplexer element MUX8.3. From

EXOR logic element EXOR.2, the signals a ₄ and a _{7 are} linked. The signal generated in the process is called a signal fed to the multiplexer element MUX8.2. from

EXOR logic element EXOR.1, the signals a ₅ and a _{6 are} linked. The signal generated in this case is fed as a signal to the multiplexer element MUX8.2. from

AND logic element AND.2 becomes the signal a ₅ supplied to an inverting input, ie ₅ and the signal a ₆ fed to a non-inverting input. The signal generated in each case is called a signal the

 Multiplexer element MUX8.2 supplied. From the AND gate

AND.1 that is fed to an inverting input

Signal a ₄ , so , and this on a non-inverting

Input signal a ₇ linked. The signal generated in this case is called signal p ⁽⁾

the multiplexer element

MUX8.2 leads. The signal a ₇ becomes the multiplexer element

MUX8.1 trains the signal ⁽⁾ and p ⁽¹⁾

a ₆ is fed to the multiplexer element MUX8.1 as signal p ⁽¹⁾

and ⁽¹⁾ . The signal a ₅ is the

Multiplier element MUX8.3 each supplied as a signal A and ⁽³⁾ . The signal a ₄ is the multiplexer element MUX8.3

each leads as a signal ⁽³⁾

and P (3)

The signal a ₁ is fed to the multiplexing element MUX8.2 as a signal

⁽²⁾

and p The signal a ₀ becomes the multiplexer element

MUX8.2 pulls as signal ⁽²⁾

and P ⁽²⁾

Each multiplexer element MUX8.1, MUX8.2, MUX8.3

the three input signals x ₁ , x ₂ , x ₃ each supplied as

 Control signals for selecting one of the signals supplied.

The input signal x _{1 is used} as the most significant control signal. The input signal x ₃ is considered the lowest quality control signal used. The multiplexer element MUX8.1 depends on table 20 as a truth table

signal values of the input signals x ₁ , x ₂ , x ₃ as the control signals one of the supplied signals p ₀ ⁽¹⁾ , p ₁ ⁽¹⁾ , p ₂ ⁽¹⁾ , p ₃ ⁽¹⁾ , p ₄ ⁽¹⁾ , p ₅ ⁽¹⁾ , p ₆ ⁽¹⁾ , p ₈ ⁽¹⁾ , selected and subsequently forwarded as generated test signal p ⁽¹⁾ .

According to Table 20, the multiplexer element MUX8.2 is used as

Truth table depending on the signal values of the

Input signals x ₁ , x ₂ , x ₃ as dis control signals one of the supplied signals p ₀ ⁽²⁾ , p ₁ ⁽²⁾ , p ₂ ⁽²⁾ , p ₃ ⁽²⁾ , p ₄ ⁽²⁾ , p ₅ ⁽²⁾ , p ₆ ⁽²⁾ , p ₇ ⁽²⁾ , selected and subsequently forwarded as generated test signal p ⁽²⁾ . According to Table 20, the multiplexer element MUX8.3 as the truth table depends on the signal values of the input signals x ₁ , x ₂ , x ₃ as the

Control signals one of the supplied signals p ₀ ⁽³⁾ , p ₁ ⁽³⁾ , p ₂ ⁽³⁾ , p ₃ ⁽³⁾ , p ₄ ⁽³⁾ , p ₅ ⁽³⁾ , p ₆ ⁽³⁾ , p ₇ ^{(3) is} selected and subsequently passed on as generated test signal p ⁽³⁾ . In the event that the predeterminable signal combination is not provided as a variable combination signal m, but instead is programmed in a fixed manner, for example as already explained with reference to FIGS. 10, 12, 13, 14, then, for example, permanently programmed signal values can be supplied to the inputs to the multiplexer elements which are known from the table 20 as truth tables for p ⁽¹⁾ , p ⁽²⁾ , p ⁽³⁾ .

24 shows a circuit component PBITS1 for such an application. The signals to are generated by means of a circuit connection at points P1.0 to P1.7 as logic ZERO or logic ONE according to

Truth table for P1 of the respective application. The signals) to 4 (2) are by means of a Sch

old connection at points P2.0 to P2.7 generated as logical ZERO or logical ONE according to the truth table for p (2) of the respective application. The signals A to 4 are by means of a circuit connection at points P3.0 to P3.7 as logical ZERO or logical ONE generated according to the truth table for p ^{(3) of} the respective application.

For example, for the application already explained with reference to FIG. 14, the following signal values of its truth table apply to signal a ₍₁₎ from FIG. 14.

a ₍₁₎ = (0, 0, 0, 1, 0, 1, 1); Thus, if these signal values for (a ₇ , a ₆ , a ₅ , a ₄ , a ₃ , a ₂ , a ₁ , a ₀ ) are used in Table 20, then for test signals p ⁽¹⁾ , p ^{(2 )} , p ⁽³⁾ following signal values of their respective truth table

p ⁽¹⁾ = (0, 0, 0, 1, 1, 0, 0, 1);

p ⁽²⁾ = (0, 1, 0, 1, 1, 1, 1, 1);

p ⁽³⁾ = (1, 0, 0, 1, 1, 0, 0, 1);

This application is shown in FIG. 24.

For example, for the application also explained with reference to FIG. 14, the following signal values of its truth table apply to signal a ₍₂₎ from FIG. 14.

a ₍₂₎ = (0, 1, 1, 0, 1, 0, 0, 1); If these signal values are used in the same way for (a ₇ , a ₆ , a ₅ , a ₄ , a ₃ , a ₂ , a ₁ , a ₀ ) in table 20, then for test signals p ⁽¹⁾ , p ^{( 2)} , p ⁽³⁾ following signal values of their respective truth table p ⁽¹⁾ = (0, 1, 1, 0, 0, 0, 0, 0)

p ⁽²⁾ = (1, 1, 0, 0, 1, 0, 0, 1)

p ⁽³⁾ = (0, 1, 1, 0, 0, 0, 0, 0)

FIG. 25 shows a circuit component PBITS2 for this application, whose circuit connections at points P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7 are matched to this application.

Table 21 is intended to explain these two application cases. For better differentiation, the respective test signals are identified by an additional subscript as well as the signals a ₍₁₎ and a ₍₂₎ . Table 21

As FIG. 26 shows, the circuit components PBITS1 and PBITS2 which have just been explained can be used in a seventeenth circuit for generating two output signals from three input signals in accordance with programmable, hard-wired logic operations. As already explained with reference to FIG. 14, circuit block BB2F2 generates a tuple each of four transfer signals, from which each transfer signals a ₍₁₎ and a _{(2) can be} generated by means of a multiplexer element MUX4.1 and MUX4.2, respectively one reconstruction block each REKON.1 and REKON.2.

 For example with a rear derailleur, the one to be linked

Signals are only provided in the form of tuples of transfer signals, these two multiplexer elements MUX4.1 and MUX4.2 omitted. This is illustrated in FIG. 26 by the dashed lines. A circuit component CORR.1 and CORR.2 are provided for each of these tuples of transfer signals, which are constructed identically and are already explained with reference to FIGS. 21 and 22. These circuit components CORR.1 and CORR.2 are each supplied with three test signals which are generated by the circuit components PBITS1 and PBITS2 explained with reference to FIGS. 24 and 25.

The circuit component CORR.1 becomes the tuple of transfer signals The transfer signals are generated by the circuit block BB2F2, as already explained with reference to FIG. 14. The test signals are generated by the circuit component PBITS1 generated. These are routed to the circuit component CORR.1. As already explained with reference to FIGS. 21, 22, 23, the circuit component CORR.1 turns a tuple of correctable ones

Transfer signals y generated.

The output signal a _{(1) can be} generated from these. A single incorrectly generated signal can thus be handled, for example one of these transfer signals or test signals, without this leading to incorrectly generated correctable transfer signals.

The circuit component COFR.2 is supplied with the tuple of transfer signals p. These handover signals

are, as already explained with reference to FIG. 14, generated by the circuit block BB2F2. The test signals from the circuit component PBITS2 generated . These are fed to the circuit component CORR.2. As already explained with reference to FIGS. 21, 22, 23, the

 Circuit components CORR.2 a tuple of correctable

Transfer signals ) ( ) ( ) ( ) generated. The output signal a _{(2) can be} generated from these. A single incorrectly generated signal can thus be strengthened, for example one of these transfer signals or

Test signal without this leading to incorrectly generated correctable transfer signals. For the 1-bit full adder shown in FIGS. 14, 24, 25, 26, a tuple of correctable transfer signals can thus be generated, from which its output signals a ₍₁₎ and a _{(2) can be} generated. Even in the event that a single signal is incorrectly generated, this can still be coped with, so that it is nevertheless correctly generated

 correctable handover signals are given. Such sporadic or permanent errors cannot falsify a result.

Likewise, as has already been explained, for example, with reference to FIGS. 14, 24, 25, an arbitrarily predeterminable linkage of input signals in the form of correctable transfer signals can be provided, in which the circuit connections required for the respective linkage are programmably hard-wired.

As FIG. 27 shows, an eighteenth circuit for generating a logical output signal a consists of two

Input signals x ₁ , x ₂ from a circuit block BD2 and a reconstruction element REK, which has already been explained with reference to FIG. 1. The circuit block ED2 has two multiplexer elements MUX4.1, MUX4.2, which have already been explained with reference to FIG. 2. The circuit block BD2 also has a circuit part ZWA, which has already been explained with reference to FIG. 1. Finally, the circuit block BD2 also has a circuit part ZWE, which is already explained with reference to FIG. 3. The variably predeterminable signal link is entered as a link signal m, which is composed of four signals for entering binary digits for 2 ⁽³⁾ , 2 ⁽²⁾ , 2 ⁽¹⁾ , 2 ^{(0) of} a binary representation for

the link signal m, as has already been explained, for example, with reference to Table 2 and FIG. 1.

The input signal x _{1 is} fed to the circuit part ZWA to generate four intermediate signals according to 0 _d , 3 _d , 12 _d , 15 _d , as has already been explained with reference to FIG. 1. The input signals x ₁ and x _{2 are} fed to the circuit part ZWE to generate four intermediate signals according to 0 _d , 6 _d , 9 _d , 15 _d , as has already been explained with reference to FIG. 1.

The multiplexer element MUX4.1 is supplied with the intermediate signals of the circuit part ZWB according to 0 _d , 6 _d , 9 _d , 15 _d as multiplexer input signals. The signal for the binary digit 2 ^{(2) of} the linkage signal m is supplied as a low-value control signal. The signal for binary digit 2 ^{(0) of} the link signal m is supplied as a higher-order control signal. A transfer signal y ^{(1) is} generated as the multiplexer output signal. The multiplexer element MUX4.2 the intermediate signals of the circuit part ZWA according to 0 _d , 3 _d . 12 _d , 15 _d supplied as multiplexer input signals. The signal for the binary digit 2 of the logic signal m is supplied as a low-value control signal. As a higher-order control signal,

Signal for binary digit 2 ^{(3) of} the link signal m supplied. A transfer signal y ^{(2) is} generated as the multiplexer output signal.

The two multiplexer elements MUX4.1 and MUX4.2 form a subcircuit UED of the circuit block BD2.

The transfer signals y ⁽¹⁾ and y ^{(2) are} fed to the reconstruction element REK. This is called the reconstruction signal r

Input signal x ₂ supplied. The output signal a ^(m) becomes

consequently, a = y ⁽¹⁾ .x ₂ + y ⁽²⁾ generates in the following manner. ₂ ;

Table 22 shows the transfer signals y ⁽¹⁾ and y ^{(2) used} in each case for each of inputable link signals m. Table 22

In this application according to the invention, the following are

Reconstruction signals, scatter signals and arbitrary signals used:

r ⁽¹⁾ = (0, 1, 0, 1) = x ₂ = r;

r ⁽²⁾ = (1, 0, 1, 0) = x ₂ = ⁽¹⁾ = r;

s ⁽¹⁾ = (1, 0, 1, 0) = x ₂ = r ⁽²⁾ = r ⁽¹⁾

= ;

s ⁽²⁾ = (0, 1, 0, 1) = x ₂ = r ⁽²⁾ = r ⁽¹⁾

= r;

b ⁽¹⁾ = (a ₁ , a ₂ , a ₃ , a ₄ ) = A;

b ⁽²⁾ = (a ₃ , a ₄ , a ₁ , a ₂ ) = A;

 Accordingly, the following rule applies to the generation of

Transfer signals:

y ⁽¹⁾ = ar ⁽¹⁾ + b ⁽¹⁾ .s ⁽¹⁾ = ar + b ⁽¹⁾ . =

= A (x ₂ , x ₁ ) .x ₂ + =

= (a ₄ , a ₃ , a ₂ , a ₁ ). (0,1,0,1) + (a ₁ , a ₂ , a ₃ , a ₄ ). (1, 0, 1, 0) = = (0, a ₃ , 0, a ₁ ) + (a ₁ , 0, a ₃ , 0) = (a ₁ , a ₃ , a ₃ , a ₁ ); y ⁽²⁾ = ar ⁽²⁾ + b ⁽²⁾ .s ⁽²⁾ = ar + b ⁽²⁾ . =

= A (x ₂ , x ₁ ). + A ( ₂ , x ₁ ) .x ₂ =

= (a ₄ , a ₃ , a ₂ , a ₁ ). (1,0,1,0) + (a ₃ , a ₄ , a ₁ , a ₂ ). (0,1,0,1) = = (a ₄ , 0, a ₂ , 0) + (0, a ₄ , 0, a ₂ ) = (a ₄ , a ₄ , a ₂ , a ₂ );

Based on this rule for the formation of the transfer signals according to y ⁽¹⁾ = (a ₁ , a ₃ , a ₃ , a ₁ ); y ⁽²⁾ = (a ₄ , a ₄ , a ₂ , a ₂ ); Table 22 can be generated, from which the circuit of FIG. 27 can be derived.

FIG. 28 shows a further embodiment for one

 Circuit block BA2, which is already based on FIG. 1

is explained. Two identically constructed linking elements BA1.1 and BA1.2 are provided. Each of these logic elements BA1 has three AND logic elements AND.1, AND.2, AND.3, and an OR logic element OR. As already explained with reference to FIG. 1, the input signal x _{1 is} supplied to the circuit block BA2, which is supplied to each of the logic elements BAI in the circuit of FIG. As already explained with reference to FIG. 1, a logic signal m is input to the circuit block BA2, which is supplied in the form of four logic signals, the logic signal value of which corresponds to the binary digits for 2 ³ , 2 ² , 2 ¹ , 2 ⁰ from a binary representation of the logic signal m as a binary number. The logical signal values of these four signals, which the

Forming link signal m are by definition dis logical signal values for according to the truth

table for a ^(m) , as already explained with the help of tables, 1,2,3. As already explained with reference to FIG. 1, these four logic signals serve in the circuit part BA2 as control signals zg1, zg2 for the selection of a logic signal value for each of the two transfer signals generated by the circuit block BA2. It serves the signal for as low value

Control signal zg1.1 to select the logical signal value for the transfer signal y ⁽¹⁾ . It serves as the signal for as a higher-order control signal zg2.2, and the signal for as the low-value control signal zg1.2 for selecting the logical signal value for the transfer signal y ⁽²⁾ .

The following applies to the multiplexer element MUX4.0 from FIG. 1:

The following applies to the multiplexer element MUX4.1 from FIG. 1: It can be seen that the circuit block BA2 can be constructed so that the transfer signal y ⁽¹⁾ in the logic element

BA1.1 by means of three AND logic elements and one

OR logic element is generated, and that the transfer signal y ⁽²⁾ in the logic element BA1.2 by means of three

AND logic elements and an OR logic element is generated, with an identical circuit structure for the two logic elements BA1. This can be achieved by the signal the logic element BA1.1 as the higher-order control signal zg2.1 and as the lower-order control signal zg1.1 the signal is fed and by the signal the logic element BA1.2 as the higher-order control signal zg2.2 and as the lower-order control signal zg1.2

Signal is supplied. In each of the link elements

BA1, the input signal x _{1 is} fed to the AND logic element AND.1 at a non-inverting input and to the AND logic element AND.2 at an inverting input. The higher-order control signal zg2 is the AND gate AND.1 at an inverting input, the AND gate AND.2 at a non-inverting input, and the AND gate AND.3 at a non-inverting

Input fed. The lower-order control signal zg1 is supplied to the AND gate AND.1 at a non-inverting input, the AND gate AND.2 at an inverting input, and the AND gate AND.3 at a non-inverting input. The signals generated by the three AND logic elements AND.1, UND.2, AND.3 are fed to an OR logic element OR, which generates the transfer signal y of the logic element BA1.

Such a circuit block BA2 according to FIG. 28 can be used, for example, in switchgear, computing systems or even larger data processing systems, in which a tuple of transfer signals is used instead of individual signals. It is the linking element BA1, for example, relating to a signal delay for formation

a handover signal cheap. FIG. 29 shows a further embodiment for one

 Circuit block BB2, which is already based on FIG. 3

is explained. Two identically constructed logic elements BB1.1 and BB1.2 are provided. Each of these logic elements BB1 has five AND logic elements AND.1, AND.2, AND.3, AND.4, AND.5, and an OR logic element OR. As already explained with reference to FIG. 3, the input signals x ₁ and x _{2 are} fed to the circuit block BB2, which are fed to each of the logic elements BB1 in the circuit of FIG. As already explained with reference to FIG. 3, a logic signal m is sent to circuit block BB2

 entered, which is in the form of four logical signals

is supplied, the logical signal value of which corresponds to the binary digits for 2 ³ , 2 ² , 2 ¹ , 2 ⁰ from a binary representation of the

 Linking signal m as a binary number. The logical ones

Signal values of these four signals, which form the link signal m, are by definition the logical signal values for according to the truth table for a ^(m) , as already explained with the help of tables 1,2,3. As already explained with reference to FIG. 3, these four logic signals serve in the circuit part BB2 as control signals zg1, zg2 for the selection of a logic signal value for each of the two transfer signals generated by the circuit block BB2. It serves as the signal for as a low-order control signal zg1.1

Selection of the logical signal value for the transfer signal y ⁽¹⁾ .

It serves as the signal for as a higher-order control signal zg2.2, and the signal for ₃ as a low value

 Control signal zg1.2 to select the logical signal value for

( ²⁾

 the transfer signal y.

The following applies to the multiplexer element MUX4.0 from FIG. 3:

The following applies to the multiplexer element MUX4 1 from FIG. 3:

It can be seen that the circuit block BB2 can be constructed such that the transfer signal y ⁽¹⁾ in the logic element BB1.1 by means of five AND logic elements and one

OR logic element is generated, and that the transfer signal y ⁽²⁾ in the logic element BB1.2 by means of five

AND logic elements and an OR logic element is generated, with an identical circuit for the two logic elements BB1. This can be achieved by using the logic element BB1.1 dss signal as the higher value

Control signal zg2.1 and as the lower-order control signal zg1.1 the signal is supplied, and by the link

tion element BE2.2 the signal as the higher order control signal zg2.2 and as the lower order control signal zg1.2 the signal is fed. In each of the logic elements BB1, the input signal x ₁ becomes the AND logic element AND.1 at a non-inverting input, the AND logic element AND.2 at an inverting input, and the AND logic element AND.3 at a non-inverting input , and the AND gate AND.4 fed to an inverting input. In each of the logic elements BB1, the input signal x _{2 is} the AND logic element AND.1 at an inverting input, the AND logic element AND.2 at a non-inverting input, the AND logic element AND.3 at a non-inverting input, and the AND gate AND.4 fed to an inverting input. The higher-order control signal zg2 is applied to the AND gate AND.1 at an inverting input, the AND gate AND.2 at an inverting input, the AND gate AND.3 at a non-inverting input, the AND gate AND.4 a non-inverting Input, and the AND gate AND.5 fed to a non-inverting input. The lower-order control signal zg1 is the AND logic element AND.1 at a non-inverting input, the AND logic element AND.2 at a non-inverting input, the AND logic element AND.3 at an inverting input, the AND logic element AND .4 at an inverting input, and the

 AND logic element AND.5 on a non-inverting

 Input fed. The signals generated by the five AND logic elements AND.1, AND.2, AND.3, AND.4, AND.5 are fed to an OR logic element OR, which generates the transfer signal y of the logic element BB1. Such a circuit block BB2 according to FIG. 29 can be used, for example, in switchgear, computing systems or even larger data processing systems in which a tuple of transfer signals is used instead of individual signals. It is the link element BB1, for example, relating to a signal propagation time for formation

 a handover signal cheap.

Figures 29 and 18 are considered for considerations regarding signal propagation times. It is assumed that the two circuit parts BB2.Y1 and BB2.Y2 from FIG. 18 have been implemented according to FIG. Using the example of the logic circuit M3Y1 and the test circuit TEST3.Y1 in the following

 Signal propagation times examined. Both the subcircuit BB2.Y1 and the reconstruction elements REK.A and REK.B each use an inversion in succession, one

AND operation, and an OR operation. As a result, the signal propagation time is almost the same, so that the signals a ^(m1) , b ^{(m1) are} close

ezu are generated at the same time. The reconstruction element REK.Y1 also uses an inverse, an AND operation, and an OR operation in succession. Accordingly, it is advantageous if the test signal t ^{(Y1) is} almost simultaneously with the transfer signal

 is generated. In such an application, at

which is predominantly a modular circuit structure Reconstruction elements is less important than one

To achieve favorable signal propagation times, the reconstruction elements REK.C, REK.D, REK.E can therefore be replaced by a test element which also uses an inversion, an AND operation, and an OR operation in succession, so that for the test signal t ^{( Y1)} , as already explained with reference to FIG. 18, the following applies:

 = =

FIG. 31 shows such a test element TT3, which can be used instead of the reconstruction elements REK.C, REK.D, REK.E by the test component TEST3.Y1 as shown in FIG. The test element TT3 has four AND logic elements AND.1, AND.2, AND.3, AND.4 and an OR logic element OR. The input signal x ₁ is the AND gate AND.1 at a non-inverting input, the AND gate AND.2 at a non-inverting input, the AND gate AND.3 at an inverting input, and the AND gate AND. 4 leads to an inverting input. The signal a ^(m1) is fed to the AND gate AND.1 at a non-inverting input and to the AND gate AND.2 at an inverting input. The signal b ^(m1) is fed to the AND logic element AND.1 at a non-inverting input, and the AND logic element AND.2 at an inverting input. The signal y is the AND gate AND.1 on a non-inverting

Input, and the AND gate AND.3 leads to a non-inverting input. The signal y becomes the

AND gate AND.2 fed to a non-inverting input, and the AND gate AND.4 to a non-inverting input. The test signal t ^(Y1) is from

OR logic element OR generates from the four signals which are generated by the four AND logic elements AND.1, UND.2, UND.3, AND.4. Due to an identical circuit structure for the two test components TEST.Y1 and TEST3.Y2 from the

FIG. 18 is an identical modification of the circuit structure, as is already the case for the test component TEST3.Y1

is explained, also executable for the test components TEST3.Y2. The following reference character table is used in connection with the figures and in the description: ZERO logical signal, the truth table of which is consistent

 consists of logical signal values equal to logical 0, ONE logical signal, its truth table consistently

 consists of logical signal values equal to logical 1, ERR error signal, which is equal to ONE in the event of an error and otherwise equal to ZERO

 m link signal, for entering a veriatable

 Predeterminable signal linkage, for example consisting of several signals in the form of binary digits, which can be combined to form a binary number

 a output signal, output

 av intermediate output signal, which is used to generate

 of transfer signals is used

x input signal

y transfer signal

z intermediate signal

ze multiplexer input signal

zf multiplexer output signal

zg control signal, usable for a multiplexer element zh enable signal of a multiplexer element

r reconstruction signal, assigned to a transfer signal s scatter signal, assigned to a transfer signal

b Any signal, assigned to a transfer signal

t test signal, within test circuits

p Test signal, for the correction of transfer signals

q Difference signal, for correcting transfer signals f Signal for displaying an error which occurs in the

 Failure is equal to ONE, and otherwise equal to ZERO is another logic signal

 P, Q, R, S points for a programmable hardwired

 Circuit connection

 INV inverter

AND AND logic element

OR OR logic element

EXOR, EX EXOR logic element REK reconstruction element

RSA circuit element, for generating a

 Reconstruction signals

BA1, BB1 linking element, for generating a

 Transfer signals

MUX2, MUX4, MUX8, MUX16, MUXN, MUX2N, MUX4N

 Multiplexer element, for selecting one of train-guided signals according to control signal values

TT3 test element

 ZWA, ZWB, ZWC, CORR, PBITS, PBITS1, PBITS2, A, B1, B2, R1, R2, S1, S2, Y1, Y2

 Circuit component

TEST4Y1A, TEST4Y2A

 Test component

REKONS reconstruction part

UEA, UEB, UEC, UED

 Partial circuit

TEST1, TEST2, TEST3, TEST4

 Test circuit

M, MM, MM3Y1, MM3Y2, MM3Y3

 Linking circuit for generating a

 Output signals according to a local combination of input signals

REKS reconstruction circuit

REKON reconstruction block

 BA2, BA2F, BB2, BB4, BB2N, BB2F, BE2F2, BC2, BD2, BOOT2

 Circuit part, circuit block

Claims

Claims

1. Process for generating logical signals from

logical input signals so that a logical output signal can be generated by means of the signals, which corresponds to a logical signal combination of the input signal assigned to this output signal, with the following feature: a tuple ((y ⁽¹⁾ , ..., y ^(N) )), which one

 the output signal (a) which can be generated therefrom and this

Signal combination assigned to the output signal (A (x _K , ... x ₁ )) of the input signals (x _K ; k = 1, ... K) is assigned,

consisting of a number (N; 2 N /

2 ^K ) of logical

Transfer signals (y ⁽ⁿ⁾ ; n = 1, ... N) are generated (BA2, BA2F, BB2, BB4, BB2N, BB2F, BB2F2, BC2, BD2, BOOT2), which are generated

- That each of these transfer signals (y ⁽ⁿ⁾ ) one each

OR of one hand of an AND operation of the output signal (a) associated with the over Gabs signal (y ⁽ⁿ⁾⁾ respectively associated reconstruction signal (r ⁽ⁿ⁾⁾ and on the other hand, an AND operation of the transfer signal (y ⁽ⁿ⁾⁾ respectively Any signal (b ⁽ⁿ⁾ ) with one assigned to the transfer signal (y ⁽ⁿ⁾ )

Scattering signal (s ⁽ⁿ⁾ ) corresponds, in particular according to the following formula y ⁽ⁿ⁾ = ar ⁽ⁿ⁾ + b ⁽ⁿ⁾ .s ⁽ⁿ⁾ for n = 1, ... N,

- And that each AND operation of each of the reconstruction signals (r ⁽ⁿ¹⁾ ) with a different one

Reconstruction signals (r ⁽ⁿ²⁾ ) is always logically ZERO, in particular according to the following formula

r ⁽ⁿ¹⁾ .r ⁽ⁿ²⁾ = 0 for 1 n1 / n2 / N,

- and that an OR operation of all reconstruction signals (r ⁽ⁿ⁾ ; n = 1, ... N) is always logical ONE, especially according to the following formula r ⁽¹⁾ + r ⁽²⁾ + ... + r ^(N) = 1,

- And that each AND operation of one of the

Reconstruction signals (r ⁽ⁿ⁾ ) with the scatter signal (s ⁽ⁿ⁾ ) assigned to them are always logic ZERO, in particular according to the following formula r ⁽ⁿ⁾ .s ⁽ⁿ⁾ = 0 for n = 1, ... N, - So that the output signal (a) based on this tuple of the transfer signals by means of an OR operation of all

AND operations (REK, REKON, REKONS) of each of the transfer signals (y ⁽ⁿ⁾ ) with each of these transfer signals

(y ⁽ⁿ⁾⁾ associated reconstruction signal (r ⁽ⁿ⁾⁾ is in particular according to the following formula erzsugbar

a = y ⁽¹⁾ .r ⁽¹⁾ + y ⁽²⁾ .r ⁽²⁾ + ... + y ^(N) .r (N).

2. The method according to claim 1

characterized in that at least one of the transfer signals (y ⁽ⁿ⁾ ) can be generated (REK, REKS) in accordance with an OR operation of all AND operations of this transfer signal (y ⁽ⁿ⁾ ) associated with further logical reconstruction signals (r ^{(n, j )} ; j = 1, ... j) and a further tuple of further logical transfer signals (y ^{(n, j)} ) associated with this transfer signal, which are generated in this way,

- that each of the other transfer signals (y ^{(n, j)} ; j = 1, ... j) corresponds to an OR operation of two AND operations (y ^{(n, j)} = y ⁽ⁿ⁾ .r ^(nj) + b ^{(n, j)} .s ^{(n, j)} .

 j = 1, ... J), namely

on the one hand the assigned transfer signal (y ⁽ⁿ⁾ ), each with one of the further reconstruction signals (r ^{(n, j)} ), and on the other hand, another logical arbitrary signal (b ^{(n, j)} assigned to the further transfer signal (y ^{(n, j) )} ) associated with the further transfer signal (y ^{(n, j))} further logic scattering signal (s ^{(n, j)),} the AND operation with the further reconstruction signal (r ^{(n, j))} is always logical ZERO results especially according to the following Formula r (n, j) _.s (n, j) = 0 for j = 1, ... J,

 - And that each AND operation of one of the others

Reconstruction ^signals (r ^{(n, j1)} ) with a different one of the further reconstruction signals (r ^{(n, j2)} ) always logically ZERO results in particular according to the following formula

r ^{(n, j1)} .r ^{(n, j2)} = 0 for 1 / j1 / j2 / J,

- and that an OR operation of all the other logical reconstruction signals (r ^{(n, j)} ; j = 1, ... J) always results in a logical ONE, in particular according to the following formula r ⁽ⁿ ' ^J) + ... + r ^{(n, j)} + ... + r ^{(n, 1)} - 1,

 - and that each AND operation of one of the others

Reconstruction of signals (r ^{(n, j))} with the transfer signal (y ⁽ⁿ⁾⁾ associated reconstruction signal (r ⁽ⁿ⁾⁾ not logically for all combinations of input signal values to NULL in particular according to the formula r ⁽ⁿ⁾ .r ^{(n, j )} ≠ 0,

- So that the Ausgsbesignal (a) can be generated by means of a

OR link of all AND links of the mutually assigned reconstruction signals and transfer signals, with such an AND link for each of the further transfer signals (y ^{(n, j)} ), consisting of the further one

Transfer signal (y ^{(n, j)} ), the further reconstruction signal (r ^{(n, j)} ), and that reconstruction signal (r ⁽ⁿ⁾ ) which is assigned to the assigned transfer signal (y ⁽ⁿ⁾ ), in particular according to the following formula

a = y ^(N) .r ^(N) + ... + y ^{(n + 1)} .r ^{(n + 1)} +

+ y ^{(n, j)} .r ^{(n, j)} .r ⁽ⁿ⁾ + ... + y ^{(n, 1)} .r ^{(n, 1)} .r ⁽ⁿ⁾ +

+ y ^(n-1) .r ^(n-1) + ... y ⁽¹⁾ .r ⁽¹⁾ .

3. The method according to claim 2

characterized in that a transfer signal (y ⁽ⁿ⁾ ) can be generated (REKS) correspondingly continued

(i = 1, ... I) each further tuple of generated further (j = 1, ... j ⁽ⁱ⁾ ) transfer signals and others

 Reconstruction signals in particular according to the following formula

4. The method according to claim 3

characterized in that each of the transfer signals (y ⁽ⁿ⁾ ) of a primary tuple can be generated (REKS) continued (i = 1, ... I) corresponding to another

(j ⁽ⁱ⁾ = 1, ... J ⁽ⁱ⁾ ) tuples of generated further transfer signals and further reconstruction signals, in particular according to the following formula

5. The method according to at least one of claims 1 to 4 g e k e n n z e i c h n e t by inverted in pairs

Reconstruction signals in particular according to the following formula

6. The method according to at least one of claims 1 to 5 characterized by inverted scatter signals assigned to the reconstruction signals, in particular according to the following formula

7. The method according to at least one of claims 1 to 6 characterized by at least one Belisbig signal (b = A ( x _K , ... ₁ )), which corresponds to the logical combination of the output signal to be specified, but from at least one inverted input signal (BA2, BA2F, BE2, BB4, BB2N, BB2F, BC2, BD2).

8. The method according to at least one of claims 1 to 7 g e k e n n z e i c h n s t by at least one of the

Reconstruction signals (r ^{(j (1), ..., j (i))} = x _k ), which is equal to one of the input signals (BB2, BB4, BB2N, BB2F, BC2, BD2).

9. The method according to at least one of claims 1 to 8, characterized by at least one of the reconstruction signals (r ^{(j (1), ..., j (i))} = x _k1 ⊕ x _k2 .

1 k1 k2 = K), which is equal to an EXOR combination of two input signals (BA2, BA2F).

10. The method according to at least one of claims 1 to 9 characterized in that the transfer signals are generated at one location (BOOT2) and are transferred to another location where the output signal is generated from the transfer signals (REKONS).

11. The method according to at least one of claims 1 to 10, characterized in that the transfer signals are saved at one point in time (BOOT2), and that at another point in time the output signal is generated from the read out transfer signals (REKONS).

12. The method according to at least one of claims 1 to 11, characterized in that at least one transfer signal (y ⁽ⁿ⁾ ) is selected (UEA, UEB, UEC, UED) from such an offer of a number (J) of processed intermediate signals (z ^(j) ; j = 1, ... J), so that always one

AND linkage of the respective output signal (a) with that reconstruction signal (r ⁽ⁿ⁾ ) which is assigned to this transfer signal (y ⁽ⁿ⁾ ) is equivalent to an AND linkage of this reconstruction signal (r ⁽ⁿ⁾ ) with that one

Intermediate signals (z ^(j) .r ⁽ⁿ⁾ = ar ⁽ⁿ⁾ ), which as the

Transfer signal (y ⁽ⁿ⁾ = z ^(j) ) must be selected in each case.

13. The method according to at least one of claims 1 to 12, characterized in that for a further intended logical combination (V) of individual output signals (a _(i) ; i - 1, ... I) to form a linked output signal ( a _(V) = V (a _(I) , ... a ₍₁₎ )) with a tuple generated for each of the individual output signals (a _(i) ) of the same number (N ₍₁₎ = N _{( i)} = N) of

Handover signals; n = 1, ... N; i = 1, ... I), for which one

an identical reconstruction signal at the same position within the respective tuple = r ⁽ⁿ⁾ ; i = 1, ... I; n = 1, ... N) is assigned, another tuple of the same number (N) of linked further transfer signals n = 1, ... N) from the transfer

signals; n = 1, ... N; i = 1, ... I) is generated so that

 each of the linked handover signals accordingly

its position (n) in the tuple according to the intended logical link (V) but instead of the individual output signals (a _(i) ) from those transfer signals is generated, which in turn at the same position (s) in the tuple

n = 1, ... N) are provided (M3Y3, MM0, MM1, MM2, MK3).

14. Circuit for performing the method

according to one of claims 1 to 13

by a circuit block

(BA2, BB2, BB2N, BC2, BD2, BA2F, BB2F, BB2F2, BOOT2),

which at least one of a number (2nd K) from the

Input signals (x _k ; k = 1, ... K) is supplied,

and which of them at least one tuple ((y ⁽¹⁾ , ... y ^(N) )), which of the output signal (a) which can be generated therefrom and the signal combination associated with this output signal (a)

(a = A (x _K , ... x ₁ )) of the input signals (x _K ; k = 1, ... K)

is assigned (a = (y ⁽¹⁾ , ... y ^(N) )),

consisting of a number (N) of the transfer signals

(y ⁽ⁿ⁾ ; n = 1, ... N).

15. Circuit according to claim 14

characterized in that at least one circuit component (ZWA, ZWB, ZWC) is provided in the circuit block (BA2, BA2F, BB2, BB2F, BB2F2, BB2N, BC2, BD2) for processing at least one of offers of a number (3) of intermediate signals ( z ^(j) ; j = 1, ... J), for which an AND operation of one of these intermediate signals (z ^(j) ) with one of the reconstruction signals (r ⁽ⁿ⁾ ) is the same as an AND operation of this reconstruction signal ( r ⁽ⁿ⁾ ) with the output signal, in particular according to the following formula z ^(j) .r ⁽ⁿ⁾ = ar ⁽ⁿ⁾ .

16. Circuit according to claim 15

 due to the fact that the

 Circuit components (ZWA) prepared four intermediate signals (z1, z2, z3, z4), namely:

 - A first intermediate signal (z1), the

 Signal value is always logic ZERO (z1 = 0),

 - A second intermediate signal (z2), whose signal value is the same

one of the input signals is (z2 = x _K1 ),

 - A third intermediate signal (z3), the signal value for

second intermediate signal is inverted (z3 = 2 = _k1 ),

- A fourth intermediate signal (z4) whose signal value is inverted to the first intermediate signal (z4 = 1 = 1).

17. Circuit according to claim 15

 due to the fact that the

 Circuit component (ZWE) four intermediate signals (z1, z2, z3, z4) processed, namely:

 a first intermediate signal (z1), the signal value of which is always logically ZERO (z1 = 0),

 - A second intermediate signal (z2), the signal value of which is equal to an EXOR combination of two of the input signals

(z2 = x _k1 ⊕x _k2 = x _k1 x _{k2 +} x _k1 x _k2 ),

 - A third intermediate signal (z3), the signal value for

 second intermediate signal is inverted

(z3 = 2 = x _k1 f⊕ _k2 = x _k1 x _k2 + _{k1 k2} ),

 - A fourth intermediate signal (z4), the signal value of which is inverted from the first intermediate signal (z4 = z1 = 1).

18. Circuit according to claim 15

due to the fact that the

Circuit component (ZWC) sixteen intermediate signal

(z1, z2, z3, z4, z5, z6, z7, z8, z9, z10, z11, z12, z12, z14, z15, z0) prepared, namely:

- a first intermediate signal (z1), the signal value of which is equal to an AND operation of one of the input signals (x _k1 ) with an EXOR operation of two further of the input _signals (x _k2 , x _k3 ) (z1 = x _k1 . (x _k2 ⊕x _k3 ) = x _k1 x _{k2 k3} + x _{k1 k2} x _k3 ),

- A second intermediate signal (z2), the signal value of which is equal to an AND operation of one of the input signals (x _k1 ) with an inverted EXOR operation of the other two of the input _signals (x _k2 , x _k3 )

(z2 = x _k1 . (x _k2 ⊕ _k3 ) = x _k1 x _k2 x _k3 + x _{k1 k2 k3} ),

 a third intermediate signal (z3), the signal value of which is equal to an OR operation of the first (z1) and the second (z2) intermediate signal (z3 = z1 + z2),

 - A fourth intermediate signal (z4), whose signal value is equal to an AND operation from the inverted one of the

Input signals ( _k1 ) with an EXOR combination of the two other of the input _signals (x _k2 ⊕x _k3 )

(z4 = _k1 . (x _k2 ⊕ x _k3 ) = _k1 x _k2 x _k3 + _k1 x _k2 x _k3 ), a fifth intermediate signal (z5), the signal value of which is equal to an OR operation of the third (z3) and the second (z2) intermediate signal (z5 = z3 + z2),

- a sixth intermediate signal (z6), the signal value of which is the same

 an OR operation of the fourth (z4) and the second (z2) intermediate signal is (z6 = z4 + z2),

 a seventh intermediate signal (z7), the signal value of which is an OR operation of the fourth (z4) and the third (z3) intermediate signal (z7 = z4 + z3),

- an eighth intermediate signal (z8), the signal value of which is equal to the inverted seventh ( The intermediate signal is (z8 = .

- a ninth intermediate signal (z9), the signal value of which is equal to the inverted sixth ( ) Intermediate signal is (z9 =

- A tenth intermediate signal (z10) whose signal value is equal to the inverted fifth Intermediate signal is (z10 = .

- An eleventh intermediate signal (z11), the signal value of which is the inverted fourth The intermediate signal is (z11 =

- A twelfth intermediate signal (z12), whose signal value is equal to the inverted third ) Intermediate signal is (z12 = .

- A thirteenth intermediate signal (z13), the signal value

equal to the inverted second Intermediate signal is

(z13 =

 - A fourteenth intermediate signal (z14), the signal value

equal to the inverted he first ( Intermediate signal is

(z14 =

 a fifteenth intermediate signal (z15), the signal value of which is always logically ONE (z15 = 1),

 - a sixteenth intermediate signal (z0), the signal value of which is always logically ZERO (z0 = 0).

19. Circuit according to at least one of claims 15 to 18, characterized in that in the circuit block (BA2, BA2F, BB2, BB2F, BB2F2, BB2N, BC2, BD2) at least one circuit part (UEA, UEB, UEC, UED, UEF) is provided for generating at least one of the transfer signals (y ⁽ⁿ⁾ ) by means of a selection of one of the intermediate signals (z ^(j) ; j = 1,... J) dss prepared offer.

20. Circuit according to at least one of claims 14 to 19, characterized in that a variably predeterminable logic signal link, by means of which the

Output signal (a) can be extracted from the input signals (x _k ; k = 1, ... K), in the form of a link signal (m)

is entered, which is composed of a number (L + 1 = 2 ^K ) of logical signals, the signal value of which as binary digits of a truth table (Table 6) for the

Output signal (a ^(m) ) corresponds so that these signals can be used as control signals (zg).

21. Circuit according to claim 16, 19 and 20

characterized in that the circuit part (UEA) has two multiplexer elements (MUX4.0, MUX4.1), to each of which the four intermediate signals (z1, z2, z3, z4) of the circuit component (ZWA) are supplied as multiplexer input signals, and which as a control signal Enter two of four binary digits (2 ^{j + 3} , 2 ^{j +2} , 2 ^{j + 1} , 2 ^j ) of the link signal (m), with a most significant

(2 ^{j + 3} ) of these binary digits as a higher-order control signal and a least significant (2 ^j ) of these binary digits as a lower-order control signal for one of the multiplexer elements (MUX4.1), and with a higher-order (2 ^{j + 2} ) of the other two ( 2 ^{j + 2} , 2 ^{j + 1} ) of these binary digits as

higher-order control signal and a low-order (2 ^{j + 1} ) of these two remaining (2 ^{j + 2} , 2 ^{j + 1} ) of these binary digits as a low-order control signal for the other of the

Multiplexer element (MUX4.0).

22. Circuit according to claim 17, 19 and 20

characterized in that the circuit part (UEB) has two multiplexer elements (MUX4.0), MUX4.1), to which the four intermediate signals (z1, z2, z3, z4) of the circuit component (ZWB) are fed as multiplexer input signals, and which as Control signals two each of four binary digits (2 ^{j + 3} , 2 ^{j + 2} , 2 ^{j + 1} , 2 ^j ; j = 2 ²ⁱ ; 0 i) the link signal (m) are entered with a

most significant (2 ^{j + 3} ) of these binary digits as the higher-order control signal and one most significant (2 ^{j + 2} ) of the remaining three (2 ^{j + 2} , 2 ^{j + 1} , 2 ^j ) of these binary digits as the low-order control signal for one of the multiplexer elements (MUX4 .1), as well as with a higher value (2 ^{j + 1} ) of the remaining two (2 ^{j + 1} , 2 ^j ) of these binary digits as a low value control signal and a lower value (2 ^j ) of these two remaining ones

(2 ^{j + 1} , 2 ^j ) of these binary digits as a higher-order control signal for the other of the multiplexer elements (MUX4.0).

23. Circuit according to claim 22

Due to the fact that the

Circuit block (BB2N) has the circuit component (ZWB) and a number (N) of the circuit parts (UEB.n; n = 1, ... N), which each have the four intermediate signals (z1, z2, z3, z4) of the circuit components (ZWB) and four of the binary digits (2 ^{j + 3} , 2 ^{j + 2} , 2 ^{j + 1} , 2 ^j ; j = 4 (n - 1); n = 1, ... N) of the link signal (m ) are fed.

24. Circuit according to claim 16, 17, 19 and 20

 due to the fact that the circuit block (BD2) has two circuit components (ZWA, ZWB), each of which generates four intermediate signals, and a circuit part (UED) which has two multiplexer elements (MUX4.1,

MUX4.2), with the four intermediate signals (0 _d , 6 _d , 9 _d , 15 _d ), which are generated by one of the circuit components (ZWB) and which are supplied to one of the multiplexer elements (MUX4.1) as Multiplexer input signals, as well as with the four intermediate signals (0 _d , 3 _d , 12 _d , 15 _d ), which are generated by the other of the circuit components (ZWA) and which are fed to the other of the multiplexer elements (MUX4.2) as multiplexer input signals, as well with a higher quality

Control signal for one of the multiplexing elements (MUX4.2) as a most significant binary digit of four binary digits (2 ³ , 2 ² , 2 ¹ , 2 ⁰ ) of the logic signal (m) supplied to the circuit part (UED), and with a higher-order control signal for the other of the multiplexer elements (MUX4.1) as a least significant binary digit (2 ⁰ ) of the four supplied binary digits (2 ³ , 2 ² , 2 ¹ , 2 ⁰ ) of the combination signal (m), and with a low-order control signal for one of the Multiplexer elements (MUX4.2) as a lower-value binary digit (2 ¹ ) of the two remaining binary digits (2 ² , 2 ¹ ) of the link signal (m), and with a low-value control signal for the other of the multiplexer elements (MUX4.1) than a higher-order binary digit (2 ² ) of these two remaining binary digits (2 ² , 2 ¹ ) of the link signal (m).

25. Circuit according to claim 14 and 20

characterized in that the circuit block (BA2) has at least one logic element (BA1) which has a first, a second, a third AND logic element (AND.1, AND.2, AND.3) and an OR logic element (OR) has, with one of the input signals (x _k ), which is fed to the first AND gate (AND.1) at a non-inverting input and the second AND gate at an inverting input, and with one of the control signals (zg2 ), which the first AND gate (AND.1) at an inverting input, the second AND gate (AND.2) at a non-inverting input, and the third AND gate (AND.3) at a non-inverting input is supplied, as well as with a further one of the control signals (zg1), which the first

AND gate (AND.1) at a non-inverting input, the second AND gate (AND.2) at an inverting input, and the third AND gate (AND.3) at a non-inverting input, and with one of the transfer signals (y), which from the

OR logic element (OR) is generated from this

supplied signals, which are generated by the three AND logic elements (UND.1, UND.2, UND.3).

26. Circuit according to claim 14 and 20

characterized in that the circuit block (BB2) has at least one logic element (BE1) which has a first, a second, a third, a fourth, a fifth AND logic element (AND.1, AND.2, AND.3, AND. 4, AND.5) and an OR gate (OR), with one of the input signals (x _k1 ), which the first AND gate (AND.1) at a non-inverting input, the second AND gate (AND .2) is fed to an inverting input, the third AND gate (AND.3) to a non-inverting input, and the fourth AND gate (AND.4) to an inverting input, and to another of the input signals ( x _k2 ), which the first AND gate (AND.1) at an inverting input, the second AND gate (AND.2) at a non-inverting input, the third AND gate (AND.3) at a non-inverting Input, and the fourth AND Ve logic element (AND.4) is fed to an inverting input, and with one of the control signals (zg2), which is connected to the first AND logic element (AND.1) at an inverting input, the second AND logic element (AND.2) an inverting input, the third AND gate (AND.3) at a non-inverting input, the fourth AND gate (AND.4) at a non-inverting input, and the fifth AND gate (AND.5) at a non inverting input is supplied, as well as with another of the control signals (zg1), which is the first

AND gate (AND.1) at a non-inverting input, the second AND gate (AND.2) at a non-inverting input, the third AND gate (AND.3) at an inverting input, the fourth

AND gate (AND.4) at an inverting input, and the fifth AND gate (AND.5) at a non-inverting input, and with one of the transfer signals (y), which is provided by the OR gate (OR) is generated from the signals supplied to it, which are generated by the five AND logic elements (AND.1, AND.2, AND.3, AND.4, AND.5).

27. Circuit according to claim 14 and 20 and at least one of claims 25 or 26

characterized in that the circuit block (BB2N) has at least one circuit part (BB2), which two of the input _signals (x _{k 1} , x _k2 ) and four of the

Control signals (zg1, zg2, zg3, zg4) are supplied.

28. Circuit according to claim 27 and 26

characterized in that the circuit part (BB2) has a first and a second logic element (BB1), with a higher-order control signal for the second logic element (BB1.2) equal to a least significant (zg1) of the four control signals (BE2) supplied to the circuit part (BE2) zg1, zg2, zg3, zg4), as well as with a lower value

Control signal for the second logic element (BB1.2) is equal to a next higher value (zg2) of the four control signals (zg1, zg2, zg3, zg4) supplied to the circuit part (BB2), as well as with a low quality control signal for the first logic element (BB1.1) equal to a next higher value (zg3) of the four control signals (zg1, zg2, zg3, zg4) supplied to the circuit part (BE2), as well as a higher value control signal for the first logic element (BB1.1) equal to a most significant (zg4) of the four the Circuit part (BB2) train-controlled control signals (zg1, zg2, zg3, zg4).

29. Circuit according to at least one of claims 14 to 28 characterized by the fact that the generated

 Output signal (a) is checked in a test circuit (TEST1, TEST2).

30. Circuit according to at least one of claims 14 to 29, characterized in that the transfer signal (y) generated in a test circuit

(TEST3, TEST4) are checked.

31. Circuit according to at least one of claims 14 to 30 characterized in that the generated transfer signals (y) can be corrected in a circuit component (CORR).

32. Circuit according to claim 31

thereby, the transfer signals (y) can be corrected in accordance with test signals (p) which are generated by a circuit component (PBITS, PBITS1, PBITS2).