EP0529718A1 - Digitales Nachrichtenübertragungssystem mit verketteten Koden und in diesem System angewandter Empfänger und Dekodierer - Google Patents

Digitales Nachrichtenübertragungssystem mit verketteten Koden und in diesem System angewandter Empfänger und Dekodierer Download PDF

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EP0529718A1
EP0529718A1 EP92202524A EP92202524A EP0529718A1 EP 0529718 A1 EP0529718 A1 EP 0529718A1 EP 92202524 A EP92202524 A EP 92202524A EP 92202524 A EP92202524 A EP 92202524A EP 0529718 A1 EP0529718 A1 EP 0529718A1
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des
moyens
une
code
les
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EP92202524A
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English (en)
French (fr)
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EP0529718B1 (de
Inventor
Khaled Société Civile S.P.I.D. Fazel
Antoine Société Civile S.P.I.D. Chouly
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Laboratoires dElectronique Philips SAS
Koninklijke Philips NV
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Laboratoires dElectronique Philips SAS
Philips Gloeilampenfabrieken NV
Koninklijke Philips Electronics NV
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0054—Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
    • G11B20/1833—Error detection or correction; Testing, e.g. of drop-outs by adding special lists or symbols to the coded information
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
    • H03M13/253—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with concatenated codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0047—Decoding adapted to other signal detection operation
    • H04L1/0048—Decoding adapted to other signal detection operation in conjunction with detection of multiuser or interfering signals, e.g. iteration between CDMA or MIMO detector and FEC decoder
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0064—Concatenated codes
    • H04L1/0065—Serial concatenated codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
    • H04L27/186—Phase-modulated carrier systems, i.e. using phase-shift keying in which the information is carried by both the individual signal points and the subset to which the individual signal points belong, e.g. coset coding or related schemes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/20—Servers specifically adapted for the distribution of content, e.g. VOD servers; Operations thereof
    • H04N21/23—Processing of content or additional data; Elementary server operations; Server middleware
    • H04N21/238—Interfacing the downstream path of the transmission network, e.g. adapting the transmission rate of a video stream to network bandwidth; Processing of multiplex streams
    • H04N21/2383—Channel coding or modulation of digital bit-stream, e.g. QPSK modulation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/438—Interfacing the downstream path of the transmission network originating from a server, e.g. retrieving encoded video stream packets from an IP network
    • H04N21/4382—Demodulation or channel decoding, e.g. QPSK demodulation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L2001/0098—Unequal error protection

Definitions

  • Transmission system comprising a transmitter for transmitting digital signals according to a block coded modulation at points of a constellation, said system comprising a receiver provided with a decoder provided with first means for erasing bit sequences and with second means correction of erasures and bit sequence errors.
  • the invention also relates to a receiver and a decoder of digital signals implemented in such a system.
  • Such a system finds its application in the transmission of digital signals by a transmission channel.
  • This may involve transmitting digital television signals, for example high definition by a satellite channel or digital signals by radio-relay systems. It may also involve transmitting sound by mobile radio, or digital data for storage, for example in a compact disc, a digital video recorder. In these cases, it is necessary for the transmission to operate at the source a prior reduction in bit rate by a source encoder and to restore the bit rate on reception by a source decoder. In cases where it is desired to transmit digital data between two digital processing units, for example between two computers, this rate reduction by a source encoder is not necessary.
  • HDTV high definition television
  • HDTV High Definition Television
  • the transmission of HDTV digital signals requires judicious protection.
  • the online error rate must be less than 10 ⁇ 11.
  • the routing of digital HDTV signals via such a channel requires source coding at a high compression rate as well as digital modulation with high spectral efficiency.
  • Source coding techniques for example based on an orthogonal transformation, can reduce the bit rate by a factor greater than 10 while ensuring good quality of restored image. This results in transmitting a bit rate of the order of 60 to 70 Mbits / s.
  • the transmission of such signals over a satellite channel requires digital modulation with spectral efficiency reaching 2.7 bits / s / Hz.
  • channel coding and modulation As an entity and for this to combine channel coding with digital modulation. This increases the efficiency of digital transmission, thus improving performance, without sacrificing spectral efficiency.
  • the redundancy added by the coding is transmitted by the redundancy of the alphabet instead of decreasing the data rate. This technique is based on the principle of maximizing the minimum Euclidean distance between the sequences of transmitted coded points.
  • MCTs of moderate complexity (4 or 8 states) can give a coding gain of 3 to 4 dB.
  • the implementation of a Viterbi decoder necessary to decode these MCTs remains costly with current technology.
  • An attractive coding technique for these applications is that of multilevel coding. The advantage of this technique is that it is suitable for a simple sub-optimal decoding process carried out in stages and presenting a good compromise between performance and implementation complexity.
  • a multi-stage decoder On reception, a multi-stage decoder operates the opposite operation and restores points corresponding to the transmitted points. In a conventional decoder this implements decision operations which estimate points and determine bits for the codes of the points estimated as a function of the phase and the amplitude which are detected on reception for each point received. Depending on the various transmission and reception conditions, some of the estimated bits are incorrect.
  • a first stage of the multistage decoder decides according to the first level of the partition. The result delivered by this first stage is used to validate the start-up of the second stage and so on until the last stage.
  • G.J. POTTIE and D.P. TAYLOR we introduce an additional notion of bit erasure after each stage decoding operating a concatenated decoding. This increases the performance of the decoder but at the cost of increased complexity. Indeed, this requires the addition of a second decoder to correct the errors and complete the erasures of bits.
  • each symbol after the decoding is independent of that who follows him.
  • the symbols after the decoding are interdependent and must be treated accordingly.
  • coding by cascaded codes requires an interleaver for coding and a deinterlacer for decoding between the internal and external coder / decoder. This obviously increases the processing and hardware production of the coding and decoding devices.
  • the coding gain thus obtained is between 0.05 and 0.1 dB which is relatively modest.
  • the object of the invention is also to increase the performance of conventional decoding by processing bit sequences while retaining an equivalent complexity of the hardware means.
  • This improvement in performance must consist, for a given bit error rate, in reducing the signal-to-noise ratio on transmission, which consequently makes it possible to reduce the power of the transmission.
  • a performance gain is obtained, without increasing the hardware complexity of the decoder, in the case of example of a phase shift modulation MDP (PSK in English) or an amplitude modulation of two carriers in quadrature MAQ (QAM in English).
  • PSK phase shift modulation MDP
  • QAM amplitude modulation of two carriers in quadrature MAQ
  • the decoder according to the invention can operate with coded modulations of several types. These can be CDM modulations, MAQ modulations or other modulations. In the case of MDP modulations, the points of the constellation have the same amplitude but differ in their phases.
  • the internal decoding means carry out a maximum likelihood decoding of the internal code words having a fixed number of estimated bits, an information part of the internal code word constituting an external symbol, the erasure of any external symbol being carried out when the determination at least one bit of the internal code word is uncertain.
  • the decoder thus takes advantage of multilevel coding which implements the notion of partition which is adapted to a simple sub-optimal decoding method carried out in stages and having a good compromise between performance and implementation complexity.
  • the erasure procedure is performed on a fixed number of points received, equal to the number of bits of a code word of the internal code, on the symbols of the external code, symbol after symbol. This procedure is performed for each external symbol independently of the other external symbols, which allows greater decision reliability.
  • the internal decoder By using a maximum likelihood decoding, the internal decoder then presents an optimal efficiency.
  • the external decoder can take advantage of the presence of error correlations at the output of the internal decoding.
  • the decoder according to the invention does not require any coding interleaver, so no decoding deinterleaver. This greatly simplifies the material realization.
  • This constellation is partitioned according to several levels of partition. One floor operates for a single level of partition.
  • the detection means determine, for each point received PR, a pair of distances (D1, D2) between said point received PR and two closest points PT1, PT2 forming part of the subset of the partition level of said stage, as well as a series of binary pairs b p 1, b p 2 of the same weight p as the binary assignments of points PT1 and PT2 respectively.
  • binary pairs b p 1, b p 2 of the same weight p form sequences of bits organized in sequence. If the internal code at transmission is of length n, the sequences after decoding constitute internal code words of n bits b p . That is to say n bits of the same weight p as the n points estimated after detection.
  • the constellation of a coded modulation can be partitioned into several levels. Each of the levels is coded and each stage of the decoder then processes only one of said levels. It is also possible that subsequent stages do not implement a sequence erasure procedure, this procedure then being reserved for the first partition levels.
  • the decoder further comprises at least one stage provided with said detection means and first means which carry out an internal decoding by generating estimated code words of an internal code.
  • the last partition level (s) are not coded.
  • the corresponding stage or stages are only provided with said detection means which perform, validated by the stages which precede it / them, a detection of received points PR not coded.
  • Each stage acts in cascade on the stages which follow it. For this, the decoded bits of one stage are used to make the decisions in the next stage.
  • the coding device is connected to a transmission channel 15. It can be radio links, satellite links or cable links.
  • this bit rate is reduced to 70 Mbits / s at the output of the source encoder 11.
  • These samples are encoded by the encoder of channel 12 to make them not vulnerable to imperfections in the channel.
  • the modulator 13 then adapts the digital samples to the transmission channel, for example a satellite channel.
  • the coding device 5, the decoding device 105 and the transmission channel 15 constitute a system for coding / decoding digital signals with coded modulation.
  • the invention relates to channel decoding which is the reverse operation of the channel coding operated on transmission.
  • the channel coding concerned by the invention is a multilevel coding. For the sake of clarity, the principle of multilevel coding is first explained.
  • the M bits e1, e2, ..., e i ..., e M (with e i the bit assigned to the i th level of the partition), select one of the 2 M subsets, and the m - M remaining bits designate a point in the selected subset.
  • Figure 2 shows the partition scheme for an MDP-8 modulation.
  • this constellation point allocation process is to classify the m bits represented by the transmitted point as a function of their vulnerabilities with respect to noise. It is very easy to see that the bit e2 is less vulnerable than the bit e1, since it corresponds to a minimum Euclidean distance d2> d1. According to the partition principle described above, it can be shown that if the bits e k , k ⁇ i - 1, are sufficiently protected so that they are correct, the bit e i , i ⁇ M, is better protected from noise than all the other bits e j , j ⁇ i and that the last (mM) bits are the least vulnerable.
  • the first, from D1 to D M1 are coded by concatenated codes (E i , I i ), E i being a block code and I i being a parity code.
  • the following bit streams, after D M1 and up to D M are coded by a unique binary coding I i (n i , k i , ⁇ i ).
  • External encoders 341, 342, ... 34 M1 carry out the encodings E i .
  • a code symbol E i is represented on q i bits.
  • the parity codes I i (q i + 1 , q i , 2) encode each symbol of q i bits delivered by the external coders, by adding a parity bit to them.
  • Internal encoders 351, 352, ... 35 M1 carry out the codings I i .
  • the coding of each symbol of the external code by an internal parity code constitutes the concatenated coding of the two codes E i and I i .
  • the codes E1, ... E M1 can be Reed-Solomon codes on a Galois body CG (2 q1 ). That is to say that each symbol of the RS code consists of q1 bits.
  • the codes I1, ... I M1 can be binary parity codes (q1 + 1, q1, 2).
  • a code word corresponds to n (q + 1) points of the constellation and can be represented by a binary matrix G with m lines and n (q + 1) columns where the j th column represents the binary assignment of the j th point of the block, and the i th line represents the bits assigned to the i th partition level.
  • mM coded by a unique internal code.
  • Multilevel coding (FIG. 3) is carried out using a series-parallel conversion circuit 30 which transforms the serial flow data D in parallel flow data D1, D2 ... D m .
  • the first M1 binary trains are coded by coders 311, 312 ... 31 M1 which deliver the coded binary data e1, e2 ... e M1 resulting from a coding concatenated by the coders 341 to 34 M1 and 351 to 35 M1 .
  • the bit streams from M2 to M are coded by coders 35 M2 .. 35 M which deliver binary data e M2 ... e M from the unique coding I i .
  • Bit streams D M + 1 ... D m may not be coded.
  • a selection member 32 enables each word (e à, e2 ... e m ) to be assigned the binary assignment of a point of the constellation containing 2 m points which is transmitted by the modulator (connection 33).
  • the third level (3rd floor) is not coded.
  • a point in MDP-8 is represented by a column in this matrix.
  • a block is then formed of 360 consecutive points.
  • the decoding will consist in carrying out the reverse operations of the coding. Detection is carried out with each stage in each of the levels of the partition. A concatenated decoding is carried out in the stages where a concatenated coding has been carried out. After each detection in a subset of the partition, each stage performs two decodings (internal decoding and external decoding).
  • FIG. 4 represents a general diagram of a multi-stage decoder with certain stages operating on concatenated codes.
  • Detectors 401 ... 40 M1 , 40 M2 ... 40 M ... 40 m carry out detections each in a partition level.
  • These deliver internal code words erased or not erased respectively to external decoders 441, 442 ... 44 M1 .
  • Said internal decoders eliminate the redundancy due to the internal coding of each point.
  • the external decoders then give estimates of the bit sequences.
  • a level i we take into account the estimates made in the previous levels. For this, the information estimated by the level i-1 is again coded by coders 461, 462 ... 46 M1 to find the redundancy of the internal code words. This is necessary to have code words of length n (q + 1) bits necessary for the following stages.
  • the output data enters a memory 52.
  • FIGS. 5 and 6 represent a multistage decoding for decoding concatenated codes using an MDP-8 modulation.
  • the first stage decodes an external RS code (40, 34, 7) concatenated with an internal parity code (9, 8, 2).
  • the second stage decodes an internal parity code (20, 19, 2).
  • the received block R contains noise which generates a detection uncertainty.
  • a detailed diagram of the decoder is shown in FIG. 6.
  • the signals received in phase I and in quadrature Q are digitized in analog-digital converters 601, 602 which are respectively followed by memories 611, 612 which store the digitized data in order to allow their processing in blocks.
  • Switches 621, 622 distribute, successively to the three stages, digitized data so that the stages operate one after the other on the same data blocks.
  • the first stage makes a first estimate in the 401 detector. For this, it detects a received point P and locates it in the MDP-8 constellation shown in FIG. 7. A point of an MDP-8 constellation is coded on three bits.
  • the first stage of the detector determines the least significant bit, the second stage determines the intermediate weight bit and the third stage determines the most significant bit. The first stage thus delivers sequences of least significant bits.
  • the detector 401 calculates two distances D1 and D2 relative to the two points of the constellation MDP-8 which are closest to the received point P. Such a detection is carried out for a sequence points received, here 9 points taking into account the external decoder used. The detector 401 thus delivers sequences of 9 pairs of estimated bits as well as the corresponding distances D1 and D2. For each sequence of 9 pairs of bits corresponding to 9 points received, the Viterbi 451 decoder uses this data and determines the certain or ambiguous quality of each internal code word. Viterbi decoding is a maximum likelihood decoding which uses the trellis of the code implemented by the coder.
  • the trellis of the internal code is shown in Figure 8 for a sequence of 9 points received.
  • the black dots in Figure 8 represent the nodes of the trellis.
  • the discontinuous lines correspond to bits 0 and the continuous lines correspond to bits 1.
  • a path leading to a node Ni of the trellis thus represents the state of the decisions made on the i-1 preceding points of the modulation.
  • the maximum likelihood decoding will consist in determining, for example, a node Y, possible paths in the trellis taking into account the previous points already decoded.
  • a node Y (figure 8)
  • the paths WXY or WZ Y One calculates a metric corresponding to the cumulation of the distances D1, D2 determined for each preceding point and one chooses the path having the smallest metric as being the most likely path.
  • the decoder then assigns to the bit of the point received the bit either 0 or 1 corresponding to the selected path. This determination is carried out in the same way at each node of the trellis of a sequence.
  • the Viterbi 451 decoder thus delivers 9-bit sequences, 8 bits of which represent the coded information, and erased sequences.
  • An external code word corresponds to 40 8-bit sequences, ie 320 bits.
  • the external decoder which can be a Reed-Solomon decoder, operates on 8 X 40 bits, ie 320 bits, and provides the bits estimated by the first stage, ie 40 sequences of 8 bits of information.
  • a counter 47 determines the number J of internal code words processed.
  • the second stage needs the bits of the first stage to operate.
  • the parity bits were extracted by the first stage. They must be reintroduced into the 40 sequences before introducing these 40 sequences into the second stage.
  • a parity coding I (9, 8, 2) carried out by the 461 coder makes it possible to do this.
  • the 40 x 9 bit sequences thus reconstructed allow the second detector 402 to determine the partition level B o or B1 to be taken into account for the detection.
  • the Viterbi 452 decoder then performs a 20-bit decoding corresponding to 20 points received according to the example chosen for coding.
  • a counter 49 and a comparator 50 allow, as for the previous stage, either to continue processing by the stage if the number of internal code words is not reached or to put the next stage into operation, in the opposite case .
  • this stage operates only a detection in this third partition level using the detector 403.
  • the output of the decoder 452 enters the detector 403 to allow this detection.
  • a counter 51 is incremented by one each time a stage enters into operation.
  • This counter 51 delivers an R / W signal when all the stages have finished their processing.
  • This signal makes it possible to write the results of each stage in a memory 52 which delivers the decoded data.
  • the R / W signal triggers the writing of new data in the memories 611, 612.
  • FIG. 9 represents the diagram of a 45 bi erasing Viterbi decoder, formed by a Viterbi decoder 79 proper and an erasing estimator 80.
  • the invention can also be implemented in another adaptive mode. This can be combined or not with the previous adaptive mode. This other adaptive mode is shown in FIG. 10.
  • the erasing Viterbi decoder 451 comprises a Viterbi decoder 79 proper and an erasing estimator 80.
  • the external decoder 441 which corrects the erasures. Its correction capacity is limited to a number ⁇ 1 - 1 of erasures. It can for example correct N e (N e ⁇ ⁇ 1 - 1) erasures where ⁇ 1 is the Hamming distance of the external code. If the number Ne of erasures is greater than ( ⁇ 1-1), it then delivers an incorrect result, that is to say that all the erasures are not corrected. According to the invention, it is possible to increase the correction capacity of the external decoder by passing it from ( ⁇ 1-1) to ⁇ 1 erasures.
  • a test (block 47) is carried out at the output of the external decoder 44 qui which determines whether the external decoder 441 is located beyond its correction capacities (N e ⁇ ⁇ 1).
  • N e ⁇ ⁇ 1 We determine when the number of erasures to be corrected is equal to ⁇ 1 (block 85).
  • the external decoding is carried out not by erasing the current internal code word but by using the internal code words C1 or C2 which relate respectively to point D1 or to point D2 detected for the node considered. In this situation, in fact, there is a high probability that the correct internal code word corresponds to that of point D1 or point D2.
  • the external decoder 441 operates first by replacing the erasure with the code word C1. If the result is bad, that is to say if the code word C1 has a greater Hamming distance than the code word C2, then the erasure is replaced by the code word C2.
  • This adaptive mode can deliver improved results for some internal and external concatenated codes.

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  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Probability & Statistics with Applications (AREA)
  • Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Theoretical Computer Science (AREA)
  • Artificial Intelligence (AREA)
  • Computer Security & Cryptography (AREA)
  • Error Detection And Correction (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Television Systems (AREA)
  • Dc Digital Transmission (AREA)
EP92202524A 1991-08-21 1992-08-18 Digitales Nachrichtenübertragungssystem mit verketteten Koden und in diesem System angewandter Empfänger und Dekodierer Expired - Lifetime EP0529718B1 (de)

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FR9110482 1991-08-21
FR9110482 1991-08-21

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EP0529718B1 EP0529718B1 (de) 1997-02-19

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EP (1) EP0529718B1 (de)
JP (1) JP3269858B2 (de)
KR (1) KR100265308B1 (de)
AU (1) AU661699B2 (de)
DE (1) DE69217522T2 (de)
FI (1) FI109161B (de)
TW (1) TW215136B (de)

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KR100710743B1 (ko) * 1998-05-26 2007-04-24 코닌클리케 필립스 일렉트로닉스 엔.브이. 간이 채널 디코더를 구비하는 전송 시스템 및 이 시스템의 운영 방법
KR100714860B1 (ko) * 1998-05-26 2007-05-07 코닌클리케 필립스 일렉트로닉스 엔.브이. 적응 채널 인코더 및 디코더를 구비하는 전송 시스템, 및 이 시스템의 운영 방법

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EP0529718B1 (de) 1997-02-19
US5416804A (en) 1995-05-16
AU2116792A (en) 1993-02-25
KR100265308B1 (ko) 2000-09-15
AU661699B2 (en) 1995-08-03
JP3269858B2 (ja) 2002-04-02
DE69217522D1 (de) 1997-03-27
KR930005401A (ko) 1993-03-23
DE69217522T2 (de) 1997-09-18
FI109161B (fi) 2002-05-31
FI923704A (fi) 1993-02-22
TW215136B (de) 1993-10-21
JPH05260104A (ja) 1993-10-08

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