EP0506170A1 - Structure integrée comprenant un dispositif bipolaire de puissance à haute densité de courant et une diode rapide et son procédé de fabrication - Google Patents

Structure integrée comprenant un dispositif bipolaire de puissance à haute densité de courant et une diode rapide et son procédé de fabrication Download PDF

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Publication number
EP0506170A1
EP0506170A1 EP92200748A EP92200748A EP0506170A1 EP 0506170 A1 EP0506170 A1 EP 0506170A1 EP 92200748 A EP92200748 A EP 92200748A EP 92200748 A EP92200748 A EP 92200748A EP 0506170 A1 EP0506170 A1 EP 0506170A1
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EP
European Patent Office
Prior art keywords
region
lifetime
ions
minority carriers
dopant
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP92200748A
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German (de)
English (en)
Other versions
EP0506170B1 (fr
Inventor
Ferruccio Frisina
Giuseppe Ferla
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
CORIMME Consorzio per Ricerca Sulla Microelettronica nel Mezzogiorno
Original Assignee
CORIMME Consorzio per Ricerca Sulla Microelettronica nel Mezzogiorno
SGS Thomson Microelectronics SRL
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Publication of EP0506170A1 publication Critical patent/EP0506170A1/fr
Application granted granted Critical
Publication of EP0506170B1 publication Critical patent/EP0506170B1/fr
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0744—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common without components of the field effect type
    • H01L27/075—Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. lateral bipolar transistor, and vertical bipolar transistor and resistor
    • H01L27/0755—Vertical bipolar transistor in combination with diodes, or capacitors, or resistors
    • H01L27/0761—Vertical bipolar transistor in combination with diodes only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/221—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities of killers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/904—Charge carrier lifetime control

Definitions

  • the present invention relates to an integrated structure of bipolar power device with high current density and fast diode and related manufacturing process.
  • the large thickness of the collector require the presence of minority carriers with very high lifetimes to prevent the same carriers from recombining along the crossing of the effective base.
  • planar technology used for the manufacture of bipolar power devices allows the integration, without any change of the manufacturing process, of a diode between collector and emitter.
  • Such a diode generally manufactured under the emitter contact area, that is, under the emitter metallization, has a breakdown voltage equal to the power transistor's emitter-collector breakdown voltage and very high inverted recovery times, ranging from 500 to 1000 nsec, due to the high lifetime of the minority carriers. This causes large losses during the transistor's triggering and limits its use to high frequencies (tens or hundreds of KHz).
  • diodes having low inverted recovery times ranging from 100 to 200 nsec
  • fast diodes that can be obtained only with low lifetimes of the minority carriers (ranging from 0.5 to 1 ⁇ sec).
  • the object of the present invention is to allow the manufacture of a single integrated structure comprising a bipolar power device and a fast diode, in which the bipolar device is characterized by a high current density during the conduction step and low switching losses during the triggering step and that can thus be used in particular applications such as motor control.
  • such object is attained with an integrated structure of bipolar power device and fast diode characterized in that it is formed by a single chip of semiconductor material comprising a first area with a high lifetime of the minority carriers, which constitutes a bipolar power device with high current density, and at least one second area with a reduced Lifetime of the minority carriers, which constitutes a fast diode.
  • said integrated structure comprises a substrate of semiconductor material with dopant of the first type, an epitaxial layer superimposed over it, a base region with dopant of the second type obtained inside the epitaxial layer and an emitter region with dopant of the first type obtained inside said base region to constitute said bipolar power device, the entire structure containing impurities suitable for raising the lifetime of the minority carriers, characterized in that inside said base region there is at least one annular region with dopant of the first type suitable for circumscribing inside it an under-region of said base region that is doped with ions suitable for reducing the lifetime of the minority carriers and extends in depth in an underlying under-region of the epitaxial layer and down to the substrate to constitute said fast diode.
  • a process for the manufacture of said structure comprising the growth of an epitaxial layer having a low concentration of dopant on a substrate of semiconductor material with dopant of the first type, the formation of oxide with the subsequent masking and etching for the definition of a base region, the implantation and subsequent diffusion of dopant of the second type in said base region, a further formation of oxide with the subsequent masking and etching for the definition of an emitter region and of at least one annular region suitable for circumscribing inside it an under-region of said base region, the implantation and subsequent diffusion of dopant of the first type in said emitter region and in said at least one annular region, the introduction of impurities into the entire structure to increase the lifetime of the minority carriers, and the implantation inside said under-region of ions suitable for reducing the lifetime of the minority carriers and their subsequent diffusion in depth in an underlying under-region of the epitaxial layer and down to the substrate.
  • an epitaxial layer 2 of the type N- with a low concentration of dopant is necessary for keeping voltage in power devices with a breakdown voltage ranging from 100 to 1000 volts.
  • the resistivity of the epitaxial layer 2 varies from 5 to 100 ohm/cm and the thicknesses from 5 to 100 ⁇ m.
  • a layer of oxide 3 which after appropriate masking is subsequently etched so as to define a window 5 providing access to the epitaxial layer 2.
  • ions of the type p say, boron
  • the base region 6 of a bipolar power transistor of the type NPN whose collector is constituted by the substrate 1.
  • ions of the type N+, say, arsenic there is then accomplished through the implantation of ions of the type N+, say, arsenic, and their subsequent diffusion an emitter region 12 of the bipolar NPH transistor and an annular region 13.
  • the comb-like surface extension of the emitter region 12 allows the optimization of the current distribution.
  • an under-region 20 of the base region 6 having an area ranging from (200x200) ⁇ m2 and (1000x1000) ⁇ m2, suitable for constituting the anode region of a fast PN diode to be integrated in the bipolar power device.
  • the surface of the integrated structure is coated with a layer of oxide 17 which, after appropriate masking, is subsequently etched so as to define a window 19 giving access to the under-region 20.
  • the window 19 has dimensions ranging from (50x50) ⁇ m2 and (300x300) ⁇ m2 and is located in the centre of the diode area surrounded by the annular region 13 (Fig. 5).
  • the implantation of gold or platinum ions in silicon may be accomplished, say, by using the device for the ionization of metals having a high melting point, which may be used on ionic implanters of the type using ion sources of the Freeman type or similar, that is described in the Italian patent application No. 19134 A/90 filed on 23 January 1990 in the name of CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO and through a process such as the one described in the Italian patent application No. 22237 A/90 filed on 29 November 1990 in the name of CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO.
  • the amount and the temperature of implantation of gold in silicon are selected so as to ensure that the gold ions diffuse vertically until they reach the substrate 1, but are wholly contained laterally in the under-regions 20, 21 inside the annular region 13.
  • the amount of implant and the temperature are obtained taking into account the values of some characteristic parameters such as the coefficients of vertical and horizontal diffusion and the coefficient of segregation of gold in silicon.
  • this illustrates the curve of the coefficient of vertical diffusion Dv and of the coefficient of surface diffusion Ds of gold at different temperatures.
  • the quantity of gold or platinum introduced into the silicon is distributed in relation to the concentration of dopant in the silicon.
  • the curve of the coefficient of segregation K of gold in silicon defined as the ratio between the concentration of gold in the more highly-doped silicon and the concentration of gold in the less highly ⁇ doped silicon is strongly influenced by the temperature of diffusion and the concentration of silicon.
  • connection between the depth of diffusion represented by the thickness of the epitaxial layer 2 (ranging from 20 to 100 ⁇ m) and the horizontal distance of diffusion constituted by the larger side of the under-region 20 defined inside the annular region 13 (ranging from 200 to 1000 ⁇ m) depends on the dimension of the window 19 and on the ratio between the vertical and horizontal coefficients of diffusion.
  • the oxide 17 is partially removed, which remains positioned on the surface of the integrated structure at the annular region 13 and on the sides of areas in which the contacts of base 22 and of emitter 23 are fabricated. There are then deposited the corresponding metallizations of base 24 and of emitter 25. The recoating of the annular region 13 causes the latter to be no longer contacted by the metallization 25.
  • the metallization 25, contacts the base under-region 20 forming a fast integrated diode between the emitter 12 and the collector 1.
  • two distinct areas have been manufactured inside the same device 26: one area reserved for the fast diode, constituted by the under-regions 20, 21, circumscribed by the dotted lines, wherein gold or platinum have been diffused and which is characterized by a short lifetime of the minority carriers (say, 1 ⁇ sec or less); the rest of the semiconductor chip, indicated generacally with 32, where there has been manufactured an NPN bipolar power transistor with high lifetimes (say, some 10 ⁇ sec or more) of the minority carriers determined by the gettering process.
  • the process described above for the manufacture of the structure of Fig. 4 can also be used for the manufacture of a structure wherein a transistor is necessary that has a high lifetime of the minority carriers (equal to some 10 ⁇ sec or more) and a diode with several areas having a low lifetime of the minority carriers (equal to some 1 ⁇ sec or less).
  • each window 19, 19' is then manufactured, each located between a corresponding annular region 13, 13'.
  • the dimensions of the windows 19, 19' are calculated as above in relation to the larger dimension of each annular region 13, 13' to the thickness of the epitaxial layer 2 and to the implantation dose and diffusion temperature of gold or platinum.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Bipolar Transistors (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Thyristors (AREA)
EP92200748A 1991-03-28 1992-03-17 Structure integrée comprenant un dispositif bipolaire de puissance à haute densité de courant et une diode rapide et son procédé de fabrication Expired - Lifetime EP0506170B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
ITMI910836 1991-03-28
ITMI910836A IT1245365B (it) 1991-03-28 1991-03-28 Struttura integrata di dispositivo bipolare di potenza ad elevata densita' di corrente e diodo veloce e relativo processo di fabbricazione

Publications (2)

Publication Number Publication Date
EP0506170A1 true EP0506170A1 (fr) 1992-09-30
EP0506170B1 EP0506170B1 (fr) 1999-09-08

Family

ID=11359289

Family Applications (1)

Application Number Title Priority Date Filing Date
EP92200748A Expired - Lifetime EP0506170B1 (fr) 1991-03-28 1992-03-17 Structure integrée comprenant un dispositif bipolaire de puissance à haute densité de courant et une diode rapide et son procédé de fabrication

Country Status (5)

Country Link
US (2) US5343068A (fr)
EP (1) EP0506170B1 (fr)
JP (1) JP3125112B2 (fr)
DE (1) DE69229927T2 (fr)
IT (1) IT1245365B (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996035229A1 (fr) * 1995-05-06 1996-11-07 Aea Technology Plc Procede de reduction localisee de la duree de vie
GB2325343A (en) * 1997-05-14 1998-11-18 Mitel Semiconductor Ltd Semiconductor devices with p-n junctions
EP0878849A2 (fr) * 1997-05-14 1998-11-18 Mitel Semiconductor Limited Diode de puissance

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0642085A (ja) * 1992-07-21 1994-02-15 Daiwa House Ind Co Ltd 外壁の開口フレーム固定構造
EP0675527B1 (fr) * 1994-03-30 1999-11-10 Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno Procédé de fabrication pour obtenir des transistors bipolaires ayant un temps d'emmagasinage contrÔlé
US5838057A (en) * 1994-08-03 1998-11-17 Texas Instruments Incorporated Transistor switches
GB2292252A (en) * 1994-08-05 1996-02-14 Texas Instruments Ltd Rapid turn off semiconductor devices
US6358825B1 (en) * 2000-11-21 2002-03-19 Fairchild Semiconductor Corporation Process for controlling lifetime in a P-I-N diode and for forming diode with improved lifetime control
DE102007020039B4 (de) * 2007-04-27 2011-07-14 Infineon Technologies Austria Ag Verfahren zur Herstellung einer vertikal inhomogenen Platin- oder Goldverteilung in einem Halbleitersubstrat und in einem Halbleiterbauelement, derart hergestelltes Halbleitersubstrat und Halbleiterbauelement
CN115274436B (zh) * 2022-09-28 2023-01-10 瑞森半导体科技(湖南)有限公司 一种快恢复二极管及其制备方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1619972A1 (de) * 1967-05-02 1971-03-18 Licentia Gmbh Verfahren zum Gettern von metallischen Verunreinigungen aus Siliziumkristallen
US3645808A (en) * 1967-07-31 1972-02-29 Hitachi Ltd Method for fabricating a semiconductor-integrated circuit
DE3331631A1 (de) * 1982-09-01 1984-03-01 Mitsubishi Denki K.K., Tokyo Halbleiter-bauelement

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3486950A (en) * 1967-04-26 1969-12-30 Motorola Inc Localized control of carrier lifetimes in p-n junction devices and integrated circuits
DE1942838A1 (de) * 1968-08-24 1970-02-26 Sony Corp Verfahren zur Herstellung integrierter Schaltungen
US3625781A (en) * 1969-05-09 1971-12-07 Ibm Method of reducing carrier lifetime in semiconductor structures
US3640783A (en) * 1969-08-11 1972-02-08 Trw Semiconductors Inc Semiconductor devices with diffused platinum
JPS52149666U (fr) * 1976-05-11 1977-11-12
JPS56114367A (en) * 1980-02-14 1981-09-08 Toshiba Corp Semiconductor device
US5128742A (en) * 1988-04-14 1992-07-07 Powerex, Inc. Variable gain switch
FR2638892B1 (fr) * 1988-11-09 1992-12-24 Sgs Thomson Microelectronics Procede de modulation de la quantite d'or diffusee dans un substrat de silicium et diode rapide obtenue par ce procede

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1619972A1 (de) * 1967-05-02 1971-03-18 Licentia Gmbh Verfahren zum Gettern von metallischen Verunreinigungen aus Siliziumkristallen
US3645808A (en) * 1967-07-31 1972-02-29 Hitachi Ltd Method for fabricating a semiconductor-integrated circuit
DE3331631A1 (de) * 1982-09-01 1984-03-01 Mitsubishi Denki K.K., Tokyo Halbleiter-bauelement

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 5, no. 192 (E-85)8 December 1981 & JP-A-56 114 367 ( TOSHIBA K.K. ) 8 September 1981 *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996035229A1 (fr) * 1995-05-06 1996-11-07 Aea Technology Plc Procede de reduction localisee de la duree de vie
GB2325343A (en) * 1997-05-14 1998-11-18 Mitel Semiconductor Ltd Semiconductor devices with p-n junctions
EP0878849A2 (fr) * 1997-05-14 1998-11-18 Mitel Semiconductor Limited Diode de puissance
EP0878849A3 (fr) * 1997-05-14 1999-10-20 Mitel Semiconductor Limited Diode de puissance

Also Published As

Publication number Publication date
ITMI910836A1 (it) 1992-09-28
DE69229927T2 (de) 2000-01-20
IT1245365B (it) 1994-09-20
EP0506170B1 (fr) 1999-09-08
DE69229927D1 (de) 1999-10-14
ITMI910836A0 (it) 1991-03-28
JP3125112B2 (ja) 2001-01-15
US5343068A (en) 1994-08-30
JPH0822995A (ja) 1996-01-23
US5468660A (en) 1995-11-21

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