EP0483537A2 - Current source circuit - Google Patents

Abstract

A current with a high negative temperature coefficient can be taken from a current source circuit with a resistor linked in a loop from two current mirror circuits via a current source transistor. Furthermore, such a current source circuit manufactured in CMOS technology has a high current requirement. According to the invention, these disadvantages can be reduced by replacing the resistor with a switched capacitance. <IMAGE>

Description

The invention relates to a current source circuit with a first, second, third and fourth field effect transistor according to the preamble of claim 1.

Such a current source circuit is known from the journal "IEEE Journal of Solid States Circuits", June 1977, pages 224 to 231, in particular FIG. 8 on page 228. This circuit is shown in FIG. 1, according to which the field effect transistors T1 to T4 together with the resistor R1 form a reference current source. Here, the two n-channel transistors T1 and T2 represent a first current mirror. The two p-channel transistors T3 and T4 additionally form a second current mirror.

wobei W/L [.] die Kanalbreiten/Kanallängen-Verhältnisse der Transistoren T1 bzw. T2 angeben. Aus gleichen Transistorgrößen für T1 und T2 ergeben sich auch gleiche Ströme i2 und i1.The following applies to the first current mirror "T1, T2":

where W / L [.] indicate the channel width / channel length ratios of the transistors T1 and T2. From the same transistor sizes the same currents i2 and i1 also result for T1 and T2.

wobei K die Bolzmannkonstante, T die absolute Temperatur und q die Elektronenladung angibt. Mit einem Widerstand von R1 = MΩ und einem W/L-Verhältnis der beiden Transistoren T4 und T3 von 8 ergibt sich dabei bei Raumtemperatur von 300 K für i1 ein Strom von 5,4·10⁻⁸ A.For the current i1 in connection with the second current mirror "T3, T4" there is a value according to the following formula:

where K is the Bolzmann constant, T is the absolute temperature and q is the electron charge. With a resistance of R1 = MΩ and a W / L ratio of the two transistors T4 and T3 of 8, a current of 5.4 · 10⁻⁸ A results at room temperature of 300 K for i1.

The above equation (2) applies as long as the two transistors T3 and T4 are in the area of weak inversion. From this equation it can also be seen that the current i1 at room temperature has a positive temperature coefficient of approx. +3000 ppm / K, provided the resistance R1 is assumed to be constant and independent of the temperature. A p-well resistor with a positive temperature response is usually used for the resistor R1. This typically results in a negative temperature coefficient for the current i1 in the range from approximately -5000 to -15000 ppm / K.

According to FIG. 1, a current i3 is taken from the reference current source via an n-channel field effect transistor T5. which, depending on the selected size ratio of the first current mirror (W / L [T5] / W / L [T1]), is a fraction or a multiple of the current i1, the current i3 naturally having the same temperature dependency as the current i1.

As shown above, the current i1 for the specified circuit dimensioning is 54 nA; However, since the currents i2 and i1 are of the same size, this reference current source according to FIG. 1 itself already consumes a current of approx. However, this current draw is too large for many applications.

One way to reduce the current consumption of this known reference current source is to reduce the W / L ratio of the two transistors T4 and T3. This reduces the voltage drop across the resistor R1 and thus, for a given resistor R1, the current consumption of the circuit. However, this possibility has narrow limits, since with a very low W / L ratio of the transistors T4 and T3 there are very large percentages of the voltage drop across this resistor R1 and thus also for the current i1.

Another possibility is to increase the resistance value from R1 to, for example, 10 MΩ, as a result of which the current consumption of the reference current source drops to approximately 10 nA, which can thus also be tolerated in the case of "low power" circuits.

However, since this resistor R1 is usually - as already explained above - formed by a p-well resistor and its sheet resistance is technology-related only approx. 2 kΩ /, a disproportionately large chip area (approx. 1 mm²) was required for such a resistor, which is of course also undesirable.

Finally, there is also the possibility of reducing the current consumption by using a likewise high-resistance resistor R1, this resistor being realized by a specially produced layer, for example implanted polysilicon with a high sheet resistance and thus a small space requirement. However, the provision of such a high-ohmic poly resistor requires a special mask and additional process steps and thus causes increased costs. Such a resistor can also only be produced with relatively large tolerances. The current i3 that can be tapped via the transistor T5 is therefore also subject to large variations and the circuit is therefore not suitable for applications in which the current i3 is to have a largely constant value.

The invention is therefore based on the object of providing a current source circuit of the type mentioned at the outset which allows current to be drawn, the current of which is largely constant with little overall power consumption by the current source circuit.

This object is achieved by the characterizing features of patent claim 1.

Accordingly, the essence of the invention consists in simulating the resistor R1 according to FIG. 1 by a switched capacitance. As with many integrated circuits a stable quartz frequency of, for example, 32.768 kHz is available, a resistance of approx. 10 MΩ can easily be realized here with a small capacitance of a few pF. For example, with a frequency f of 32.768 kHz and a capacitance value of 3 pF, a capacitive resistance of 10.1 MΩ results.

Of particular note here is the small chip area requirement of such a capacitor of 3 pF, which therefore only requires a fraction (less than 1%) of the area of an ohmic (p-well) resistor with the same resistance value.

Furthermore, a thin silicon dioxide layer (gate oxide), which is generated in any case during the production of an integrated CMOS circuit, is usually used as the dielectric for such a capacitance. The layer thickness of this oxide is typically a few 100 Å and is manufactured within narrow tolerance limits of less than +/- 5%. Capacities with very small variations in the absolute value can thus be produced without additional process steps, so that under the stipulation of a constant clock frequency, a reference current source with small variations in the current i3 drawn by the transistor T5 with a low current consumption of the circuit itself, e.g. B. less than 10 nA and small chip area requirements.

In an advantageous development of the invention, a current source circuit is specified by the characterizing features of claim 2, which current output circuit with a preset temperature coefficient delivers. The temperature coefficient of this output current is determined by the capacitors provided in the circuit arrangement controlled by the second current mirror, the sign of which is predetermined by the phase position of the clock signals supplied to this circuit arrangement.

By arranging further such circuit arrangements controlled by the second current mirror, in another advantageous development of the invention, several output currents with a selectable temperature coefficient and sign can be obtained. Current sources with different temperature characteristics can thus be made available on an integrated circuit.

Furthermore, according to the characterizing features of claims 4 and 5, a further simple possibility for generating output currents with different negative temperature coefficients is given, the values of which are predetermined by the dimensioning of the transistors of the current mirrors involved.

Finally, further advantageous embodiments of the invention are given by the characterizing features of claims 6 and 7.

Figur 2

ein Ausführungsbeispiel der erfindungsgemäßen Stromquellenschaltung,

Figur 3

ein Schaltbild eines weiteren Ausführungsbeispieles der Erfindung zur Erzeugung von Ausgangsströmen mit vorbestimmten Temperaturkoeffizienten,

Figur 4

Spannungs-Zeit-Diagramme zur Erläuterung der Funktionsweise der Schaltung nach Figur 3,

Figur 5

ein weiteres Ausführungsbeispiel der Erfindung zur Erzeugung von Ausgangsströmen mit negativem Temperaturkoeffizienten.

Figur 6

ein Schaltbild eines weiteren Ausführungsbeispieles der Erfindung zur Erzeugung eines Stromes mit negativem Temperaturkoeffizienten, und

Figur 7

ein Schaltbild zur Erzeugung von mehreren Strömen mit unterschiedlichen negativen Temperaturkoeffizienten.

In the following, the current source circuit according to the invention with its advantages will be explained and illustrated using exemplary embodiments in connection with the figures. Show it:

Figure 2

an embodiment of the current source circuit according to the invention,

Figure 3

2 shows a circuit diagram of a further exemplary embodiment of the invention for generating output currents with predetermined temperature coefficients,

Figure 4

Voltage-time diagrams to explain the mode of operation of the circuit according to FIG. 3,

Figure 5

a further embodiment of the invention for generating output currents with a negative temperature coefficient.

Figure 6

a circuit diagram of another embodiment of the invention for generating a current with a negative temperature coefficient, and

Figure 7

a circuit diagram for generating multiple currents with different negative temperature coefficients.

In the figures, components with corresponding functions are provided with the same reference symbols.

The basic structure of the current source circuit according to FIG. 2 corresponds to that according to FIG. 1 with 5 field effect transistors T1 to T5. The two n-channel transistors T1 and T2 and the two p-channel transistors T3 and T4 form a first and a second current mirror, for which purpose the control electrode of the transistor T1 with its drain electrode and the control electrode of the transistor T3 also with it Drain electrode are connected. Furthermore, the control electrodes of the transistors T1 and T2 or T3 and T4 forming a current mirror are connected to one another. The two transistors T2 and T3 are connected in series via their channel paths and connect the reference potential of the circuit to an operating voltage source V _DD , in that the transistor T2 has its source electrode at the reference potential and the source electrode of the transistor T3 is at the operating potential. As a result, these two transistors T2 and T3 form a main current branch 2 which connects the reference potential to the operating voltage potential V _DD . A further main current branch 1, which is parallel to this, is connected by a series connection of transistor T1, transistor T4, a resistor R2 and two p Channel transistors T6 and T7, starting from the reference potential of the circuit and connected to one another in the order listed, the source electrode of transistor T6 being at the operating potential of the operating voltage source V _DD . Finally, an n-channel transistor T5 is provided, the gate electrode of which is connected to the first current mirror via the gate electrode of the transistor T1 and the source electrode of which is also at the reference potential of the circuit. A current i3 can be taken from the drain electrode of this transistor T5, the magnitude of which corresponds to the current i1 flowing in the main circuit 1 with the same dimensions of the transistors T1 and T5. In the equilibrium state of the circuit, the current i1 corresponds to the current i2 flowing in the main circuit 2.

Furthermore, according to Figure 2, a first and second capacitor C1 and C2 are provided, the first capacitor C1 being arranged parallel to the channel path of the transistor T6 and the second capacitor C2 having its first connection at the reference potential of the circuit and with its second connection to the Control electrode of the first and second transistor T1 and T2 is connected.

The two control electrodes of the transistors T6 and T7 are supplied with clock signals Cl1 and Cl2 which are in phase opposition to one another, that is to say if the gate electrode of the transistor T7 receives a low signal (L level), and is simultaneously present on the gate electrode of the other transistor T6 High signal (H level) on.

The mode of operation of the circuit arrangement according to FIG. 2 will now be explained below:
The capacitor C1 is discharged by the transistor T6 at the L level during the clock phase, since the transistor T6 is turned on and at the same time the transistor T7 is in the blocked state. In the subsequent clock phase, the control electrode of transistor T6 is at an H level and at the same time the gate electrode of transistor T7 is at an L level, as a result of which capacitor C1 now charges up to a voltage value V _C , which is determined by the size relationships of the Transistors T1 to T4 results.

In this circuit, the resistor R2 in the main current branch 1 only has the function of a current limitation and is intended to prevent the transistors from changing from H to L level when the clock signal Cl1 changes on the edge T1 to T4 briefly an excessive current flow occurs. The value of this resistor R2 is not critical and can therefore z. B. be formed by an appropriately dimensioned p-channel transistor T7 itself, which has the desired resistance value in the conductive state. Since in this circuit the current i1 is not constant over time in comparison to that according to FIG. 1, but pulsates in rhythm with the applied clock frequency, but the current i3 taken via T5 should normally not have any temporal fluctuations, the capacitor C2 already mentioned is of the common type Gate connection of the transistors T1, T2 and T5 connected as smoothing capacitance to the reference potential, the value of which is also on the order of a few pF.

With the circuit according to the invention shown in FIG. 2, an output current i3 can thus be generated with minimal space requirement and low power consumption, which has only small manufacturing-related tolerances and whose absolute value is almost exclusively dependent on the selected transistor dimensions of the transistors T1 to T5, the capacitance value of the capacitor C1 and the Frequency of the applied clock signal Cl1 and Cl2 depends. However, the achievable temperature coefficient of the output current i3 is fixed and is approximately +3000 ppm / K, since the capacitor C1 itself has only a very low temperature coefficient.

The exemplary embodiment according to FIG. 3 contains, with the switching elements T1 to T7, C1 and C2 and R2, a circuit part which corresponds to the circuit arrangement according to FIG. 2. Therefore, this circuit part in following are no longer explained. In addition, this circuit arrangement contains a current source transistor T8 which is controlled by the first current mirror T1 and T2 and is designed as an n-channel field effect transistor. This transistor T8, which has its source electrode at the reference potential of the circuit, supplies an emitter current i4 for an npn bipolar transistor Q1, which serves as a reference _voltage source Q _ref . For this purpose, its base electrode and its collector electrode are at the potential of the operating voltage source V _DD , in order to thereby generate the base-emitter voltage V _{BE of} the transistor Q1 at the circuit node K1 which is required as a temperature-dependent reference voltage. A series circuit comprising two field effect transistors T9 and T10 connects this circuit node K1 to the operating voltage source V _DD , the transistor T9 connected to this potential being of the p-channel type and the transistor T10 connected to the circuit node K1 being the n-channel type. The connection point of the two channel sections of these transistors T9 and T10 leads to a connection K3 of a circuit arrangement 3. The two control electrodes of these two transistors T9 and T10 are connected to one another and are driven by a clock signal Cl1. As a result, depending on the state of this clock signal Cl1, the connection K3 is switched either to the reference voltage V _BE (Cl1 = H level) or to the operating voltage source V _DD (Cl1 = L level).

A current i5 can be taken from the circuit arrangement 3 and, as will be shown further below, a certain temperature coefficient can be impressed on it. For this purpose, this circuit arrangement 3 contains one of the second current mirror T3 and T4 controlled current source transistor T13 of the p-channel type, whose drain electrode supplies said output current i5 and whose source electrode is connected to the operating voltage source V _DD via a series circuit comprising two p-channel effect transistors. The control electrode of the transistor T11 is supplied with the clock signal Cl1 and the control electrode of the transistor T12 with the clock signal Cl2, which is in phase opposition to the clock signal Cl1, or vice versa, the clock signal Cl2 and the transistor T12 with the clock signal Cl1. The clock signal lines are connected to the connections K5 and K6 of the circuit arrangement 3. The output current i5 is withdrawn at a connection K7.

A first capacitor C4 of this circuit arrangement 3 corresponds to the capacitor C1 parallel to the channel section of the transistor T11, while a second capacitor C3 connects the connection point K4 of the two channel sections of the transistors T11 and T12 to the node K3.

The mode of operation of the circuit arrangement according to FIG. 3 is as follows:
The field effect transistors T11, T12 and T13 and the capacitors C3 and C4, in cooperation with the circuit according to FIG. 2 described above, deliver an output current i5, the temperature profile of which is essentially determined by the dimensioning of the capacitors C3 and C4 and by the reference voltage V _BE and their temperature dependence is.

The base-emitter voltage V _{BE of} the vertical npn transistor Q1 manufactured in integrated CMOS technology is subject to only slight fluctuations in the given manufacturing process with the parameter scatter to be expected over several manufacturing lots. The absolute value and temperature profile of this voltage are also only influenced by the current density, that is to say by the ratio of the emitter area of the transistor Q1 to the emitter current i4. Since the current i4, the size of which corresponds to the size of the current i1 with the same dimensioning of the transistors T1 and T8, is, however, only subject to slight production variations, the absolute value and temperature dependence of the reference voltage V _{BE of} the reference _voltage source Q _{ref can} be determined very precisely in the given circuit dimensioning.

If the capacitor C3 of the circuit arrangement 3 is initially disregarded, it is found that the arrangement of the switching elements T11, T12, T13 and C4 corresponds exactly to the circuit arrangement of the switching elements T4, T6, T7 and C1, that is, with the same dimensioning of the Capacitor C4 of transistors T11 to T13, like capacitor C1 and transistors T4, T6 and T7, the output current i5 and its temperature profile will correspond to the current i1.

Diagrams a, b according to FIG. 4 show the level curve of the clock signals Cl1 and Cl2, which are in phase opposition to one another. The voltage diagram c shows the voltage curve V _{C4 of} the capacitor C4. At time t 1, this capacitor C4 - C3 would not be present - charged by a voltage amount -V _C4 to a final voltage -V _end at time t₂.

Der Spannungsverlauf an diesem Kondensator C4 ist mit dem Spannungsdiagramm d nach Figur 4 dargestellt. Hieraus ist ersichtlich, daß die weitere Spannungsänderung -V_C4 bis zum Endwert -V_end aufgrund der Anfangsspannung - V_C4 kleiner als im Spannungsdiagramm c ohne die Kompensation durch den Kondensator C3 ist. Daraus ergibt sich zunächst, daß der entnehmbare Strom i5 kleiner ist als der Strom i1.If the capacitor C3 is now taken into consideration, the following occurs under the assumption that the transistors T9, T10 and T11 are driven with the clock signal Cl1 according to FIG. 4a and T12 with the inverted clock signal Cl2 according to FIG. 4b:
While the clock signal is Cl1 to L level, the capacitor C4 is discharged via the transistor T11 to the operating potential V _DD and at the same time the node K3 is also held via the transistor T9 to the operating potential V _DD, that is, the capacitor C3 is also discharged . When the edge of the clock signal Cl1 changes from L to H level, the circuit node K3 is switched to the reference voltage V _BE and thus the capacitor C4 is suddenly charged to a differential voltage - V _C4 via the coupling capacitance C3, the following value for this differential voltage - V _C4 results in:

The voltage curve across this capacitor C4 is shown with the voltage diagram d according to FIG. It can be seen from this that the further voltage change -V _C4 to the final value -V _end is smaller due to the initial voltage - V _C4 than in the voltage diagram c without the compensation by the capacitor C3. This initially shows that the current i5 that can be drawn is smaller than the current i1.

Since the differential voltage - V _C4 - as can be seen from equation (3) - is a fraction of the reference voltage V _BE corresponds, this differential voltage - V _C4 also follows the temperature profile of this reference voltage V _BE , that is, with increasing temperature, the differential voltage - V _C4 also becomes smaller. However, this increases the charging voltage -V _C4 , that is, the charge of the capacitor C4 from the initial value - V _C4 to the final value -V _end takes place over a larger voltage range and thus the current i5 that can be drawn also increases. A positive temperature coefficient thus results for the output current i5, the value of which, with the known temperature profile of the reference voltage V _{BE, being determined} only by the ratio of the capacitance values of the capacitors C3 and C4.

If, on the other hand, the clock signals at terminals K5 and K6 are interchanged in the circuit according to FIG. 3, that is to say that transistor T11 receives clock signal Cl2 and transistor T12 receives clock signal Cl1, a negative temperature coefficient for output current i5 is thereby achieved. The corresponding voltage curve across the capacitor C4 is shown in the diagram e in FIG.

When the clock signal Cl1 switches to H level at the time t 1, the terminal K3 is connected to the reference voltage V _BE via the transistor T10 which is turned on, while at the same time the capacitor C4 is discharged via the transistor T11 to the operating potential V _DD , since the clock signal Cl2 switches to L level, that is, the capacitor C3 is simultaneously charged to the reference voltage V _BE .

Now transistor T11 is blocked when the clock signal Cl2 changes from L to H level. At the same time, however, the clock signal Cl1 changes from H to L level, as a result of which the circuit node K3 is switched to the operating voltage potential V _DD via the transistor T9. Thus, at this point in time the two capacitors C3 and C4 are connected in parallel and since the capacitor C3 was previously charged to the reference voltage V _BE , the parallel connection of the two capacitors C3 and _{C4 is} reloaded to the voltage difference + V _C4 . The charging of this capacitor C4 up to the final voltage value -V _end thus takes place over a wider voltage range -V _C4 than in the circuit without temperature compensation according to FIG. 4c, and the output current i5 which can be drawn is therefore initially greater. At higher temperature, however, the reference voltage V _BE becomes smaller and thus the initial charging voltage + V _C4 is also reduced, i.e. the charge on the capacitor C4 from the initial voltage value + V _C4 to the final voltage value -V _end takes place over a smaller voltage range and with increasing temperature this means that the current i5 that can be drawn also becomes smaller with increasing temperature, that is to say that i5 has a negative temperature coefficient.

If parallel to the terminals K2, K3, K5 and K6 of the circuit arrangement 3 according to FIG. 3, further such circuit arrangements 3₁, 3₂, 3₃, ... are connected in parallel, output currents i5, i5₁, i5₂, i5₃,. .. are generated with different temperature behavior. Such a current source circuit is shown in FIG. 5, the reference _voltage source Q _ref and the switching elements T1 to T7, C1 and C2 are not shown. Each of these circuit arrangements 3₁, 3₂, 3₃, ... correspond to their structure of the circuit arrangement 3 according to Figure 3. They thus contain transistors T11₁, T12₁, T13₁, T11₂, T12₂, T13₂, ... and capacitors C3₁, C4₁, C3₂, C4₂ , .... At the terminals K7₁, K7₂, K7₃, ... a current i5₁, i5₂, i5₃, ... can be removed.

FIG. 6 now shows a circuit with which the current source circuit according to FIG. 3 can be supplemented to generate an output current with negative temperature coefficients. It is assumed here that the circuit according to FIG. 3 supplies an output current i5 with a positive temperature coefficient. Instead of the current source circuit according to FIG. 3, FIG. 6 shows only the circuit branches supplying the output current i3 and the output current i5. The output current i3 represents the input current for a current mirror made up of two p-channel field effect transistors, while the output current i5 is fed as an input current into a further current mirror made up of two n-channel field effect transistors T14 and T15. The first current mirror T16, T17 is connected to the operating voltage source V _DD and supplies an output current i6 via the transistor T17. In contrast, the second current mirror T14, T15 is connected to the reference potential of the circuit and supplies an output current i7 via the transistor T15. These two output currents i6 and i7 are summed to an output current i8 at a circuit node K8.

Since the output current i3 and thus also the output current i6 has a very low positive temperature coefficient, whereas the output current i5 can have a very large positive temperature coefficient depending on the dimensioning of the capacitors C3 and C4, the total output current i8 which can be seen in the circuit according to FIG Difference of the current i6 and the current i7, have a negative temperature coefficient, the value of this temperature coefficient is only specified by the dimensioning of the transistors T15 and T17.

For example, it is possible to dimension these transistors T15 and T17 so that the current i7 becomes greater than the current i6 at a certain temperature. If no current is drawn from the circuit node K8 in this case, that is to say this circuit node K8 is not loaded by, for example, a connected current mirror, the voltage potential at this circuit node K8 is below a limit temperature predetermined by the dimensioning at the voltage potential of the operating voltage source V _DD and changes when it is exceeded this limit temperature to the reference potential of the circuit. In this way, a temperature sensor can be produced with this circuit using simple means.

FIG. 7 shows a circuit expanded according to FIG. 6, in which further transistors T15₁, T15₂, T15₃, ... and T17₁, T17₂, T17₃, ... are provided as current source transistors controlled by the current mirrors. The paired current source transistors T15₁, T17₁ and T15₂, T17₂ and T15₃, T17₃ each deliver an output current i7₁, i6₁ and i7₂, i6₂ and i7₃, i6₃, which are each added up in a circuit node K8₁, K8₂ and K8₃ to produce an output current i8₁, i8₂ and i8₃, these output currents i8₁, i8₂ and i8₃ having different negative temperature coefficients, whereby the values of these temperature coefficients only depend on the dimensioning of the transistors T15₁ to T15₃ and T17₁ to T17₃ is specified.

The circuits described above, which are built in integrated CMOS technology, can, contrary to the conditions shown, also be operated with a different polarity of the operating voltage source V _DD by swapping the p- and n-channel transistors and changing the reference point of the reference voltage V _BE , the capacitors C1 and C4 from + V _DD to -V _DD .

Claims (7)

Current source circuit with a first, second, third and fourth field effect transistor (T1, T2, T3, T4), the first and second field effect transistor (T1, T2) of a first channel type and the third and fourth field effect transistor (T3, T4) of a second Are channel type and the series-connected channel sections of the first and fourth or the second and third field effect transistors (T1, T4; T2, T3) form a first and a second main current branch (1, 2) and wherein to form a first and a second current mirror the control electrode of the first or third field effect transistor (T1, T3) is connected to the first main current branch (1) and the control electrode of the second field effect transistor (T2) or to the second main current branch (2) and the control electrode of the fourth field effect transistor (T4) and for taking a first current source current (i3), a fifth field effect transistor (T5) is controlled by the first current mirror (T1, T2), characterized in that a A first pair of field effect transistors (T6, T7) is provided, these field effect transistors (T6, T7) being connected in series in the first main circuit (1) between the fourth field effect transistor (T4) of the second current mirror (T3, T4) and an operating voltage source (V _DD ) are connected such that a first capacitor (C1) is connected in parallel to the channel path of that field effect transistor (T6) of the first field effect transistor pair (T6, T7) which is connected to the operating voltage source (V _DD ), that a second Capacitor (C2) connects the connected control electrodes of the first and second field effect transistors (T1, T2) to the reference potential of the circuit and that the control electrodes of the field effect transistors (T6, T7) of the first pair of field effect transistors are supplied with counter-phase clock signals (Cl1, Cl2). Current source circuit according to Claim 2, characterized in that a reference voltage source (Q _ref ) and a second pair of field effect transistors (T9, T10) are provided, these two field effect transistors being of the opposite channel type and the series circuit of these two field effect transistors being connected to the reference _voltage source (Q _ref ) and a common clock signal (Cl1) is fed to the connected control electrodes of these two field effect transistors (T9, T10) and that a circuit arrangement (3) is provided with the following features: a) for taking a second current source current (i5), this circuit arrangement (3) comprises a current source transistor (T13) controlled by the second current mirror (T3, T4) and a third pair of field effect transistors (T11, T12), the series connection of these two field effect transistors (T11, T12) connects the current source transistor (T13) to the operating voltage source (V _DD ), b) Furthermore, a first and second capacitor (C3, C4) is provided, the one connection of the two capacitors (C3, C4) to the connection point (K4) of the two field effect transistors of the third field effect transistor pair (T11, T12) and the another connection of the first or second capacitor (C3, C4) is connected to the connection point of the two field effect transistors of the second pair of field effect transistors (T9, T10) or is at the potential of the operating voltage source (V _DD ), c) the control of the third pair of field effect transistors (T11, T12) is carried out by controlling the control electrodes with clock signals in phase opposition (Cl1, Cl2). Current source circuit according to claim 2, characterized in that for the removal of further current source currents (i5₁, i5₂, ...) further circuit arrangements (3₁, 3₂, ...) each with a current source transistor (T13₁, T13₂, ...) a third pair of field effect transistors ( T11₁, T12₁; T11₂, T12₂; ...) and a first and second capacitor (C3₁, C4₁; C3₂, C4₂; ...) with the features a, b, c are provided. Current source circuit according to Claim 2, characterized in that a third current mirror (T16, T17) is provided, to which the first current source current (i3) is supplied as the input current, that a fourth current mirror (T14, T15) is provided, the second current source current being the input current (i5) fed is and that for taking a third current source current (i8) the output currents of the two current mirrors are led to a common node K8. Current source circuit according to claim 4, characterized in that the third current mirror (T16, T17) a first group of current source transistors (T17₁, T17₂, ...) and the fourth current mirror (T14, T15) a second group of current source transistors (T15₁, T15₂, ...) control and that for the removal of further third current source currents (i8₁, i8₂, ...) the output currents of the current source transistors combined in pairs from the first and second group are each routed to a common node (K8₁, K8₂ ...). Current source circuit according to one of the preceding claims, characterized in that a current source transistor (T8) is provided which is driven by the first current mirror (T1, T2) and that a bipolar transistor (Q1) connected as a diode with its as the reference voltage source (Q _ref ) Emitter-collector path is arranged in series with the current source transistor (T8), the collector electrode being at the potential of the operating voltage source (V _DD ) and the reference voltage V _{BE being} tapped off at the emitter electrode. Current source circuit according to one of the preceding claims, characterized in that the current source circuit is implemented in CMOS technology.

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