EP0623865A2 - Current source arrangement - Google Patents

Current source arrangement Download PDF

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Publication number
EP0623865A2
EP0623865A2 EP94106767A EP94106767A EP0623865A2 EP 0623865 A2 EP0623865 A2 EP 0623865A2 EP 94106767 A EP94106767 A EP 94106767A EP 94106767 A EP94106767 A EP 94106767A EP 0623865 A2 EP0623865 A2 EP 0623865A2
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EP
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Prior art keywords
transistor
current source
transistors
parallel
arrangement according
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EP94106767A
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German (de)
French (fr)
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EP0623865B1 (en
EP0623865A3 (en
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Dieter Dr. Dipl.-Ing. Draxelmayr
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Siemens AG
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Siemens AG
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only

Definitions

  • the invention relates to a current source arrangement with a current source that feeds two antivalent controlled transistors lying in parallel.
  • Circuits with current output are known in a variety of applications. A distinction is made between circuits which switch the output current on and off and those circuits which switch the current between an output path and another path. The latter type of circuit is very suitable for fast circuits, i. H. for circuits with high cut-off frequencies.
  • a typical area of application for circuits with current output are D / A converters.
  • D / A converters For example, from publication Y.Nakamura: A 10-b 70-MS / s CMOS D / A Converter ", IEEE Journal of Solid-State Circuits, Vol. 26, No. 4, April 1991, pp.
  • each current cell contains a current source which is controlled by a bias voltage and which feeds transistors lying in parallel in an equivalent manner, that is to say with complementary signals, and the publication states that it is favorable to have such a current cell from p-channel
  • Other common parameters of such circuits in CMOS technology are their supply voltage of 5 V with a fluctuation of +/- 10%, an output voltage of 1.4 V at 75 ohms and an upper limit frequency of a few 10 MHz with a resolution of at least 8 bits.
  • the invention is based on the object of specifying a current source arrangement and its use which can be used for high cut-off frequencies and which produces only slight interference during switching operations.
  • the invention has the advantage that the connection point of the two transistors of the cascode stage used as the current source and the feed point of the current source in the switch arrangement are excellently decoupled statically and dynamically, so that the switching operations of the switch transistors are kept away from the sensitive and slow current source transistor controlled by a bias voltage can be. Small switch transistors can also be used so that interference injections remain low even at high cut-off frequencies.
  • the invention offers the further advantage that it can also be used to build larger circuit arrangements, the individual current source arrangements of which are decoupled from one another.
  • Embodiments of the invention are characterized in the subclaims.
  • the transistors P1 and P2 connected as cascode form the actual current source.
  • the p-channel transistor P1 has its output circuit in series with the output circuit of the p-channel transistor P2.
  • P1 is controlled by a bias voltage at terminal B1 and forms a current source transistor.
  • the transistor P2 is a cascode transistor for the transistor P1.
  • the connection point K 1 of the output circuits of P1 and P2 controls a control transistor P3 which, like P1, is connected to an output terminal to a positive supply voltage VCC.
  • the other output connection of the p-channel transistor P3 is connected on the one hand to the control connection of the cascode transistor P2 and on the other hand to an output connection of a transistor N1.
  • the other output terminal of transistor N1 is at reference potential GND, while its control terminal is connected to a further bias voltage via terminal B2.
  • the transistor N1 serves as a current source for the transistor P3.
  • the output of the current source at node K2 feeds two parallel n-channel switch transistors S1 and S2.
  • the control connections of the switch transistors S1 and S2 are antivalent, that is to say controlled with complementary signals, and for this purpose are connected to respective terminals SQ and S at which the complementary signals are located.
  • the free output connections of transistors S1 and S2 form the outputs of the current source arrangement with terminals IQ and I.
  • the circuit according to FIG. 1 works as follows. With the forward or. Reference voltage, the output current of the current source arrangement is essentially defined. P1 is typically a relatively large transistor, so that larger coupling capacitances and therefore longer time constants must be taken into account at P1.
  • the second transistor P2 of the current source fulfills two functions: First, the transistor P2 increases the differential output resistance of the current source, which improves the static characteristic. On the other hand, P2 ensures dynamic decoupling of the circuit nodes K1 and K2, i. H. of the output terminals of transistor P2. This results in a rapid settling of the current source arrangement. With the decoupling of nodes K1 and K2, it is prevented that interference at K1 due to switching operations of the switch transistors reach terminal B1 via transistor P1 and can influence other current source arrangements controlled by terminal B1.
  • the arrangement with the transistors P2, P3 and N1 forms a closed control loop which regulates the potential at K1 to a constant value independently of the processes at K2.
  • the n-channel transistor N1 controlled by the further bias voltage at the terminal B2 forms the current source for the transistor P3.
  • the actual control loop thus consists only of the relatively small transistors P2 and P3. This means that the control loop enables fast control.
  • the control loop from P2 and P3 thus ensures that the potential at node K1 is compensated for a change at node K2 in the sense of keeping K1 constant.
  • n-channel transistors S1 and S2 work as switches and are therefore not additional cascode transistors.
  • p-channel types are also possible as switch transistors. With a low voltage reserve, however, it is not intended to use transistors of the p-channel type instead of the n-channel switch transistors S1 and S2.
  • FIG. 2 shows a further exemplary embodiment of a current source arrangement, in which the same elements as in FIG. 1 are shown with the same reference numerals.
  • the arrangement differs from FIG. 1 in the implementation of the current source for the transistor P2 and in a transistor TC connected in parallel with the switch transistors S1 and S2, which acts as a capacitor.
  • the capacitor TC is intended to smooth the voltage curve at the node K2 during the current transition from one switch S1 to the other switch S2 and vice versa.
  • the actual current source is supplied by a supply voltage VCCI, while the circuit part is supplied with the control transistor P3 by a supply voltage VCCA, which is typically of the same level.
  • a p-channel transistor P4 connected to VCCI is controlled by the bias voltage at terminal B1 and generates a current which is translated into the branch with the control transistor P3 with the aid of a current mirror formed from the n-kakal transistors N2 and N3.
  • the transistor N2 connected as a diode is connected with its drain and gate to P4, while the transistor N3 is connected with its drain to the transistor P3.
  • the gate connections of N2 and N3 are connected to each other. Both transistors N2 and N3 are connected on the source side to reference potential GND.
  • the advantage of the current source arrangement shown in FIG. 2 is that the local current generation implemented for the current source arrangement or current cell of FIG. 2 guarantees freedom of coupling when several current cells are connected to one another.
  • the switch transistors S1 and S2 are designed asymmetrically.
  • the switching transistor S1 absorbs the current from the current source when it is not used at output 1. For this reason, the output IQ is set to 0 V or reference potential GND. Since this potential at terminal IQ is lower than the potential at terminal 1, it can be achieved with an asymmetrical configuration of transistors S1 and S2 that the voltage at node K2 makes only small jumps when switching between the switch transistors.
  • the ratio of channel width to channel length can be lower for transistor S1 than for transistor S2.
  • a possible value of channel width / channel length is 18/4 for S1 and 75/4 for S2.
  • the invention shown in the figures enables good static and dynamic decoupling of the circuit points K1 and K2. This allows switching operations on the switch transistors S1 and S2 to be kept away from the sensitive and slow current source transistor P1.
  • the use of small switching transistors S1 and S2 generally leads to only slight interference coupling of the switching signals into other circuit parts.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Analogue/Digital Conversion (AREA)
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Abstract

The current source device has a current source supplying a pair of exclusive=OR parallel transistors (S1,S2). The current source comprises a regulated cascade stage (P1,P2,P3,N1). The first transistor (P1) is controlled by a bias voltage (B1) and the control input of the second transistor (P2) is coupled to the output of a regulating transistor (P3). The control input of the latter is coupled to a junction (K1) between the first two transistors. The cascade transistors and the regulating transistors are of p-channel type, the parallel transistors being of n-channel type.

Description

Die Erfindung betrifft eine Stromquellenanordnung mit einer Stromquelle, die zwei antivalent gesteuerte parallel liegende Transistoren speist.The invention relates to a current source arrangement with a current source that feeds two antivalent controlled transistors lying in parallel.

Schaltungen mit Stromausgang sind in vielfältigen Anwendungen bekannt. Man unterscheidet dabei Schaltungen, die den Ausgangsstrom ein- bzw. ausschalten und solche Schaltungen, die den Strom zwischen einem Ausgangspfad und einem anderen Pfad umschalten. Der letztere Schaltungstyp eignet sich sehr gut für schnelle Schaltungen, d. h. für Schaltungen mit hohen Grenzfrequenzen.Circuits with current output are known in a variety of applications. A distinction is made between circuits which switch the output current on and off and those circuits which switch the current between an output path and another path. The latter type of circuit is very suitable for fast circuits, i. H. for circuits with high cut-off frequencies.

Ein typisches Einsatzgebiet für Schaltungen mit Stromausgang sind D/A-Wandler. So ist aus der Veröffentlichung Y.Nakamura: A 10-b 70-MS/s CMOS D/A Converter", IEEE Journal of Solid-State Circuits, Vol. 26, No. 4, April 1991, pp. 637-642 ein D/A-Umsetzer mit einer Stromzellenmatrix bekannt. Jede Stromzelle enthält eine von einer Vorspannung gesteuerte Stromquelle, die antivalent, d. h. mit komplementären Signalen gesteuerte parallel liegende Transistoren speist. Die Veröffentlichung führt aus, daß es günstig ist, eine derartige Stromzelle aus p-Kanal-Transistoren aufzubauen. Weitere übliche Parameter derartiger Schaltungen in CMOS-Technologie ist ihre Versorgungsspannung von 5 V mit einer Schwankung von +/-10%, eine Ausgangsspannung von 1,4 V an 75 Ohm sowie eine obere Grenzfrequenz von einigen 10 Mhz bei einer Auflösung von mindestens 8 bit.A typical area of application for circuits with current output are D / A converters. For example, from publication Y.Nakamura: A 10-b 70-MS / s CMOS D / A Converter ", IEEE Journal of Solid-State Circuits, Vol. 26, No. 4, April 1991, pp. 637-642 D / A converter with a current cell matrix known.Each current cell contains a current source which is controlled by a bias voltage and which feeds transistors lying in parallel in an equivalent manner, that is to say with complementary signals, and the publication states that it is favorable to have such a current cell from p-channel Other common parameters of such circuits in CMOS technology are their supply voltage of 5 V with a fluctuation of +/- 10%, an output voltage of 1.4 V at 75 ohms and an upper limit frequency of a few 10 MHz with a resolution of at least 8 bits.

Der Erfindung liegt die Aufgabe zugrunde, eine Stromquellenanordnung und ihre Verwendung anzugeben, die sich für hohe Grenzfrequenzen einsetzen läßt und bei Schaltvorgängen nur geringe Störungen erzeugt.The invention is based on the object of specifying a current source arrangement and its use which can be used for high cut-off frequencies and which produces only slight interference during switching operations.

Diese Aufgabe wird mit den Merkmalen der Patentansprüche 1 und 7 gelöst.This object is achieved with the features of claims 1 and 7.

Die Erfindung hat den Vorteil, daß der Verbindungspunkt der beiden Transistoren der als Stromquelle verwendeten Kaskodestufe und der Einspeisepunkt der Stromquelle in die Schalteranordnung statisch und dynamisch ausgezeichnet entkoppelt sind, so daß die Schaltvorgänge der Schaltertransistoren von dem empfindlichen und langsamen, von einer Vorspannung gesteuerten Stromquellentransistor ferngehalten werden können. Weiterhin können kleine Schaltertransistoren verwendet werden, so daß Störeinkopplungen auch bei hohen Grenzfrequenzen gering bleiben. Die Erfindung bietet den weiteren Vorteil, daß sich mit ihr auch größere Schaltungsanordnungen aufbauen lassen, deren einzelne Stromquellenanordnungen voneinander entkoppelt sind.The invention has the advantage that the connection point of the two transistors of the cascode stage used as the current source and the feed point of the current source in the switch arrangement are excellently decoupled statically and dynamically, so that the switching operations of the switch transistors are kept away from the sensitive and slow current source transistor controlled by a bias voltage can be. Small switch transistors can also be used so that interference injections remain low even at high cut-off frequencies. The invention offers the further advantage that it can also be used to build larger circuit arrangements, the individual current source arrangements of which are decoupled from one another.

Ausgestaltungen der Erfindung sind in Unteransprüchen gekennzeichnet.Embodiments of the invention are characterized in the subclaims.

Die Erfindung wird nachfolgend anhand von in den Figuren der Zeichnung dargestellten Ausführungsbeispielen näher beschrieben. Es zeigen:

Figur 1
eine erste Ausführungsform der Erfindung und
Figur 2
eine weitere erfindungsgemäße Stromquellenanordnung.
The invention is described below with reference to exemplary embodiments shown in the figures of the drawing. Show it:
Figure 1
a first embodiment of the invention and
Figure 2
a further current source arrangement according to the invention.

In der Stromquellenanordnung gemäß Figur 1 bilden die als Kaskode geschalteten Transistoren P1 und P2 die eigentliche Stromquelle. Der p-Kanal-Transistor P1 liegt mit seinem Ausgangskreis in Reihe zum Ausgangskreis des p-Kanal-Transistors P2. P1 wird von einer an der Klemme B1 liegenden Vorspannung gesteuert und bildet einen Stromquellentransistor. Der Transistor P2 ist ein Kaskodetransistor für den Transistor P1. Der Verbindungspunkt K 1 der Ausgangskreise von P1 und P2 steuert einen Regeltransistor P3, der mit einem Ausgangsanschluß ebenso wie P1 an einer positiven Versorgungsspannung VCC angeschlossen ist. Der andere Ausgangsanschluß des p-Kanal-Transistors P3 ist einerseits mit dem Steueranschluß des Kaskodetransistors P2 und andererseits mit einem Ausgangsanschluß eines Transistors N1 verbunden. Der andere Ausgangsanschluß des Transistors N1 liegt auf Bezugspotential GND, während sein Steueranschluß an über eine Klemme B2 an einer weiteren Vorspannung liegt. Der Transistor N1 dient als Stromquelle für den Transistor P3.In the current source arrangement according to FIG. 1, the transistors P1 and P2 connected as cascode form the actual current source. The p-channel transistor P1 has its output circuit in series with the output circuit of the p-channel transistor P2. P1 is controlled by a bias voltage at terminal B1 and forms a current source transistor. The transistor P2 is a cascode transistor for the transistor P1. The connection point K 1 of the output circuits of P1 and P2 controls a control transistor P3 which, like P1, is connected to an output terminal to a positive supply voltage VCC. The other output connection of the p-channel transistor P3 is connected on the one hand to the control connection of the cascode transistor P2 and on the other hand to an output connection of a transistor N1. The other output terminal of transistor N1 is at reference potential GND, while its control terminal is connected to a further bias voltage via terminal B2. The transistor N1 serves as a current source for the transistor P3.

Der Ausgang der Stromquelle am Knotenpunkt K2 speist zwei parallel liegende n-Kanal-Schaltertransistoren S1 und S2. Die Steueranschlüsses der Schaltertransistoren S1 bzw. S2 werden antivalent, d. h. mit komplementären Signalen gesteuert und sind dazu mit jeweiligen Klemmen SQ bzw. S verbunden, an denen die komplementären Signale liegen. Die freien Ausgangsanschlüsse der Transistoren S1 und S2 bilden die Ausgänge der Stromquellenanordnung mit den Klemmen IQ bzw. I.The output of the current source at node K2 feeds two parallel n-channel switch transistors S1 and S2. The control connections of the switch transistors S1 and S2 are antivalent, that is to say controlled with complementary signals, and for this purpose are connected to respective terminals SQ and S at which the complementary signals are located. The free output connections of transistors S1 and S2 form the outputs of the current source arrangement with terminals IQ and I.

Die Schaltung gemäß Figur 1 arbeitet folgendermaßen. Mit der an der Klemme B1 liegenden Vor-bzw. Referenzspannung wird der Ausgangsstrom der Stromquellenanordnung im wesentlichen definiert. P1 ist typischerweise ein relativ großer Transistor, so daß an P1 größere Koppelkapazitäten und damit längere Zeitkonstanten beachtet wewrden müssen.The circuit according to FIG. 1 works as follows. With the forward or. Reference voltage, the output current of the current source arrangement is essentially defined. P1 is typically a relatively large transistor, so that larger coupling capacitances and therefore longer time constants must be taken into account at P1.

Der zweite Transistor P2 der Stromquelle erfüllt zwei Funktionen: Zum einen erhöht der Transistor P2 den differentiellen Ausgangswiderstand der Stromquelle, wodurch sich die statische Kennlinie verbessert. Zum anderen gewährleistet P2 eine dynamische Entkopplung der Schaltungsknoten K1 und K2, d. h. der Ausgangsanschlüsse des Transistors P2. Dadurch ergibt sich ein schnelles Einschwingen der Stromquellenanordnung. Mit der Entkopplung der Knoten K1 und K2 wird verhindert, daß Störungen an K1 aufgrund von Schaltvorgängen der Schaltertransistoren über den Transistor P1 an die Klemme B1 gelangen und weitere von der Klemme B1 gesteuerte Stromquellenanordnungen beeinflussen können.The second transistor P2 of the current source fulfills two functions: First, the transistor P2 increases the differential output resistance of the current source, which improves the static characteristic. On the other hand, P2 ensures dynamic decoupling of the circuit nodes K1 and K2, i. H. of the output terminals of transistor P2. This results in a rapid settling of the current source arrangement. With the decoupling of nodes K1 and K2, it is prevented that interference at K1 due to switching operations of the switch transistors reach terminal B1 via transistor P1 and can influence other current source arrangements controlled by terminal B1.

Die Anordnung mit den Transistoren P2, P3 und N1 bildet einen geschlossenen Regelkreis, der das Potential an K1 unabhängig von den Vorgängen an K2 auf einen konstanten Wert regelt. Der von der weiteren Vorspannung an der Klemme B2 gesteuerte n-Kanal-Transistor N1 bildet die Stromquelle für den Transistor P3. Der eigentliche Regelkreis besteht somit lediglich aus den relativ kleinen Transistoren P2 und P3. Das bedeutet, daß der Regelkreis eine schnelle Regelung ermöglicht. Der Regelkreis aus P2 und P3 sorgt somit dafür, daß das Potential am Knoten K1 gegenüber einer Änderung am Knoten K2 im Sinne einer Konstanthaltung an K1 ausgeregelt wird.The arrangement with the transistors P2, P3 and N1 forms a closed control loop which regulates the potential at K1 to a constant value independently of the processes at K2. The n-channel transistor N1 controlled by the further bias voltage at the terminal B2 forms the current source for the transistor P3. The actual control loop thus consists only of the relatively small transistors P2 and P3. This means that the control loop enables fast control. The control loop from P2 and P3 thus ensures that the potential at node K1 is compensated for a change at node K2 in the sense of keeping K1 constant.

Die n-Kanal-Transistoren S1 und S2 arbeiten als Schalter und sind somit nicht zusätzliche Kaskodetransistoren. Grundsätzlich sind als Schaltertransistoren auch p-Kanal-Typen möglich. Bei einer geringen Spannungsreserve ist aber nicht vorgesehen, anstelle der n-Kanal-Schaltertransistoren S1 und S2 Transistoren vom p-Kanal-Typ einzusetzen. Bei der erfindungsgemäßen Anordnung ist es möglich, für die Schaltertransistoren S1 und S2 vergleichsweise kleine Transistoren zu verwenden, da aufgrund der verfügbaren, vergleichsweise hohen Steuerspannung kein hoher Spannungsabfall am jeweiligen Schaltertransistor auftritt. Damit können auch bei hohen Grenzfrequenzen die von der Stgromquellenanordnung erzeugten Störungen klein gehalten werden.The n-channel transistors S1 and S2 work as switches and are therefore not additional cascode transistors. In principle, p-channel types are also possible as switch transistors. With a low voltage reserve, however, it is not intended to use transistors of the p-channel type instead of the n-channel switch transistors S1 and S2. In the arrangement according to the invention, it is possible to use comparatively small transistors for the switch transistors S1 and S2, since, due to the comparatively high control voltage available, there is no high voltage drop across the respective switch transistor. The disturbances generated by the current source arrangement can thus be kept small even at high cut-off frequencies.

Figur 2 zeigt ein weiteres Ausführungsbeispiel einer Stromquellenanordnung, in der gleiche Elemente wie in Figur 1 mit gleichen Bezugszeichen dargestellt sind. Die Anordnung unterscheidet sich von der Figur 1 in der Realisierung der Stromquelle für den Transistor P2 und in einem parallel zu den Schaltertransistoren S1 und S2 geschalteten Transistor TC, der als Kondensator wirkt. Der Kondensator TC soll den Spannungsverlauf am Knotenpunkt K2 beim Stromübergang von einem Schalter S1 zum anderen Schalter S2 und umgekehrt glätten.FIG. 2 shows a further exemplary embodiment of a current source arrangement, in which the same elements as in FIG. 1 are shown with the same reference numerals. The arrangement differs from FIG. 1 in the implementation of the current source for the transistor P2 and in a transistor TC connected in parallel with the switch transistors S1 and S2, which acts as a capacitor. The capacitor TC is intended to smooth the voltage curve at the node K2 during the current transition from one switch S1 to the other switch S2 and vice versa.

Gemäß Figur 2 ist die eigentliche Stromquelle von einer Versorgungsspannung VCCI versorgt, während der Schaltungsteil mit dem Regeltransistor P3 von einer typischerweise gleich hohen Versorgungsspannung VCCA versorgt wird. Gemäß Figur 2 wird ein an VCCI angeschlossener p-Kanal-Transistor P4 von der Vorspannung an der Klemme B1 gesteuert und erzeugt einen Strom, der mit Hilfe eines aus den n-Kakal-Transistoren N2 und N3 gebildeten Stromspiegels in den Zweig mit dem Regeltransistor P3 übersetzt wird. Dazu ist der als Diode geschaltete Transistor N2 mit seinem Drain und Gate an P4 angeschlossen, während der Transistor N3 mit seinem Drain am Transistor P3 angeschlossen ist. Die Gate-Anschlüsse von N2 und N3 sind miteinander verbunden. Beide Transistoren N2 und N3 sind sourceseitig an Bezugspotential GND angeschlossen.According to FIG. 2, the actual current source is supplied by a supply voltage VCCI, while the circuit part is supplied with the control transistor P3 by a supply voltage VCCA, which is typically of the same level. According to FIG. 2, a p-channel transistor P4 connected to VCCI is controlled by the bias voltage at terminal B1 and generates a current which is translated into the branch with the control transistor P3 with the aid of a current mirror formed from the n-kakal transistors N2 and N3. For this purpose, the transistor N2 connected as a diode is connected with its drain and gate to P4, while the transistor N3 is connected with its drain to the transistor P3. The gate connections of N2 and N3 are connected to each other. Both transistors N2 and N3 are connected on the source side to reference potential GND.

Der Vorteil der in Figur 2 gezeigten Sromquellenanordnung besteht darin, daß die für die Stromquellenanordnung bzw. Stromzelle der Figur 2 realisierte lokale Stromerzeugung bei der Verschaltung mehrerer Stromzellen untereinander eine Verkoppelungsfreiheit garantiert.The advantage of the current source arrangement shown in FIG. 2 is that the local current generation implemented for the current source arrangement or current cell of FIG. 2 guarantees freedom of coupling when several current cells are connected to one another.

Bei der Stromquellenanordnung der Figur 2 ist vorgesehen, die Schaltertransistoren S1 und S2 unsymmetrisch auszubilden. Der Schalttransistor S1 nimmt den Strom der Stromquelle auf, wenn er am Ausgang 1 nicht gebraucht wird. Aus diesem Grund ist der Ausgang IQ auf 0 V bzw. Bezugspotential GND gelegt. Da dieses Potential an der Klemme IQ niedriger als das Potential an der Klemme 1 ist, kann mit einer unsymmetrischen Ausbildung der Transistoren S1 und S2 erreicht werden, daß die Spannung am Knotenpunkt K2 beim Umschalten zwischen den Schaltertransistoren nur kleine Sprünge macht. So kann das Verhältnis von Kanalweite zu Kanallänge beim Transistor S1 niedriger sein als beim Transistor S2. Ein möglicher Wert von Kanalweite/Kanallänge beträgt für S1 18/4 und für S2 75/4.In the current source arrangement of FIG. 2, it is provided that the switch transistors S1 and S2 are designed asymmetrically. The switching transistor S1 absorbs the current from the current source when it is not used at output 1. For this reason, the output IQ is set to 0 V or reference potential GND. Since this potential at terminal IQ is lower than the potential at terminal 1, it can be achieved with an asymmetrical configuration of transistors S1 and S2 that the voltage at node K2 makes only small jumps when switching between the switch transistors. The ratio of channel width to channel length can be lower for transistor S1 than for transistor S2. A possible value of channel width / channel length is 18/4 for S1 and 75/4 for S2.

Die Erzeugung der Vor-bzw. Referenzspannungen und der komplementären Signale ist bekannt.The generation of the pre or. Reference voltages and the complementary signals are known.

Die in den Figuren dargestellte Erfindung ermöglicht eine gute statische und dynamische Entkopplung der Schaltungspunkte K1 und K2. Dadurch können Schaltvorgänge an den Schaltertransistoren S1 und S2 von dem empfindlichen und langsamen Stromquellentransistor P1 ferngehalten werden. Die Verwendung kleiner Schalttransistoren S1 und S2 führt generell zu nur geringen Störeinkopplungen der Schaltsignale in andere Schaltungsteile.The invention shown in the figures enables good static and dynamic decoupling of the circuit points K1 and K2. This allows switching operations on the switch transistors S1 and S2 to be kept away from the sensitive and slow current source transistor P1. The use of small switching transistors S1 and S2 generally leads to only slight interference coupling of the switching signals into other circuit parts.

Claims (7)

Stromquellenanordnung mit einer Stromquelle, die zwei antivalent gesteuerte parallel liegende Transistoren speist, dadurch gekennzeichnet, daß die Stromquelle (P1, P2, P3, N1) als geregelte Kaskodestufe ausgebildet ist, deren erster Transistor (P1) von einer Vorspannung (B1) gesteuert wird und deren zweiter Transistor (P2) an seinem Eingang mit dem vom Ausgang eines Regeltransistors (P3) verbunden ist, der eingangsseitig an dem Verbindungspunkt (K1) des ersten und des zweiten Transistors angeschlossen ist.Current source arrangement with a current source that feeds two antivalently controlled transistors lying in parallel, characterized in that the current source (P1, P2, P3, N1) is designed as a regulated cascode stage, the first transistor (P1) of which is controlled by a bias voltage (B1) and whose second transistor (P2) is connected at its input to that of the output of a control transistor (P3) which is connected on the input side to the connection point (K1) of the first and the second transistor. Anordnung nach Anspruch 1, dadurch gekenn zeichnet, daß die Stromquellentransistoren (P1, P2) und der Regeltransistor (P3) jeweils vom p-Kanal-Typ und die parallel liegenden Transistoren (S1, S2) jeweils vom n-Kanal-Typ sind.Arrangement according to claim 1, characterized in that the current source transistors (P1, P2) and the control transistor (P3) are each of the p-channel type and the parallel transistors (S1, S2) are each of the n-channel type. Anordnung nach Anspruch 1 oder 2, dadurch gekennzeichnet, daß der Regeltransistor (P3) von einer Stromquelle (N1; P4, N2, N3) gespeist wird.Arrangement according to claim 1 or 2, characterized in that the control transistor (P3) is fed by a current source (N1; P4, N2, N3). Anordnung nach einem der Ansprüche 1 bis 3, dadurch gekennzeichnet, daß in Serie zu dem Regeltransistor (P3) ein Transistor ( N3) eines Stromspiegels (N2, N3) liegt, dessen anderer Transistor (N2) in Serie zu einem weiteren Transistor (P4) geschaltet ist, der von der Vorspannung (B1) gesteuert wird.Arrangement according to one of claims 1 to 3, characterized in that a transistor (N3) of a current mirror (N2, N3) is located in series with the control transistor (P3), the other transistor (N2) in series with a further transistor (P4) is switched, which is controlled by the bias voltage (B1). Anordnung nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, daß parallel zu den parallel liegenden Transistoren (S1, S2) eine Kapazität (TC) geschaltet ist.Arrangement according to one of the preceding claims, characterized in that parallel to the ones lying in parallel Transistors (S1, S2) a capacitance (TC) is connected. Anordnung nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, daß die parallel liegenden Transistoren (S1, S2) unterschiedliche Transistorgeometrien haben.Arrangement according to one of the preceding claims, characterized in that the transistors (S1, S2) lying in parallel have different transistor geometries. Verwendung einer Stromquellenanordnung nach einem der vorhergehenden Ansprüche in einem Digital-Analog-Umsetzer.Use of a current source arrangement according to one of the preceding claims in a digital-to-analog converter.
EP94106767A 1993-05-07 1994-04-29 Current source arrangement Expired - Lifetime EP0623865B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE4315299 1993-05-07
DE4315299A DE4315299C1 (en) 1993-05-07 1993-05-07 Current source device for D=A converter

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EP0623865A2 true EP0623865A2 (en) 1994-11-09
EP0623865A3 EP0623865A3 (en) 1995-01-11
EP0623865B1 EP0623865B1 (en) 1997-11-05

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Publication number Priority date Publication date Assignee Title
DE19746950C2 (en) * 1997-01-31 2003-11-06 Lg Semicon Co Ltd Digital-to-analog converter

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Publication number Priority date Publication date Assignee Title
US3995177A (en) * 1973-01-02 1976-11-30 Fairchild Camera And Instrument Corporation Electronic watch
US4769559A (en) * 1987-06-02 1988-09-06 Motorola, Inc. Switchable current source
EP0483537A2 (en) * 1990-10-29 1992-05-06 TEMIC TELEFUNKEN microelectronic GmbH Current source circuit
EP0531615A2 (en) * 1991-08-09 1993-03-17 Nec Corporation Temperature sensor circuit and constant-current circuit

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US3995177A (en) * 1973-01-02 1976-11-30 Fairchild Camera And Instrument Corporation Electronic watch
US4769559A (en) * 1987-06-02 1988-09-06 Motorola, Inc. Switchable current source
EP0483537A2 (en) * 1990-10-29 1992-05-06 TEMIC TELEFUNKEN microelectronic GmbH Current source circuit
EP0531615A2 (en) * 1991-08-09 1993-03-17 Nec Corporation Temperature sensor circuit and constant-current circuit

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Title
1990 SYPOSIUM ON VLSI CIRCUITS, 7. Juni 1990, HONOLULU Seiten 55 - 56 KUMAZAWA ET AL. 'An 8 bit 150 MHz CMOS D/A Converte with 2 Vp-p wide range output.' *
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ELECTRONICS LETTERS, Bd.28, Nr.9, 23. April 1992, ENAGE GB Seiten 820 - 822 WEY ET AL. 'Current mode divide by two circuit' *
IEEE 1991 CUSTOM INTEGRATED CIRCUITS CONFERENCE., 12. Mai 1991, SAN DIEGO Seiten 26.5.1 - 26.5.4 TAKAKURA ET AL. 'A 10 bit 80 MHz Glitchless CMOS D/A Converter.' *
IEEE INTERNATIONAL SOLID STATE CIRCUITS CONFERENCE, Bd.32, Februar 1989, NEW YORK US GROENEVELD ET AL. 'A self Calibration Technique for Monolothic High-Resolution D/A Converters.' *

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EP0623865B1 (en) 1997-11-05
DE59404502D1 (en) 1997-12-11
DE4315299C1 (en) 1994-06-23
EP0623865A3 (en) 1995-01-11

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