EP0464620A2

EP0464620A2 - Image information control apparatus and display system

Info

Publication number: EP0464620A2
Application number: EP91110530A
Authority: EP
Inventors: Hiroshi C/O Canon Kabushiki Kaisha Inoue
Original assignee: Canon Inc
Current assignee: Canon Inc
Priority date: 1990-06-27
Filing date: 1991-06-26
Publication date: 1992-01-08
Anticipated expiration: 2011-06-26
Also published as: DE69123182D1; DE69123182T2; EP0464620B1; ATE145492T1; KR950012016B1; KR920001418A; EP0464620A3; JP2840398B2; JPH0458221A

Abstract

An image information control apparatus includes a partial write detector having at least two types of memory units for detecting and storing addresses accessed to a VRAM in units of lines in a scanning direction, thereby repeating the detection and the storage at different cycles, a circuit for performing calculations to recognize partial write information from contents of each of the memory units, memory units for storing the respective calculation results, a circuit for comparing the memory contents to determine a size relationship between partial write areas, a partial write ID signal controller for controlling a partial write ID signal on the basis of the size relationship between partial write areas and externally outputting the signal, and a circuit for, even when partial writing is being executed, forcibly interrupting the partial writing in accordance with a state of an external refresh control signal, starting refresh, and restarting the partial writing in accordance with a partial write state and a change in state of the refresh control signal.

Description

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates to a display system and, more particularly, to an image information control apparatus for use in a display system using a ferroelectric liquid crystal having a memory function.

Related Background Art

The screen size and the resolution of a liquid crystal display system required in a personal computer (PC) or a work station (WS) have been increased year by year, and the system is required to have compatibility with a conventional PC or WS.
Especially when a display panel using a ferroelectric liquid crystal (FLCD) imparted with a memory function is adopted in a PC or a WS, it is required to smoothly move, e.g., a mouse or a cursor to perform display. Such a moving display is realized by a partial writing system (in which only scan lines corresponding to an area to be partially rewritten are scanned) as disclosed in U.S. Patent No. 4,655,561. In the PS or the WS, when a mouse is to be moved and displayed while a partial scroll screen is displayed (also in this case, only scan lines corresponding to the scroll screen are scanned), and especially when the mouse is to be displayed beside the scroll screen, the entire scroll screen is not sometimes displayed.

SUMMARY OF THE INVENTION

It is an object of the present invention to solve the above conventional problem and provide a liquid crystal display system and, more particularly, a ferroelectric liquid crystal display system having improved compatibility with a CRT display system.
It is another object of the present invention to provide an image information control system having improved compatibility with a CRT display system.
According to the first aspect of the present invention, there are provided an image information control apparatus and a display system using the same, the image information system comprising a partial write detector having at least two types of memory units for detecting and storing addresses accessed to a VRAM in units of lines in a scanning direction, thereby repeating the detection and the storage at different cycles, a circuit for performing calculations to recognize partial write information from contents of each of the memory units, memory units for storing the respective calculation results, a circuit for comparing the memory contents to determine a size relationship between partial write areas, a partial write ID signal controller for controlling a partial write ID signal on the basis of the size relationship between partial write areas and externally outputting the signal, and a circuit for, even when partial writing is being executed, forcibly interrupting the partial writing in accordance with a state of an external refresh control signal, starting refresh, and restarting the partial writing in accordance with a partial write state and a change in state of the refresh control signal.
According to the second aspect of the present invention, there are provided an image information control apparatus and a display system using the same, wherein the partial write information detected in units of lines by the memory units are identified as continuous line address groups in the scan line direction from the accessed address data, the number of addresses, a start line address or an end line address, or the number of lines is calculated for each group, and a total number of accessed lines is calculated.
According to the third aspect of the present invention, there are provided an image information control apparatus and a display system using the same, wherein only access to the VRAM performed during writing is rendered valid.
According to the fourth aspect of the present invention, there are provided an image information control apparatus and a display system using the same, wherein a detection period (sampling period) of the memory units for executing detection and storage in units of lines in the scan direction is shorter than a storage period thereof.
According to the fifth aspect of the present invention, there are provided an image information control apparatus and a display system using the same, wherein when the size relationship between the partial write areas obtained from the partial write information is to be determined, a detection period (sampling period) of a memory unit having partial write information of a larger area is shorter than a storage period thereof.
According to the sixth aspect of the present invention, there are provided an image information control apparatus and a display system using the same, wherein a cycle of determining the size relationship between the partial write areas obtained from the partial write information is synchronized with a cycle of the partial write detector for repeating detection and storage such that the cycles are integer multiples with respect to the different memory units, respectively.

BRIEF DESCRIPTION OF THE DRAWINGS

Fig. 1 is a block diagram showing an apparatus of the present invention;
Fig. 2 is a view for explaining a multitask used in the present invention;
Fig. 3 is a timing chart showing timings used in the present invention;
Fig. 4 is a timing chart for realizing forced refresh (LL) used in the present invention;
Fig. 5 is a block diagram showing hardware used in the present invention;
Fig. 6 is a block diagram showing a static memory;
Fig. 7 is a view for explaining a case 1;
Fig. 8 is a view for explaining a case 2;
Fig. 9 is a view for explaining a case 3;
Fig. 10 is a view for explaining a case 4;
Fig. 11 is a view for explaining a case 5;
Fig. 12 is a view for explaining a case 6;
Fig. 13 is a view for explaining a case 7;
Fig. 14 is a view for explaining a case 8;
Fig. 15 is a view for explaining a case 9;
Fig. 16 is a view for explaining a case 10;
Fig. 17 is a timing chart of the present invention (according to claim 4);
Fig. 18 is a view for explaining a sampling H/W used in the present invention;
Fig. 19 is a view for explaining a scheduler in an X-window used in the present invention;
Figs. 20 and 21 are schematic views for explaining graphic command execution; and
Fig. 22 is a view of explaining VRAM access.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

An apparatus and a system according to the present invention are suitable as a display using an FLCD (ferroelectric liquid crystal) imparted with a memory function and can allow use of both a partial writing method of realizing moving display such as a mouse or a cursor and a total-refresh scanning driving method.
A partial writing method used in the present invention is basically performed as follows.

① When a drawing request requires partial writing, total refresh is interrupted, and a partial write area on a screen is scanned in a non-interlace manner.
② When the partial writing is finished, the refresh is restarted.

An actual operation is not so simple as described above but requires the following recognitions:

[1] To recognize which drawing request is highest-priority partial writing

This recognition will be described below by taking Fig. 20 as an example. Fig. 20 illustrates four events, i.e., three independent windows and a moving mouse font. A window ① displays a clock, a window ② displays a rotationally moving line, and a window 3 displays vertical scrolling of characters. The respective windows have different display speeds and display asynchronous with each other (independent events). Since a one-line access time of an FLCD remains unchanged, provided that a temperature is constant, a time (scanning time) required to perform each window display by partial writing is proportional to the size of a partial write area. If partial writing is generated in one window while partial writing is executed in another, one of the windows partial writing of which is executed prior to the other must be determined. For this reason, a priority order for partial writing operations must be predetermined when an event occurs so that the priority order is recognized to perform processing by predetermined procedures each time partial write request is generated. For example, the priority order is determined such that partial writing during scroll display is interrupted, clock display partial writing is performed, and then the interrupted partial writing is restarted, and procedures between the respective partial writing operations are determined accordingly.

[2] To have graphic scheduler for partial writing

The concept of priority order is unsatisfactory in a multitask system such as a UNIX/X-Window. In such a system, several requests simultaneously access partial writing and are stored in host queues (Fig. 19). Thereafter, these requests are transferred from the respective host queues to a queue buffer of a server either via a network or internally. In this case, however, the requests are set in the buffer of the server while their drawing order to a VRAM is held. Therefore, the priority order does not work well because the requests are processed in accordance with the drawing order. For example, although "mouse" has the highest priority, if a large number of image drawing requests to the VRAM are present before the mouse request, the mouse request is not executed until the foregoing requests are finished. That is, the mouse request cannot have the highest priority order in this multitask system (Fig. 20).
To solve the above problem, a graphic scheduler is introduced. This scheduler functions to give a proper priority order for partial writing to a request from a queue of a host (Fig. 21).
The basic concepts of the FLCD H/W interface of the present invention are as follows.

① The start, the end, and the number of a group of continuous lines accessed to a VRAM are calculated, and the data is stored in a "stack".
② Several groups are simultaneously detected for each period (different from the S/W case).
③ In the "stack", a margin for a certain time can include the above several groups.
④ Several stacks can be obtained in a priority order.
⑤ The last partial writing access has the highest priority.

Fig. 1 is a block diagram showing an apparatus of the present invention, in which a register for catching access information to a VRAM is illustrated. This information is transferred to an external circuit to count the number of partial writing operations or is transferred to another memory.
This register adopts at-random inputs and serial outputs.
Fig. 2 shows a multistack for obtaining a priority order in the present invention. A stack 1 stores a partial write area for every Δt. On the other hand, a stack 2 basically stores a partial write area for every 2Δt in order to obtain a priority order.
In this case, the depth level of each stack is not determined.
Fig. 3 shows switching timings between partial writing and refresh in the present invention.
A value B represents the number of switching times. If A exceeds B, all of partial writing operations must be interrupted to maintain a screen image by refresh.
In a current FLCD, however, it is difficult to set a fixed B.
Fig. 4 shows two signals PAR and REF for performing switching between partial writing and refresh in the present invention. Referring to Fig. 3, a new GSP is controlling switching between partial writing and refresh.
In a GSP (tradename: available from Texas Instruments), the value "B" for an FLCD cannot be recognized, and the end of refresh in continuous partial write requests cannot be determined.
Therefore, this partial write H/W supplies the signal PAR to a new FLCD controller, and the FLCD controller supplies the signal REF to the H/W to perform refresh, independently of each other.
Fig. 5 shows several hardware of the present invention. Although Fig. 5 is not correct, it provides a concept. Double buffers are preferably used in a sampling register and a memory register.
These registers are alternately used.
Each register is constituted by a large number of F.F.s (Flip-Flops) or a static memory.
When F.F.s are used, a read register is serially reset (Fig. 5).
When a static memory is used (Fig. 6), however, another hardware must be used to serially read data, and data "0" must be overwritten at all addresses by still another hardware upon resetting.
Fig. 6 shows a static memory used in the present invention.

Premise:

An accessed line address is assigned to an address of the static memory.

Sampling:

Data "1" is set at a memory address assigned to an accessed line address.

Transfer:

When a gate is turned off, control is performed such that an address is automatically assigned to an auto-address generator.

Reset:

Upon resetting, an auto-data generator overwrites data "0" at all addresses of the memory while assigning addresses.
A case 1 shown in Fig. 1 shows a practical multi-register arrangement. In this case, only one request is generated, and processing is performed at the highest speed.
A case 2 shown in Fig. 8 shows another arrangement at a middle speed.
A case 3 shown in Fig. 9 shows an arrangement at high and middle speeds.
A case 4 shown in Fig. 10 shows an arrangement at a plurality of speeds. This arrangement has two windows which scroll at different speeds. This condition is strict for partial writing.
A case 5 shown in Fig. 11 is similar to the case 4 except that the sizes and positions of two windows on a screen are different from each other. This condition is also strict for partial writing.
A case 6 shown in Fig. 12 is similar to the case 3 except that the scroll speed of the case 6 is different from that in the case 3. This condition is also strict for partial writing.
A case 7 shown in Fig. 13 is still another arrangement of the case 3, in which an improved method of obtaining a priority order is used.
A case 8 shown in Fig. 14 is still another arrangement of the case 4. This arrangement has two windows which scroll at different speeds. Also in this case, an improved method of obtaining a priority order for partial writing is used.
A case 9 shown in Fig. 15 shows another arrangement of the case 5, in which an improved method of obtaining a priority order is used. This case is no longer hard as compared with the foregoing partial writings.
A case 10 shown in Fig. 16 shows another arrangement of the case 6, in which partial writing is no longer hard as compared with the foregoing cases. Also in this case, a timing chart shown in Fig. 17 is used.
Fig. 17 shows a sequence and switching of actual partial writing and refresh in the present invention according to the arrangement shown in Fig. 16.
Sampling timings and request timings with respect to stacks will be described below.
Referring to Fig. 17, actual sampling timings of stacks 1 and 2 are shifted from each other. Access requests such as a-b, c-d, e-f, and g-h accompanying movement of a circle are detected in the sampling time of the stack 1, and scroll requests are detected in the sampling time of the stack 2. Since long partial writing has a priority to short one, the final result as partial write information is obtained as shown in Fig. 17.
Therefore, actual partial writing and refresh are controlled as follows.

① Refresh before partial writing is interrupted.
② Partial writing is executed for moving circles a-b and c-d.
③ Since the end timing of the a-b and c-d partial writing is before an examination timing of the next partial writing, the stack 1 is in a data indefinite state, and the stack 2 is sampling. Therefore, refresh is executed.
④ When partial write data are determined, the respective stack data are compared with each other, and partial writing of sampling data of the stack 2, a-h, and a scroll request is executed.

Fig. 18 shows a practical example for explaining an actual sampling H/W in an FLCD interface according to the timing chart shown Fig. 17.
Referring to Fig. 18, a scrolling image and a moving circle are present on a screen.

Assumption:

A VRAM access time per bit is 100 nsec.
A VRAM is constituted by 1 M x 8 bits. The size of the circle is 100 x 100 bits, and the scroll size is 1 K x 1 K bits. Therefore, times required for the moving circle and the scrolling window are 0.125 msec. and 12.5 msec., respectively.
The circle moves every 25 msec., and scrolling is performed every 100 msec.

Access to VRAM

Types of access to the VRAM are actually READ access and WRITE access. Strictly speaking, the WRITE access is actually required in terms of partial write control.
Fig. 22 shows an example of copying one window to the other. In this case, a copy source window is accessed to the VRAM in a READ CYCLE, and a copy destination window is accessed in a WRITE CYCLE. Actually, partial writing is started at only the copy destination and need not be performed at the copy source.
Partial writing is always performed after the access to the VRAM in the WRITE CYCLE and need not be performed in the READ CYCLE.
If both the READ and WRITE CYCLEs are used to detect access to the VRAM time consumption for partial writing is doubled.

[2] Scheduler

As described above, the FLCD requires a scheduler under the multitask. In a hardware interface, long partial writing has a priority, or partial write data latched at the start timing of partial writing has a priority. In addition, until one partial writing cycle is finished, another partial writing cycle is not accepted. Therefore, an order of actually generated partial write requests is uniformed during the sampling period, and partial writing operations are simultaneously executed thereafter. For this reason, a priority order of each event is converted into a size relationship between physical partial write areas by the hardware of item [1] above, and simultaneous partial writing operations are superposed within a certain period. Therefore, scheduling of the partial write request order at this timing is assumed to be completed.
As described above, the FLCD partial writing mainly requires two items, and these two items must have the same function in the hardware interface.
The item [1] is related to a priority order, and the item [2] is related to a scheduler. (The scheduler of item [2] above has no clear arrangement but is included in the hardware of item [1] and has a function different therefrom.)
As shown in Figs. 1, 2, 3, and 5 and the basic concept, allocation of priority orders can be obtained by an H/W using the following procedures.

① At least two specific registers are provided.
② With respect to the scan direction, y line accessed to the VRAM is detected by the registers during the respective sampling periods (by using the double buffer technique as shown in Fig. 5). The sampling period is, e.g., a maximum of 25 msec.
③ Obtained data are serially transferred to an external circuit. A transfer clock is, e.g., 10 MHz (Fig. 2).
④ The external circuit checks whether the accessed y lines are only one line or a block having start and end addresses, and calculates the number of accessed lines/blocks or the total number of accessed lines. That is, the serial data is converted into parallel data, and the accessed continuous block in the registers is obtained in an external memory called "stack"s.
⑤ These detected data for partial writing are stored in the respective "stack"s at different sampling periods, e.g., 25 msec. and 50 msec. A stack having two or more sampling periods can be made (Figs. 3 and 4).
⑥ If an image is to be held on a screen while partial writing is continued for a long time period or permanently, the total number of accessed lines must be monitored. However, it is difficult to set B fixed in a hardware manner for the following two reasons.

That is, B means a limited value with respect to the total number. B is probably smaller than the total number of scan lines because if B exceeds the total number, an access time for this partial writing exceeds a frame period. In other words, non-interlace is caused by partial writing over the frame period. For this reason, flicker is easily caused.
In addition, since the frame period changes due to a temperature dependency of the FLCD, B changes in accordance with temperatures. Therefore, no fixed value B can be set.
The other reason, which is important, is that a refresh stop timing must be known during partial writing. This stop timing is also variable due to the temperature dependency of the FLCD. To solve these problems, two control signals (to be described later) are added to the FLCD H/W interface.
There are two ideas of allocating priority orders. The cases 1 to 6 show several examples using an invention that the fastest partial writing has the first priority order.
In this description, assume that the pixel size of the FLCD is 1,024 (vertical) x 1,280 (horizontal) and the frame frequency (refresh rate) at an ordinary use temperature is 20 Hz.
The plurality of registers described above are designed to distinguish priority orders. However, a care must be paid to the cases 3 to 6 for allocating priority orders well.
The cases 3 to 6 suggest that very strict limitations are necessary.
A register 1 detects the fastest movement of, e.g., every 25 msec. (= 40 Hz).
A register 2 detects the second fastest movement of, e.g., every 50 msec. (= 20 Hz).
A register 3, if present, detects the third fastest movement of, e.g., every 100 msec. (= 10 Hz). Although it is assumed that a register 4 detects a movement of every 200 msec. or more, the register 4 is meaningless because refresh of the FLCD is performed at 20 Hz or less (50 msec. or more). The register 3 is unnecessary for the same reason.
Thereafter, the data move to the respective "stack"s as shown in Fig. 2. In the cases 1 and 2, the respective movements are detected and displayed well because there is only one movement in each case.
However, a care must be paid when different movements are simultaneously present as in each of the cases 3 to 6. If the fastest register for partial writing has the highest priority order as described in each drawing operation, it is understood that a very strict limitation is present to complete a plurality of partial writing operations. That is, the frame frequency of the FLCD must be higher than the highest sampling frequency, i.e., 25 msec. (= 40 Hz), and this is impossible in this FLCD.
An opposite assumption with respect to priority order allocation must be made (cases 7 to 10). That is:
The priority order is "stack 2 > stack 1". In other words, until the longest partial writing with respect to an FLCD panel is finished, the stack 1 does not affect the partial writing. This will be described in more detail below. (The cases 1 and 2 are not affected by this new assumption because only one request is present in each case).
In the case 7, on the basis of the new partial writing priority order allocation assumption, the fastest moving object is not continuously displayed but sometimes displayed or interlaced and displayed. In the case 8, the movement of the stack 1 is interlaced as in the case 7.
In the case 9, the same result as in the case 8 is obtained.
In the case 10, the same result as in the case 7 is obtained.
The operation is performed well in all cases (cases 7 to 10) regardless of the speed of the FLCD because until the longest partial writing is finished, another partial writing is interlaced. Therefore, the conventional problem cannot arise.
The last invention about priority order allocation is an actual execution manner. In the above description, it is assumed that partial write data is instantaneously detected by the register and stored during the sampling period. In actual processing, however, a certain period must be consumed in sampling. In addition, the FLCD must have a scheduler for requests simultaneously generated especially under the multitask. Therefore, the H/W FLCD interface operates, for example, as shown in Fig. 17.
Referring to Fig. 17, an actual sampling time of the stack 1 is 12.5 msec., and that of the stack 2 is 25 msec., i.e., twice that of the stack 1. During these periods, it is assumed that the gates to the detectors (registers) are "ON". Each register detects and stores an accessed line address. The sampling interval of the stack 1 is 25 msec., and that of the stack 2 is 50 msec.
As parameters in Fig. 17, Fig. 18 and the case 10 described above are used.
Two images are present on a screen: one is an image of a circle moving at a high speed; and the other, a scrolling window. The circle moves every 25 msec. (= 40 Hz), and the scroll speed is every 100 msec. (= 10 Hz).
The access time of a VRAM per bit is 100 nsec/bit (this speed is considerably higher than other speeds). In this case, eight bits can be simultaneously accessed.
In a scrolling window, one scroll full-screen access time is:

Therefore, one-screen access of the window can be completely detected within the sampling time of 25 msec. of the stack 2. In addition, since the scroll speed is 100 msec. while the sampling interval is 50 msec., partial writing of one scroll screen can be started after the detection.
On the other hand, since two accesses of delete and write are performed as a unit for the circle to display one movement thereof:

Therefore, one moving display access cycle can be completely detected within the sampling time of 12.5 msec. of the stack 1. In addition, since the sampling interval is 25 msec., at least one moving display partial writing cycle can be started for a circle having a moving speed of 25 msec.
A case in which scrolling and a circle are simultaneously present will be described below. This case corresponds to the case 10.
In the description of Fig. 17, when partial writing of the stack 2 for larger partial writing is to be started, a scrolling window includes image information of a circle present on the screen. Partial writing of the circle moving during scrolling is displayed in accordance with information from the stack 1.
If the end of partial writing comes before comparison between the stacks and both the stacks have indefinite sampling data or are executing sampling, refresh is performed until the next comparison time (= ③).
When the next partial write time comes, partial writing is started by interrupting the refresh.
If no partial write data is present, the refresh is, of course, continued until the next partial writing is detected.
According to the present invention, compatibility with respect to a CRT display system is improved by simultaneously displaying partial scrolling and a mouse movement.
An image information control apparatus includes a partial write detector having at least two types of memory units for detecting and storing addresses accessed to a VRAM in units of lines in a scanning direction, thereby repeating the detection and the storage at different cycles, a circuit for performing calculations to recognize partial write information from contents of each of the memory units, memory units for storing the respective calculation results, a circuit for comparing the memory contents to determine a size relationship between partial write areas, a partial write ID signal controller for controlling a partial write ID signal on the basis of the size relationship between partial write areas and externally outputting the signal, and a circuit for, even when partial writing is being executed, forcibly interrupting the partial writing in accordance with a state of an external refresh control signal, starting refresh, and restarting the partial writing in accordance with a partial write state and a change in state of the refresh control signal.

Claims

An image information control apparatus comprising:
a partial write detector having at least two types of memory units for detecting and storing addresses accessed to a VRAM in units of lines in a scanning direction, thereby repeating the detection and the storage at different cycles;
a circuit for performing calculations to recognize partial write information from contents of each of said memory units;
memory units for storing the respective calculation results;
a circuit for comparing the memory contents to determine a size relationship between partial write areas;
a partial write ID signal controller for controlling a partial write ID signal on the basis of the size relationship between partial write areas and externally outputting the signal; and
a circuit for, even when partial writing is being executed, forcibly interrupting the partial writing in accordance with a state of an external refresh control signal, starting refresh, and restarting the partial writing in accordance with a partial write state and a change in state of the refresh control signal.
An apparatus according to claim 1, wherein the partial write information detected in units of lines by said memory units are identified as continuous line address groups in the scan line direction from the accessed address data, the number of addresses, a start line address or an end line address, or the number of lines is calculated for each group, and a total number of accessed lines is calculated.
An apparatus according to claim 1, wherein only access to said VRAM performed during writing is rendered valid.
An apparatus according to claim 1, wherein a detection period (sampling period) of said memory units for executing detection and storage in units of lines in the scan direction is shorter than a storage period thereof.
An apparatus according to claim 1, wherein when the size relationship between the partial write areas obtained from the partial write information is to be determined, a detection period (sampling period) of a memory unit having partial write information of a larger area is shorter than a storage period thereof.
An apparatus according to claim 1, wherein a cycle of determining the size relationship between the partial write areas obtained from the partial write information is synchronized with a cycle of said partial write detector for repeating detection and storage such that the cycles are integer multiples with respect to said different memory units, respectively.
A display system comprising:
an image information control apparatus having
a partial write detector having at least two types of memory units for detecting and storing addresses accessed to a VRAM in units of lines in a scanning direction, thereby repeating the detection and the storage at different cycles,
a circuit for performing calculations to recognize partial write information from contents of each of said memory units,
memory units for storing the respective calculation results,
a circuit for comparing the memory contents to determine a size relationship between partial write areas,
a partial write ID signal controller for controlling a partial write ID signal on the basis of the size relationship between partial write areas and externally outputting the signal, and
a circuit for, even when partial writing is being executed, forcibly interrupting the partial writing in accordance with a state of an external refresh control signal, starting refresh, and restarting the partial writing in accordance with a partial write state and a change in state of the refresh control signal; and
a display panel.
A system according to claim 7, wherein the partial write information detected in units of lines by said memory units are identified as continuous line address groups in the scan line direction from the accessed address data, the number of addresses, a start line address or an end line address, or the number of lines is calculated for each group, and a total number of accessed lines is calculated.
A system according to claim 7, wherein only access to said VRAM performed during writing is rendered valid.
A system according to claim 7, wherein a detection period (sampling period) of said memory units for executing detection and storage in units of lines in the scan direction is shorter than a storage period thereof.
A system according to claim 7, wherein when the size relationship between the partial write areas obtained from the partial write information is to be determined, a detection period (sampling period) of a memory unit having partial write information of a larger area is shorter than a storage period thereof.
A system according to claim 7, wherein a cycle of determining the size relationship between the partial write areas obtained from the partial write information is synchronized with a cycle of said partial write detector for repeating detection and storage such that the cycles are integer multiples with respect to said different memory units, respectively.