JPH0458221A - Image information controller and display system - Google Patents

Abstract

PURPOSE:To improve interechangeability for a CRT display system by simultaneously displaying partial scrolling display and mouse moving display. CONSTITUTION:This system is provided with at least two kinds of memory parts which detect and store an address accessing a VRAM in line units with respect to a scanning direction. By repeating the detection and the storage in respective different cycles, partial write information is calculated so as to be recognized from the contents of the respective memories. The contents of the memory which stores the calculated results are compared to discriminate the size of a partial write area. Based on the size of the partial write area, a partial write discriminating signal is controlled and outputted to the outside. Then, the partial write is forcibly interrupted according to the state of a refresh control signal from the outside and the partial write is restarted according to the change of the state of the refresh control signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to an image information control device in a display system, particularly in a display system using a ferroelectric liquid crystal having memory properties.

[Conventional technology]

Recently, the liquid crystal display systems required for personal computers (PCs) and '7-stations (WS) have become larger and have higher resolutions year by year.
Compatibility with S is also required.

Ferroelectric liquid crystal (FLCD) with special memory properties
When adopting a display panel using a PC or WS in a PC or WS, it is essential that the mouse or cursor, for example, be displayed by moving smoothly, but such a moving display is disclosed in US Pat. This is realized by a partial writing method (scanning only the scanning lines corresponding to the area to be partially rewritten) as disclosed in . In PS and WS, when a partial scroll screen (this screen also scans only the scan line corresponding to the scroll screen) is displayed, when the mouse is moved and the display is attempted, especially if the mouse is displayed next to the scroll screen. When doing so, the entire scroll screen might not be displayed.

[Summary of the invention]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a liquid crystal display system, particularly a ferroelectric liquid crystal display system, which overcomes the aforementioned problems and has improved compatibility with CRT display systems.

Another object of the present invention is to provide an image information control system with improved compatibility with CRT display systems.

The present invention firstly uses VRAM (memory for storing image information).
At least two types of memory sections are provided for detecting and storing accessed addresses line by line in the scanning direction, and a partial write detection circuit that repeats the above detection and storage at different cycles, and a partial write detection circuit that recognizes partial write information from the contents of each memory. a circuit that calculates the size of the partial write area; a memory unit that stores each of the above calculation results; a circuit that compares the memory contents of each of the above to determine the size relationship of the partial write areas; A partial write identification signal control circuit that controls the partial write identification signal and outputs it to the outside, and a partial write identification signal control circuit that forcibly interrupts partial writing and starts refreshing even during partial writing depending on the state of the external refresh control signal. , and a circuit that controls the partial write state and a circuit that controls the partial write to restart again according to a change in the state of the refresh control signal, and a display system using the same: Second, the line unit detected in the memory section The partial write information is identified from the accessed address data as a group of line addresses in the continuous scanning line direction, and for each group, the number, start line address, end line address,
or an image information control device that calculates the number of lines and further calculates the total number of accessed lines, and a display system using the same: Thirdly, an image information control device that makes access to VRAM valid only during writing, and this Display system using: Fourthly, an image information control device and display system in which the detection period (sampling period) of the memory unit that detects and stores line by line in the scanning direction is shorter than the storage period: Fifthly, from partial write information Image information control device and display system in which the detection period (sampling period) of a memory section having partial write information of a large area is shorter than the storage period when simultaneously determining the size relationship of the obtained partial write areas: Sixth, the partial write area The cycle for determining the size relationship of the partial write area obtained from the write information is linked to the cycle of the partial write detection circuit that repeats the previous detection and storage, and is set to be an integer multiple of each other for each different memory section. An image information control device and display system:

[Detailed description of aspects of the invention]

The device and system of the present invention provide memory-enabled F
It is suitable for a display using an LCD (ferroelectric liquid crystal), and in particular can use a partial writing method that realizes moving display of a mouse or cursor, as well as a full refresh scanning drive method.

The partial writing method used in the present invention is basically performed as follows.

- If a drawing request requires partial writing, full refresh is canceled and the partial writing area on the screen is scanned in a non-interlaced manner.

■After partial writing is completed, refresh is resumed.

In reality, it's not this simple. The following recognition is required: [1] - Recognizing which drawing request should be the highest priority partial write.

Take FIG. 20 as an example. There are four events. Three separate windows and moving mouse font. Window ■
, a clock display, window ■ a rotating line display,
In the window ■, characters are displayed in a vertical scrolling manner.

The display speed within each window is different, and they are displayed asynchronously with each other (independent events). Since the access time for one line of FLCD does not change if the temperature is constant,
The time (scanning time) required when displaying each window by partial writing is proportional to the size of the partial writing area. Now, when a partial window write is executed while another window partial write occurs, it is necessary to decide which partial write should be executed with priority.

For this reason, it is necessary to determine the priority order in advance when an event occurs for partial writing, to recognize this priority every time a partial write request occurs, and to deal with it according to a determined procedure. For example, priorities are determined such that partial writing during scroll display is interrupted, writing is performed on the clock display portion, and then the interrupted partial writing is resumed, and procedures between each partial writing are determined.

[2] Having a graphics scheduler for partial writing.

In multitasking systems such as UNIX/X-Window, the concept of priorities alone is not sufficient. In such a system, several requests simultaneously invoke partial writes and are stored in respective host queues (Figure 19). These requests are then transferred from each host queue to the server's queue.
Transferred over the network or internally to a buffer. However, here, the requests buffered in the server are already set while maintaining the drawing order to the VRAM.

Therefore, priorities do not work well because they follow that order. For example, "mouse" has the highest priority, but there are many requests to draw images to VRAM before the mouse request (in some cases, the mouse request must wait until the previous requests have finished). After all, mouse requests cannot have the highest priority under such a multitasking system (Figure 20).

To solve this problem, a graphics scheduler is introduced. This scheduler ultimately functions to give requests from the host side queue appropriate priority for partial writes (FIG. 21).

The basic concept of the FLCD H/W interface of the present invention is: - Calculate the start, end and line number of a continuous group of accessed lines to VRAM, and store data in "5 tack"; Several groups are detected simultaneously in each period (different from the S/W case), ■ In "5 tack", the margin for a certain time can include the aforementioned several groups, ■ Several 5 tack has priority. ■The last partial write access has the highest priority.

FIG. 1 is a block diagram of the device of the present invention, showing registers for catching access information to VRAM, transferring this information to external circuits, counting the number of partial writes, and performing other functions. Indicates that the data will be sent to memory.

Random input and serial output are used.

FIG. 2 shows a multi-fist stack for obtaining priorities in the present invention. The stack l stores partial write areas every Δ. Conversely, stack 2 essentially stores every 2Δ to obtain priority.

Here, it is not decided how deep the stack should be.

FIG. 3 shows a timing chart of switching between partial write and refresh in the present invention.

B represents a certain value and is the number of switching. When A exceeds B, any partial writing must be interrupted to maintain the screen image by refreshing.

However, it is difficult to set a fixed B in current FLCDs.

FIG. 4 shows two signals, PAR and REF, for switching between partial write and refresh in the present invention. In FIG. 3, the new GSP is attempting to control switching between partial writing and refresh.

However, GSP (G made by Texas Instruments)
SP: Registered product) is “B” for FLCD.
The value cannot be recognized and the end of refresh during successive partial write requests cannot be determined.

Therefore, this H/W for partial writing sends a signal, PAR, to the new FLCD controller, and the FLCD controller independently sends a signal, REF, to the previous H/W for refreshing.

FIG. 5 shows some of the hardware of the present invention. This is not correct, but it provides an idea. It is desirable to use double buffers for the sampling register and memory register.

They are used alternately.

The register is made up of many F, F, (Flip-Flop)- or static memories.

For F, F, the read register is reset serially (Figure 5).

However, in the case of static memory (Figure 6), in order to read data serially, it must be done with separate hardware, and in addition, at reset, another hardware overrides the MO'' data for all addresses. Must.

FIG. 6 shows the case of static memory in the present invention.

Assumption: The accessed line address is allocated to a static memory address.

Sampling: Set data l" to the memory address allocated to the accessed line address.

Transfer: When the gate is turned "OFF", control is transferred to the automatic address generation circuit to automatically allocate an address. Data in the memory is read out while being serially assigned addresses from the previous generation circuit.

Reset: At reset, the automatic data generation circuit allocates addresses and overrides all addresses in memory with “0” data.

Ca5el in FIG. 7 shows an example of a multi-register for partial writing. In this case, only one request is occurring and it is also the fastest.

Ca5e2 in FIG. 8 shows another example at medium speed.

CaSe3 in FIG. 9 shows an example of a mixture of high speed and medium speed.

Ca5e4 in FIG. 1O shows an example at multiple speeds. There are two windows, each scrolling at a different speed. This case is a severe condition for partial writing.

Ca5e5 in FIG. 11 is an example of Ca5e4, but the size and position on the screen are different. In this case as well, there are severe conditions for partial writing.

Ca5e6 in FIG. 12 is an example similar to Ca5e3, but the scrolling speed of Ca5e3 is different. In this case as well, there are severe conditions for partial writing.

Ca5e7 in FIG. 13 is another example of Ca5e3. An improved method for obtaining priorities is used here.

Ca5e8 in FIG. 14 is another example of Ca5e4. There are two windows that are scrolling at different speeds. An improved method of obtaining priorities for partial writes is also used in this case.

Ca5e9 in FIG. 15 is another example of Ca5e5. Here again, an improved method is used to obtain priorities. This case is no longer strict compared to the previous partial writing.

Ca5e l O in Figure 16 is another example of Ca5e6. In this case, partial writing is no longer more difficult than before. Only in this case, the 17th
The timing chart shown in the figure is used.

FIG. 17 shows the actual partial write and refresh sequence and switching in FIG. 16 according to the present invention.

It describes when the stack is sampled and when a request is generated.

In FIG. 17, the actual sampling timings of stack 1 and stack 2 are shifted as shown.

Access requests associated with movement of circles such as a-b, c-d, e-f, g-h, etc. are detected within the sampling time of stack 1, and scroll requests are detected within the sampling time of stack 2. Here, larger partial writes are given priority over shorter ones, so the final result as partial write information is as shown in the figure.

Therefore, actual partial writing and refreshing are controlled as follows.

■ Interrupt refresh before partial writing, ■ a-b
, c-d, the moving display portion of the circle is written.

■The end point of writing parts a-b and c-d is before the next partial writing consideration time, stack 1 is in an undefined data state, and stack 2 is being sampled.
Execute refresh.

(2) Compare each stack data at the time when the partial write data is determined, and execute partial write of the sampling data of stack 2, ah, and scroll request.

FIG. 18 is an example for explaining the actual sampling H/W in the FLCD interface in FIG. 17.

There is a scrolling image and a moving circle on the screen.

Assumption: VRAM access time per bit is 100nsec
It is.

The VRAM is composed of 1MX8bits. The size of the circle is 100 X l 00 bits, the scroll size is IK is being carried out.

Access to VRAMAccess to VRAM actually includes READ access and WRITE access. Strictly speaking from the perspective of partial write control, what is actually required is WRITE access.

FIG. 22 is an example of converting a certain window into another window. In this case, the copy source window is VRAM1. m is accessed with READ CYCLE, and the copy destination window is WRITE CYC.
Accessed in LE. Actually, partial writing is started only at the copy destination, and there is no need to perform partial writing at the copy source as well.

Always use WRITE CYCLE to partially write to VRAM
This is done after the access by READ CYCLE, and is not necessary for READ CYCLE.

If both READ/WRITE cycles/lz+7) were used to detect access to VRAM, twice as much time would be wasted on partial writes.

[2] Scheduler As already mentioned, FLCD requires a scheduler under multitasking. In the case of a hardware interface, a larger partial write has priority, or partial write data that is latched at the start of partial write has priority. No other partial writing will be accepted until the partial writing is completed. Therefore, the order of partial write requests that actually occur is made uniform during the sampling period, and then partial writes are performed all at once, so the priority that was originally given to each event is physically This is converted into a size relationship of partial write areas, and simultaneous mixed partial writes are folded into a certain period. Therefore, at this point, scheduling of the order of partial write requests is implicit.

As mentioned above, FLCD partial writing mainly requires 2
two items are required and must have the same functionality at the hardware interface.

[1] concerns the priority order, and [2] concerns the scheduler. (Although the scheduler [2] mentioned above is not explicitly configured, it is included in the hardware [1]. The functions are also different.) Figures 1, 2, 3, and 5. As seen in the basic concept, priority assignment is obtained in H/W by using the following procedure: ■ Providing at least two special registers.

(2) For the scanning direction, the y-lines accessed to the VRAM are detected in the register during each sampling period (using the bubble buffer technique as in FIG. 5). For example, here the maximum sampling is 25 m
sec, every.

■The obtained data is serially transferred to an external circuit.

...For example, the transfer lock is set to 10 MHz (
Figure 2).

(2) The external circuit calculates whether the accessed y-line is only one line or a block with start-end addresses, as well as the number of accessed lines/blocks and the total number of accessed lines. ...That is, converting serial data into parallel data and obtaining consecutive blocks accessed in a register to an external memory called "5 tack".

■The data detected as these partial writes are collected according to different sampling periods -- for example, one every 25m5ec and the other every 50m5ec.
5tack".Furthermore, 5tack with two or more sampling periods is possible (Figures 3 and 4).
.

■If it is necessary to keep the image on the screen while partial writing continues for a long time or permanently, it is necessary to monitor the total number of accesses. However, it is difficult to set a fixed value B for two reasons.

B means the limit number for the total number. Perhaps B is less than the total number of scan lines. The reason is that when B exceeds the total number, the access time for this partial write exceeds the frame period. In other words, non-interlacing due to partial writing occurs beyond the frame period. For this reason, it is easy to flicker.

Additionally, due to the temperature dependence of the FLCD, the frame period changes and thus B changes with temperature. Therefore, a fixed B value cannot be set.

Another reason is that it is important to know when to stop refreshing while partial writing continues. This is also variable due to the temperature dependence of the FLCD. In order to solve these problems, FLCD H/W
The interface applies two control signals described below.

Now, I have two ideas for assigning priorities.

Cases 1 to 6 show several examples using one invention in which the fastest partial writing has first priority.

The pixel size of the FLCD used in the explanation is 1024 x vertical.
The frame frequency (refresh rate) at the horizontal temperature is 1280 Hz and the normal operating temperature is 20 Hz.

The previous registers are designed to differentiate priorities. However, attention must be paid to cases 3 to 6 in order to properly allocate priorities.

They demonstrate the need for very strict constraints.

Register l detects the fastest movement, e.g. 25m
s e c , every (=40Hz equivalent).

Register 2 detects a second movement, e.g. 50ms
e c , every (=20Hz equivalent).

If there is, register 3 will detect a third movement, e.g. 100 m.
s e c, every (=10Hz equivalent). register 4 is 20
0 msec.

It should be more than that, but the FLCD refresh is 2
Since it is below 0 Hz (50 msec, above), it is meaningless. Also, register 3 is not necessary for the same reason.

Thereafter, the data are each moved "5 tack" from each other as seen in FIG. case 1 and case
In 2, each movement is detected and displayed as ``Uma'' (for only one movement).

However, care must be taken when there are mixed movements as seen in cases 3 to 6.

As can be seen in the explanation of the figure, if the highest speed register for partial writes has the first priority, it will be noticed that there are very strict constraints in order to complete multiple partial writes. That is, the frame frequency of FLCD is the highest sampling frequency, currently 25 msec, (40
(equivalent to Hz), it must be faster. That is not possible with FLCD here.

We must have the opposite assumption for priority assignment (case 7 to caselo). That is: The priority is "5tack2>5tackl'. In other words, 5tackl does not affect partial writing until the longest partial writing to the FLCD panel is completed. It is explained in more detail below: (ca
Since sel and case 2 are single requests, they are not affected by the new assumption. ) The new partial write priority allocation is based on the assumption that c
In ase7, the fastest moving object is displayed occasionally or thinned out, and is not displayed continuously. cas
In e8 (similar to ase7, the 5 tackle movement is thinned out.

Case 9 has the same result as case 8.

Caselo is the same as Ca5e7.

No matter what the FLCD speed is, all cases (case 7 to caselo) are working fine.

This is because other partial writes are thinned out until the longest partial write is completed. Therefore, the previous problem cannot occur.

The final consideration regarding priority assignment is how to actually implement it. Up until now, it has been assumed that partial write data is instantaneously detected in a register and stored during the sampling period. However, in reality, a certain period of time must be spent on sampling. Furthermore, the FLCD interface must have a scheduler for concurrent requests, especially under multitasking. Therefore,
The H/W FLCD 1 interface operates as shown in FIG. 17, for example.

In Figure 17, the actual sampling time for stack l is 12.5 msec, and for stack 2 is 25 msec.
So, stack 1 is double. During these periods, it can be regarded as if the gate to the detection circuit (register) was "ON". Each register detects and stores the accessed line address. The sampling interval of stack 1 is every 25 msec, and the sampling interval of stack 2 is 50 msec.
Every c.

The parameters in Figure 17 and the previous casel are the same as in Figure 18.
.

use.

There are two images on the screen. One is the image of a circle moving at high speed. The other is a scrolling window. The circle is 25 msec, every (4
0Hz equivalent), and the scroll speed is 1.
Every 00 m s e (= equivalent to 10 Hz).

On the other hand, the access time per 1 bit of VRAM is 1
00 nsec/bit (this speed is faster than others). In this case, 8 bits can be accessed at a time.

In a scrolling window, the full screen access time for - times is 100nsecX (IKXIK) bits/8bits
s=12.5m5ec, (100msec.

Therefore, one screen access of window is stack 2
All can be detected within a sampling time of 25 msec. Also, the sampling interval is 50 m s
Since the scrolling speed is 100 m5ec in contrast to ec, partial writing of the l scroll screen can be started after detection.

On the other hand, for the circle, two accesses (erasing and writing) are performed as one unit for moving display, so 100nsecX (100X100) bits/8
bits=0.125m5ec, =4acces
s0.125m5ec, X2==0.25m5ec.

< 25 m sec -1 n o v i n
g, so the sampling time of stack 1 is 12.
5m5ec.

All movement display accesses can be detected within 1 hour, and the sampling interval is 25 msec, from 2-5m5e.
The circle with the moving speed of c can start partial writing of the moving display at least once.

Consider the case where scroll and circle are mixed at the same time. case
Equivalent to lO.

In the explanation of FIG. 17, when partial writing of stack 2 for larger partial writing starts, the window is scrolling and contains image information of a circle on the screen. The partial writing display of the circle that moves between scrolls is based on the information from the stack l.

If the end of the partial write is before the time to compare the stacks, and in both cases the sampling data is undefined or is being sampled, refresh is performed until the next comparison time. (Corresponding to ■) When the time for the next partial write comes, refresh is interrupted and partial write starts.

Of course, if there is no partial write data at that time, refresh is performed and continues until the next partial write is found.

〔Effect of the invention〕

According to the present invention, compatibility with a CRT display system is improved by simultaneously displaying a partial scroll display and a mouse movement display.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the apparatus of the present invention. FIG. 2 is an explanatory diagram of multitasking used in the present invention. FIG. 3 is a chart diagram of a timing chart used in the present invention. FIG. 4 is a timing chart for realizing forced refresh (LL) used in the present invention. FIG. 5 is a block diagram of hardware used in the present invention. FIG. 6 is a block diagram of static memory. FIG. 7 is an explanatory diagram of case 1. FIG. 8 is an explanatory diagram of case 2. FIG. 9 is an explanatory diagram of case 3. FIG. 10 is an explanatory diagram of case 4. FIG. 11 is an explanatory diagram of case 5. FIG. 12 is an explanatory diagram of case 6. FIG. 13 is an explanatory diagram of case 7. FIG. 14 is an explanatory diagram of case 8. FIG. 15 is an explanatory diagram of case 9. FIG. 16 is an explanatory diagram of case IO. FIG. 17 is a timing chart of the present invention (invention of claim 4). FIG. 18 is an explanatory diagram of the sampling H/W used in the present invention. Figure 19 shows the X-win do used in the present invention.
It is an explanatory diagram of the scheduler in w. FIGS. 20 and 21 are explanatory diagrams schematically showing graphic command execution. FIG. 22 is an explanatory diagram of the VRAM accelerator.廼：＊plt”771 p(IY't('QL (Access <-) )
Ae reshVRAM ACCESS Ding'IME

Claims (12)

[Claims] (1) At least two types of memory sections are provided to detect and store the addresses accessed to the VRAM line by line in the scanning direction, and a partial write detection circuit that repeats the above detection and storage at a different cycle; a circuit that performs calculations to recognize written information; a memory unit that stores each of the above-mentioned calculation results; a circuit that compares the contents of each of the above-mentioned memories and determines the size relationship between the partial write areas; and the size of the partial write areas. A partial write identification signal control circuit that controls a partial write identification signal based on the relationship and outputs it to the outside; and a partial write identification signal control circuit that forcibly interrupts partial writing depending on the state of an external refresh control signal even during partial writing; An image information control device comprising: a circuit that starts refreshing and controls the partial writing to be restarted again depending on the partial writing state and a change in the state of a refresh control signal. (2) The partial write information in line units detected in the memory section is identified as a group of line addresses in the continuous scanning line direction from the accessed address data, and the number, starting line address, and ending line address are determined for each group. ,
The image information control device according to claim 1, further comprising calculating the number of lines and calculating the total number of accessed lines. (3) The image information control device according to claim (1), wherein among the accesses to the VRAM, only writing is enabled. (4) The image information control device according to claim 1, wherein a detection period (sampling period) of the memory section for detecting and storing line by line in the scanning direction is shorter than a storage period. (5) A claim characterized in that when simultaneously determining the size relationship of partial write areas obtained from partial write information, the detection period (sampling period) of a memory section having partial write information of a large area is shorter than the storage period. Section (1)
image information control device. (6) The cycle for determining the size relationship of the partial write area obtained from the partial write information is linked to the cycle of the partial write detection circuit that repeats the previous detection and storage, and is set to an integer value for each different memory section. The image information control device according to claim 1, characterized in that the relationship is doubled. (7) At least two types of memory sections are provided to detect and store the addresses accessed to the VRAM line by line in the scanning direction, and a detection circuit for partial writing that repeats the above detection and storage at different cycles; a circuit that performs calculations to recognize written information; a memory unit that stores each of the above-mentioned calculation results; a circuit that compares the contents of each of the above-mentioned memories and determines the size relationship between the partial write areas; and the size of the partial write areas. A partial write identification signal control circuit that controls a partial write identification signal based on the relationship and outputs it to the outside; and a partial write identification signal control circuit that forcibly interrupts partial writing depending on the state of an external refresh control signal even during partial writing; A display system comprising an image information control device and a display panel, comprising: a circuit that starts refreshing and restarts partial writing according to a change in the state of a partial writing state and a refresh control signal; (8) The partial write information in line units detected in the memory section is identified as a group of line addresses in the continuous scanning line direction from the accessed address data, and the number, starting line address, and ending line address are determined for each group. ,
The display system according to claim 7, further comprising calculating the number of lines and calculating the total number of accessed lines. (9) The display system according to claim (7), wherein among the accesses to the VRAM, only writing is enabled. (10) The display system according to claim (1), wherein the detection period (sampling period) of the memory unit that detects and stores line by line in the scanning direction is shorter than the storage period. (11) A claim characterized in that when simultaneously determining the size relationship of partial write areas obtained from partial write information, the detection period (sampling period) of a memory section having partial write information of a large area is shorter than the storage period. term (1
) display system. (12) The cycle for determining the size relationship of the partial write area obtained from the partial write information is linked to the cycle of the partial write detection circuit that repeats the previous detection and storage, and is set as an integer for each different memory section. The display system according to claim 1, characterized in that the relationship is doubled.