EP0453476A1 - Convertisseur a/n - Google Patents
Convertisseur a/nInfo
- Publication number
- EP0453476A1 EP0453476A1 EP19900901847 EP90901847A EP0453476A1 EP 0453476 A1 EP0453476 A1 EP 0453476A1 EP 19900901847 EP19900901847 EP 19900901847 EP 90901847 A EP90901847 A EP 90901847A EP 0453476 A1 EP0453476 A1 EP 0453476A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- noise
- converter
- modulators
- modulator
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
- H03M3/412—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution
- H03M3/414—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having multiple quantisers arranged in cascaded loops, each of the second and further loops processing the quantisation error of the loop preceding it, i.e. multiple stage noise shaping [MASH] type
- H03M3/418—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having multiple quantisers arranged in cascaded loops, each of the second and further loops processing the quantisation error of the loop preceding it, i.e. multiple stage noise shaping [MASH] type all these quantisers being single bit quantisers
Definitions
- the present invention relates to an analogue to digital (AD) converter which employs sigma-delta modulators.
- Sigma-delta modulators are used in oversampled AD conversion and operate by integrating the difference between a sampled signal and a previously quantized signal. The result of the integration is compared with a reference voltage to determine whether a digital output line is to be set high or low.
- Noise is introduced into the modulators by the 1 bit quantization process and integrating amplifiers, and it is necessary to employ some form of noise shaping to remove the noise from the band of interest.
- Oversampled analogue to digital converters offer high precision conversion without requiring precision elements or accurate component matching.
- One method of achieving high order noise shaping, or shifting is to employ a relative high oversampling ratio, which is the ratio of sampling clock frequency to input signal bandwidth.
- a relative high oversampling ratio which is the ratio of sampling clock frequency to input signal bandwidth.
- High order noise shaping may also be achieved by using high order integration in the modulators.
- Direct realisation of high order sigma-delta modulators is generally avoided as they are regarded as being unstable, as discussed in a paper entitled "Oversampling A-to-D and D-to-A converters with multistage noise shaping modulators" IEEE Transactions on acoustics,- speech, and signal processing, vol 36, no. 12, December 1988.
- Realisation of high order sigma-delta modulators is normally achieved, as described in that paper, by cascading perfectly matched first order sections.
- the paper further discloses a technique of achieving quantization noise suppression wherein the quantization noise of the first stage is removed by signal subtraction.
- the noise performance of the amplifiers used in the modulators is very important.
- amplifiers generate considerable noise, especially low frequency flicker noise.
- the noise of the amplifier making up the integrator is not shaped by the feedback structure and is added directly to the output signal.
- High power consumption and a large chip area are needed to keep the amplifier noise at a sufficiently low level.
- the quantization noise of cascaded first order sections subtract and cancel each other, except that of the last stage, the noise and offset due to the amplifiers are added together at the output of the converter. They are added together in the rms sense as the noise and offset from different amplifiers are uncorrelated.
- an analogue to a digital converter comprising at least two cascaded second order sigma-delta modulators. This has several advantages compared to using first order sections. The number of comparators utilized is half what cascaded first order sections would require for the same order noise of shaping. The digital hardware immediately following each modulator section, such as delay flip-flops and digital adders, is also approximately only half as complicated as what would be required for cascaded first order sections.
- said modulators are connected such that at a digital output of said converter the noise generated by the first of said modulators is substantially removed and the noise generated by the second of said modulators has undergone high order noise shaping.
- each modulator includes two integrators and a comparator in series, whereby high order noise shaping is performed whilst using a relatively low oversampling ratio.
- Figure 1 is a circuit diagram of a first preferred embodiment of an AD converter according to the present invention
- Figure 2 is a circuit diagram of switch control circuitry of the converter of Figure 1;
- Figure 3 is a schematic circuit diagram of an output stage or a converter according to the above embodiment
- Figure 4 is a schematic block diagram showing one exemplary output processing stage to produce a 16 bit digital output for the above embodiments;
- Figure 5 illustrates schematically the operation of correlated double sampling used in a second preferred embodiment of the invention.
- Figure 6 is a circuit diagram of this second preferred embodiment.
- An AD converter 2 as shown in Figure 1, includes two second order sigma-delta modulators 4 and 6 which are cascaded so as to provide a 4th order modulator.
- the first modulator 4 includes two integrators 8 and 10 and a comparator 12 connected in series.
- the inputs to the integrators 8 and 10 and the comparator 12 are received from switched capacitors which are controlled by complimentary HOS transistors.
- the MOS transistors are, in turn, controlled by a two phase clock, CLE being one phase and CL0 being the other . phase, as shown in Figure
- the analogue signal to be converted, V. is sampled onto an input capacitor 14, having a value G.
- the first integrator 8 has a feedback capacitor 18 of value D and the quantized output is fed to the inverting input of the integrator 8 after being stored on a second feedback capacitor 20 of value C.
- the second feedback capacitor 20 stores a signal representative of the complement of the quantized output, in response to signals CLA and CLB used to control a pair of switching transistors 22 and which are received on enabling lines 24 and 26, respectively.
- the switching transistors 22 selectively couple the second feedback capacitor 20 to a low or high voltage source, + V f .
- the signals CLA and CLB are generated by a switch control circuit 28 which is connected to the two complimentary outputs 30 and 32 of the comparator 12.
- the switch control circuit 28, as shown in Figure 2 includes two storage capacitors 34 and 36 coupled to the outputs 30 and 32 of the comparator 12, respectively.
- An AND gate array 38 is connected to the storage capacitors 34 and 36 and is controlled by the two phase clock to cause the first enabling line 24 (CLA) to receive the signal stored in the second storage capacitor 36 whenever CLE is high.
- the second enabling line 26 (CLB) receives the signal stored on the first storage capacitor 34 when CLE is high.
- the integrated sampled signal outputted to the coupling capacitor 16 is inputted to the second integrated 10, together with a signal representative of the quantized output received from a third feedback capacitor 40, having a value F.
- Another pair of switch transistors 42 controlled by the enabling lines 24 and 26 are used to place the quantized output signal on the feedback capacitor 40.
- the difference between the sampled signal and the quantized output is further integrated by the second integrator 10 and the result is submitted to the comparator 12 and compared with a predetermined threshold level.
- the quantized output D Q which appears on output line 32 is high or low depending on the relationship between the output of the second integrator 10 and the predetermined threshold level.
- a further feedback capacitor 19, of value B connects the output of the second integrator 10 to its inverting input.
- the second sigma-delta modulator 6 is same as the first - b -
- the input signals are different as the second sigma-delta modulator 6 receives the output of the second integrator 10 of the first modulator 4, V , on line 50 and a signal representative of the quantized output D , of the first modulator 4 on line 52, which is connected to the third feedback capacitor 40 of the first modulator 4.
- the input signals are combined at the inverting input of the first integrator 8 of the second modulator stage 6 so as to remove any component of the input signal V. .
- the second modulator 6 is used primarily as a means which enables suppression and shaping of any noise generated in the modulators 4 and 6.
- each modulator 4 and 6 The transfer function of each modulator 4 and 6 is low pass to the signal input thereto.
- the integrators 8 and 10 of the modulators 4 and 6 appear in the feedback branch and the transfer function is second order high pass.
- Second order noise shaping is performed by each modulator 4 and 6.
- An expression for D . in the z-domain can be derived by first considering the sum of the currents at the input of the first integrator 8 of the first modulator 4 when CLO is active. This gives equation 1 below.
- the final output D of the AD converter 2 is obtained by delaying once the quantized output D , of the first modulator 4 and subtracting the quantized output of the second modulator 6 therefrom after the second quantized output D Q2 has been subjected to the transfer function - a -
- a circuit for combining the outputs D Q1 and D Q2 according to this transfer function to produce a final output D is schematically illustrated in Figure 3.
- different ways of combining the two outputs D Q , and D Q2 may be employed; derivable using analogous expressions to those given above.
- the combined output bitstream D of the sigma-delta modulator is converted to the desired digital output by a digital output stage incorporating a low pass digital filtering stage 100 and a decimation filter stage 102 (which may be a comb filter).
- Equation 4 From equation 4 it is apparent that the quantization noise of the first modulator 4 is removed and the quantization noise of the second modulator 6 is subjected to 4th order noise shaping.
- the comparators 12 are connected to the second integrators 10 during the settling phase of the integrators 10.
- the output of each comparator 12 is sampled on the relatively large capacitors 34 and 36 and held for the following clock phase.
- the switch control circuit 28 following each comparator 12 only operates during the hold phase. This gives the comparators 12 maximum settling time.
- the accuracy of the gain depends on the matching between the second feedback capacitor 20 and the input capacitors 14.
- the ratio DB/AG should.be as small as possible to reduce the noise term in equation 4.
- the capacitance ratios G/D, C/D and A/B are determined by the maximum amplifier signal swing requirements.
- DB/AG is arranged to be a power of 2 so that digital multiplication by DB/AG can be easily performed by simple data shifts.
- Higher order AD converters can be constructed by cascading more second order modulators.
- double sampling is a circuit technique which reduces low frequency noise or interference.
- the noise voltage V is sampled twice, once together with the input signal V. as discussed above and once without V. (on the idle clock phase), and the second sample is subtracted from the first sample.
- the output voltage V QUt contains the sampled version of V and digitally differentiated noise:
- Figure 6 shows how the circuit of Figure 1 is simply modified to incorporate double-sampling; the switching transistor pair following the input capacitor 14 are repositioned in the feedback network of integrator 8.
- the quantization noise spectrum of a first order modulator has strong peaks in the baseband for inactive input signals. These peaks also exist in second order modulators but are considerably reduced.
- the input to each, except the first modulator is the quantization noise of the preceding stage (which is not inactive).
- the output noise spectrum of these sections therefore do not contain significant peaks.
- the first modulator's quantization noise is cancelled by the second section, so the weak peaks of the first modulator's noise spectrum do not appear in the output. No dither is needed and the design is less complex.
- the feedback of + V f in a sigma-delta modulator should be done through the same feedback capacitors 20 and 40.
- the feedback of + V is done via different capacitors with the same nominal value.
- mismatch between the two capacitances will be around 0.1°/o to 0.5°/o. This means the converters low frequency gain for positive input will differ from the low frequency gain for negative input also by 0.1°/o to 0.5°/o giving rise to a transfer function which is non-linear and degrades the total harmonic distortion of the AD converter.
- the sigma-delta AD converter should have 16 bit resolution and a signal baseband of 64kHz. This resolution requirement translates into a signal to noise plus total harmonic distortion ratio of 96dB.
- the rms quantization noise, N, of an ideal Nth order noise shaping sigma-delta AD converter is given by equation 5 below.
- v ref re P resents half tne quantization step and f c and f are the signal baseband and clock frequency, respectively. If the maximum peak to peak rms signal amplitude is limited to V f , the maximum signal to noise ratio is given by equation 6.
- the maximum amplifier output swing is close to + 2V. This is adequate for a standard 2 ⁇ m CMOS process, whose power supply is +2.5V. A 12dB loss of signal to noise ratio can be compensated by using a higher oversampling ratio. Choosing a 5HHz clock frequency ensures a 102 dB signal to noise ratio for the 64kHz baseband, giving a 6dB margin. o Further increasing the clock frequency is difficult as the amplifier settling requirements become excessive.
- the capacitances ratios G/D, C/D and A/B are determined by the amplifier output swing requirements as 0.707. In one preferred embodiment, capacitances G, C and A are chosen 5 to be 2pF, capacitances D and B to be 2.828pF and capacitance F is chosen to be ⁇ A to produce a Butterworth denominator.
- the four operational transconductance amplifiers (OTAs) in the converter are modeled as voltage controlled o current sources in parallel with a large resistor and load capacitor.
- the load capacitor is chosen to be 0.5pF to balance the actual capacitive load of each amplifier during different clock phases. For such a capacitive load, it is found that the
- A/D convertors according to the invention may be fabricated as a complete package including the modulator 30 and also the output circuitry.
- the higher-order modulator which produces digital output and is thus, broadly speaking, also an AD convertor
- the higher-order modulator may be fabricated as a discrete package, either producing separate modulator section outputs D . or including combining circuitry similar to that of Figure 3 to produce a single output D. This offers greater flexibility to the chip designer in designing his digital applications.
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
Dans la présente invention, des sections sigma-delta de deuxième ordre sont disposées en cascade pour former des convertisseurs A/N d'ordre élevé, appropriés pour la réalisation de dispositifs de type MOS compatible. Par rapport à la cascade d'approche des sections sigma-delta de premier ordre, cette nouvelle structure nécessite moins de comparateurs et moins de circuits numériques complexes. Cette structure est également moins sensible au bruit d'amplificateurs de basses fréquences, lequel est important au niveau de résolution 16 bits. La présente invention décrit également une extrémité frontale de convertisseur A/N sigma-delta de mise en forme du bruit à intégration, de quatrième ordre, qui est capable d'assurer une résolution 16 bits et de convertir des signaux de bande de base jusqu'à 64 kHz.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB8900840 | 1989-01-16 | ||
GB8900840A GB8900840D0 (en) | 1989-01-16 | 1989-01-16 | A/d converter |
Publications (1)
Publication Number | Publication Date |
---|---|
EP0453476A1 true EP0453476A1 (fr) | 1991-10-30 |
Family
ID=10650065
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP19900901847 Withdrawn EP0453476A1 (fr) | 1989-01-16 | 1990-01-15 | Convertisseur a/n |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP0453476A1 (fr) |
CA (1) | CA2045568A1 (fr) |
GB (1) | GB8900840D0 (fr) |
WO (1) | WO1990008430A1 (fr) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5461381A (en) * | 1993-12-13 | 1995-10-24 | Motorola, Inc. | Sigma-delta analog-to-digital converter (ADC) with feedback compensation and method therefor |
US5563727A (en) * | 1994-06-30 | 1996-10-08 | Honeywell Inc. | High aperture AMLCD with nonparallel alignment of addressing lines to the pixel edges or with distributed analog processing at the pixel level |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01204528A (ja) * | 1988-02-10 | 1989-08-17 | Fujitsu Ltd | A/d変換器 |
-
1989
- 1989-01-16 GB GB8900840A patent/GB8900840D0/en active Pending
-
1990
- 1990-01-15 CA CA 2045568 patent/CA2045568A1/fr not_active Abandoned
- 1990-01-15 WO PCT/GB1990/000054 patent/WO1990008430A1/fr not_active Application Discontinuation
- 1990-01-15 EP EP19900901847 patent/EP0453476A1/fr not_active Withdrawn
Non-Patent Citations (1)
Title |
---|
See references of WO9008430A1 * |
Also Published As
Publication number | Publication date |
---|---|
WO1990008430A1 (fr) | 1990-07-26 |
GB8900840D0 (en) | 1989-03-08 |
CA2045568A1 (fr) | 1990-07-17 |
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Legal Events
Date | Code | Title | Description |
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PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
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17P | Request for examination filed |
Effective date: 19910711 |
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AK | Designated contracting states |
Kind code of ref document: A1 Designated state(s): AT BE CH DE DK ES FR GB IT LI LU NL SE |
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17Q | First examination report despatched |
Effective date: 19930812 |
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STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN |
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18D | Application deemed to be withdrawn |
Effective date: 19931223 |