EP0430405A2 - Commutateur numérique pour acheminer des signaux - Google Patents

Commutateur numérique pour acheminer des signaux Download PDF

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Publication number
EP0430405A2
EP0430405A2 EP90310062A EP90310062A EP0430405A2 EP 0430405 A2 EP0430405 A2 EP 0430405A2 EP 90310062 A EP90310062 A EP 90310062A EP 90310062 A EP90310062 A EP 90310062A EP 0430405 A2 EP0430405 A2 EP 0430405A2
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EP
European Patent Office
Prior art keywords
switcher
outputs
inputs
module
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP90310062A
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German (de)
English (en)
Other versions
EP0430405A3 (en
Inventor
Graham Dudley Roe
Pirthi Singh Dhesi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
PRO-BEL Ltd
Original Assignee
PRO-BEL Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by PRO-BEL Ltd filed Critical PRO-BEL Ltd
Publication of EP0430405A2 publication Critical patent/EP0430405A2/fr
Publication of EP0430405A3 publication Critical patent/EP0430405A3/en
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04H—BROADCAST COMMUNICATION
    • H04H20/00—Arrangements for broadcast or for distribution combined with broadcast
    • H04H20/65—Arrangements characterised by transmission systems for broadcast
    • H04H20/76—Wired systems
    • H04H20/77—Wired systems using carrier waves
    • H04H20/78—CATV [Community Antenna Television] systems

Definitions

  • This invention relates to digital routing switchers for routing signals from a plurality of switcher inputs to a plurality of switcher outputs, and in particular to switchers for high frequency applications.
  • a switcher for digital or analogue signals is constructed as a modular system comprising an array of smaller switching units which may be obtained as standard components.
  • a 16 x 16 switcher may comprise a 4 by 4 array of 4-input, 4-output switching units.
  • the number of modular switching units can simply be increased and/or the size of the modules increased.
  • Such switchers are commonly used in broadcasting applications for analogue video (e.g. PAL or NTSC) or audio signals, the interconnections between modular switching units comprising circuit board tracks or wiring. At frequencies up to 10 MHz the loss of signal quality due to the switcher presenting distributed and inaccurately terminated signal paths is not significant. It is now becoming necessary however to convert analogue video and audio signals to digital serial data at rates as high as 270 Mbit/s or more.
  • a switcher which employs matched signal paths to maintain signal quality is available, and is used for switching analogue signals (e.g. NTSC and PAL).
  • This switcher comprises a conventional array of primary switching units (corresponding to the switching units described above).
  • a respective group of inputs of the switcher is connected in parallel to the inputs of the primary switching units of each row of the array, the array having N rows where N is a plural integer.
  • Each output of the switcher is output from a N-input, 1-output switching unit, the N inputs of which are connected to respective ones of the outputs of each of the primary switching units in a corresponding column of the array.
  • the signal paths between the primary switching units and the N-input, 1-output switching units can then be matched so that the transmission time for a signal through the switcher from any input to any output is equal.
  • the invention provides a digital switcher comprising a plurality of switcher inputs arranged in n groups each comprising plural inputs, a plurality of switcher outputs arranged in m groups each comprising plural outputs, and a plurality of n .
  • each module including a primary switching unit for selectively coupling the module inputs to individual ones of the module outputs, wherein at least each module other than those in the first row further comprises a plurality of individually-controllable two-input selector switches, one for each module output, one input of each switch being coupled to an associated output of the primary switching unit of the same module and the other input of each switch being coupled to an associated output of a module in the preceding row.
  • each input to the switcher is amplified by an amplifier, each amplifier comprising a number of outputs connected in parallel to the inputs of each of the primary switching units of the corresponding row of the array. In this way the source impedances of each input to the switcher can be controlled accurately.
  • the source impedances of the outputs of each secondary switching unit will be equal and the termination impedances of the inputs of each secondary switching unit will be equal so that the impedance of each connection between components within the switcher is known and constant.
  • the switcher is advantageous for switching signals of data rates higher than 10 MHz.
  • the primary switching units and/or the selector switches are regenerative.
  • the invention may be of greatest value in switchers having from 64 to 512 inputs, although it is also advantageous in smaller or larger switchers.
  • the digital switcher of the embodiment of Figure 1 is for routing signals from twelve inputs to twelve outputs in any permutation.
  • the switcher is of modular construction, comprising a three by three array of nine modules each comprising a primary switching unit, or crosspoint, (e.g. A1) and a secondary switching unit (e.g. A2).
  • Each primary switching unit, or crosspoint, (e.g. A1) has four inputs (1-4) and four outputs (1-4). Under the control of a central controller 20 each primary switching unit can connect each of its four outputs to any of its four inputs.
  • Each secondary switching unit (e.g. A2) comprises four two-input, one-output selector switches and so has eight inputs (1-8) and four outputs (1-4); output 1 is connectable to either input 1 or 5, output 2 to input 2 or 6, output 3 to input 3 or 7 and output 4 to input 4 or 8. These connections are controlled by the central controller 20.
  • the secondary switching units regenerate data signals they receive. In each secondary switching unit the inputs are terminated and the selected received signals regenerated and sent out of the appropriate outputs.
  • the primary switching units, or crosspoints will also be regenerative.
  • the modules are notionally arrayed in three rows and three columns. Each row corresponds to four of the twelve switcher inputs, row 1 to inputs 1 to 4, row 2 to inputs 5 to 8 and row 3 to inputs 9 to 12. Each column corresponds similarly to four outputs of the switcher.
  • Each column comprises a series of secondary switching units (for example in column 2 these are B2, E2, H2), the outputs 1-4 of each being connected to four of the inputs (5-8) of the unit in the next row.
  • the outputs 1-4 of E2 in row 2 are therefore, for example, connected to inputs 5-8 of H2.
  • each secondary switching unit regenerates digital signals which it receives.
  • the lines between the secondary switching units can thus all have the same known source and termination impedances independent of conditions within the switching units. If a signal is to be routed through the switcher along a column or part of a column of secondary switching units, it is therefore relayed accurately without loss of signal quality.
  • each of the three rows of modules in the switcher corresponds to four of the 12 inputs of the switcher. Signals from each input are distributed by an amplifier 21, a separate amplifier output being connected to the appropriate input of each primary switching unit, or crosspoint, requiring access to that signal.
  • switcher inputs 5 to 8 correspond to row 2 of the array of switching modules.
  • Each of these inputs therefore enters an amplifier 21 and then separate outputs from each amplifier are sent to the corresponding inputs of the primary switching units D1, E1 and F1. In this way the input impedance of each input into the switcher is tightly controlled.
  • each primary switching unit The outputs of each primary switching unit are connected to four (1-4) of the eight inputs of its associated secondary switching unit.
  • the eight inputs of each secondary switching unit e.g. E2 are therefore connected as follows: four inputs (1-4) to the outputs of its associated primary switching unit (e.g. E1) and four inputs (5-8) to the outputs of the secondary switching unit in the previous row of the same column (e.g. B2).
  • a signal may thus be routed from any input of the switcher to any output of the switcher by routing it through the appropriate primary switching unit, or crosspoint, and then cascading or relaying it along the secondary switching units of the appropriate column.
  • primary switching unit F1 would connect input 1 of its inputs to output 3 of its outputs
  • secondary switching unit F2 would route input 3 of its inputs from the primary switching unit F1 to its output 3.
  • the signal would then be relayed or cascaded along the third column of the switcher from F2 to I2 and thus to output 11 of the switcher.
  • output amplifiers may be included to amplify each output of the switcher.
  • the secondary switching units A2, B2, C2 in the first row of the array of modules in the switcher may be omitted, and the outputs from each of the primary switching units or crosspoints A1, B1, C1 in the first row connected directly to the inputs 5-8 of the respective secondary switching units D2, E2, F2 in the second row of the array.
  • secondary switching units may be preferred to have secondary switching units on the outputs of all primary switching units, as shown in the drawing.
  • the switcher can therefore be used without loss of signal quality for switching pulses at much higher data rates than could be handled by prior art switchers.
  • each associated primary switching unit and secondary switching unit e.g. D1 and D2
  • each associated primary switching unit and secondary switching unit e.g. D1 and D2
  • the links between them could be manufactured as a single component or built on the same circuit board.
  • a number of modules may be accommodated on the same component or circuit board.
  • a switcher may be required to route as many as 200 inputs to a comparable number of outputs and may use primary switching units each having 16 or more inputs and outputs, and secondary switching units each comprising 16 or more, independently controlled, 2 input, 1 output selector switches. Practical implementations of two larger switchers of this type will now be described.
  • a 64 x 64 switcher according to the invention is shown in Figures 2 to 7.
  • the switcher is implemented on circuit boards, or cards, mounted conventionally in frames A,B for rack mounting, as shown in Figures 2 and 3.
  • the card types include an 8-channel input card 50, a 32 x 16 crosspoint card 52 and a 16-channel output card 54.
  • Each input card 50 comprises eight input channels, each channel comprising an input buffer 56 as shown in Figure 3.
  • the input buffer 56 reclocks a digital data stream applied to it from an input cable 58.
  • the cable 58 may be up to 130 metres in length, and forms an unbalanced input to the buffer 56.
  • the buffer comprises a 75 Ohm cable equaliser 60 (for a 0-130m cable) and a data regenerator 62 which regenerates the original digital signal despite degradation of its analogue parameters during transmission along the cable 58.
  • the data regenerator 62 restores the original signal level and reclocks the data using a register timed by a jitter-free clock 64 provided by a phase-locked-loop.
  • the regenerated signal is thus returned to its original sending end specification.
  • the data regeneration function may be implemented by an integrated analogue/ECL ASIC (emitter coupled logic application specific integrated circuit) to provide repeatability with low cost and high performance. In this embodiment, for example, data rates from 140 to 300 MHz may
  • the regenerated signal is then buffered to three parallel output drivers 66, 68, 70.
  • Two output drivers 66, 68 feed up to eight crosspoints in the local frame, the remaining output driver 70 being connected to an expansion port 72 of the local frame.
  • the expansion port 72 can then be connected to feed crosspoints in expansion frames, which may be required for a switcher having more than 128 outputs.
  • a 32 x 16 crosspoint card 52 is shown diagrammatically in Figure 4.
  • Each crosspoint card 52 contains two ASICs each comprising a 16 x 16 crosspoint array, and a secondary switching unit comprising 16 2-input, 1-output selector switches 76.
  • the two 16 x 16 crosspoints are arranged as a balanced 32 x 16 crosspoint array 74 whose outputs are respectively connected to an input of each of the secondary switches 76.
  • the second input of each switch is for connection to an output of another crosspoint card.
  • the 16 outputs from the secondary switches 76 are connected to outputs of the crosspoint card 52.
  • Each output card 54 carries 16 output buffer channels.
  • One channel is shown diagrammatically in Figure 5.
  • Each channel comprises a data regenerator 80 to recondition the signal.
  • the data regenerator 80 comprises an ASIC as on an input card 50, and uses a phase locked loop 82 and a register to re-clock the signal. This removes any jitter produced by crosstalk in the routing system of the switcher and restores the signal to specification for transmission to the next piece of equipment.
  • Two outputs from each channel are provided, each being fed through a line driving amplifier 84.
  • the 64 x 64 switcher is shown in Figures 2A and 2B, and in the block diagram of Figure 6.
  • Two 13-card frames A and B each contain a power supply unit (PSU) 90A, 90B, the PSU 90B being used as a back up unit for the PSU 90A.
  • the first rack A also contains a fan and thermostatic sensor powered via socket 92A to cool the switcher.
  • the total power dissipated by the switcher may be as much as 0.5 kW.
  • Switcher inputs 1 to 32 are fed to the first frame A through BNC connectors on the back of the frame, and are received by four 8-channel input cards 50A mounted in the frame.
  • the input signals are regenerated and balanced by the input cards 50A and are then fed in parallel to four crosspoint cards 52A mounted in frame A.
  • the crosspoint cards 52A correspond to the modules in the first row of the 12 x 12 switcher shown in Figure 1 in that they form the first row of modules of the switcher, and so the secondary switches on each crosspoint cards 52A may always connect the outputs of the balanced crosspoint array on the card to the card outputs.
  • the second frame B contains a further four input cards 50B to receive inputs 33-64 of the switcher via BNC connectors.
  • the input cards 50B feed signals in parallel to crosspoints on four crosspoint cards 52B.
  • the two inputs of each secondary switch on each crosspoint card 52B are connected respectively to an output from the crosspoint on the same card and to a corresponding crosspoint card output from the first frame A.
  • the switcher outputs are derived from the outputs from the crosspoint cards 52B in the second frame B. These crosspoint card outputs are connected to four output cards, 54A, 54B, each carrying 16 output channels to restore the output signals to specification for transmission from the switcher.
  • Two output cards 54 are mounted in each of the two frames, A and B, although all of the switcher outputs are derived from crosspoint cards 52B in the second frame B. This enables standardisation of the backplane in each frame.
  • All of the crosspoints and secondary switches are controlled by an external computer system, from which control signals are received at a control connector on the rear of the first frame A.
  • the signals are fed via a computer card 98A in the first frame A to buffer cards 100A, 100B in each frame. Control signals in each frame are then sent from the buffer cards to the crosspoint cards 52A, 52B.
  • an analogue reference signal may be input to a BNC connector 102A to synchronise the switcher to an external system.
  • the switcher described provides a 64 input 64 output switcher capable of switching signals at up to 300 MHz using a standard set of cards which may be used in principle to implement a switcher of any size.
  • the 64 x 64 switcher described requires 8 input cards, 8 crosspoint cards, 4 output cards, 1 control card and 2 control buffer cards. Two standard frames each capable of holding 13 cards are required. If for example a 40-input, 25-output switcher were required, identical componentry could be used but only 5 input cards (8 inputs per card), 4 crosspoint cards, 2 output cards (16 outputs available per card), 1 control card and 2 control buffer cards would be needed. Two frames would be required, which could use the same backplane circuitry as for the 64 x 64 switcher.
  • a 128 input, 128 output switcher is shown in Figure 7. This switcher is arranged in five frames V, W, X, Y, Z, mounted in a rack.
  • One frame V is used solely to house six power supply units, comprising three main units 120V and three back up units 122V.
  • Each of the other four frames W-Z can hold up to 19 cards.
  • Switcher inputs 1 to 32 are input to four 8-channel input cards 50W in the first frame W of the four card holding frames.
  • inputs 33-64 are input to the second frame X, 65-69 to the third frame Y, and 97-128 to the fourth frame Z.
  • Each frame W-Z also contains eight crosspoint cards 52W-52Z. These are fed by two of the three available outputs from each channel of the input cards 50W-50Z, the third output being reserved as an expansion port output for use if an even larger switcher is required.
  • the input cards 50W-50Z in each frame W-Z are grouped together, with four crosspoint cards 52W-52Z on each side of them. One output of each input card channel then feeds the crosspoint cards on each side.
  • Each crosspoint card 52 has 16 outputs.
  • the eight crosspoint cards of each of the first three frames therefore pass a total of 128 outputs to the secondary switches of the eight crosspoint cards in the next frame.
  • each crosspoint card 52 is positioned in its frame directly beneath the card in the previous frame from which it receives signals.
  • the third and fourth frames Y,Z each contain four output cards 54Y, 54Z. Output signals are sent to these from the eight crosspoint cards 52Z in the last frame Z. As in the 64 x 64 switcher described above, since the output cards 54Y, 54Z are not all located in the last frame Z, the same backplane circuitry may be used in all frames.
  • Each frame also contains computer, interface or buffer cards 124W - 124Z to handle control signals sent to the switcher from an external controller.
  • switcher construction can clearly be extended to any size although if more than 128 outputs were required, more than one 19 card frame would be needed to contain each stage of the 'cascade' of the switcher.
  • the expansion port output on each channel of each input card would then be used to transfer regenerated switcher input signals from one frame to another.

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  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Studio Circuits (AREA)
EP19900310062 1989-12-01 1990-09-13 Digital switcher for routing signals Withdrawn EP0430405A3 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB898927207A GB8927207D0 (en) 1989-12-01 1989-12-01 Digital switcher for routing signals
GB8927207 1989-12-01

Publications (2)

Publication Number Publication Date
EP0430405A2 true EP0430405A2 (fr) 1991-06-05
EP0430405A3 EP0430405A3 (en) 1992-07-01

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EP19900310062 Withdrawn EP0430405A3 (en) 1989-12-01 1990-09-13 Digital switcher for routing signals

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EP (1) EP0430405A3 (fr)
CA (1) CA2030895A1 (fr)
GB (1) GB8927207D0 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5818349A (en) * 1990-11-15 1998-10-06 Nvision, Inc. Switch composed of identical switch modules
EP1199885A2 (fr) * 2000-10-17 2002-04-24 Gennum Corporation Circuit de re-synchronisation améliorée et cellule de routage
CN114362785A (zh) * 2021-12-29 2022-04-15 贸联电子(昆山)有限公司 一种高频讯号切换装置及具有其的测试仪、测试系统

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4495498A (en) * 1981-11-02 1985-01-22 Trw Inc. N by M planar configuration switch for radio frequency applications
GB2181611A (en) * 1984-01-14 1987-04-23 Communications Patents Ltd Switching circuit for cable television distribution network
EP0334475A1 (fr) * 1988-02-19 1989-09-27 The Grass Valley Group, Inc. Commutateur de vidéo avec traitement individuel des signaux de vidéo sélectionnés

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4495498A (en) * 1981-11-02 1985-01-22 Trw Inc. N by M planar configuration switch for radio frequency applications
GB2181611A (en) * 1984-01-14 1987-04-23 Communications Patents Ltd Switching circuit for cable television distribution network
EP0334475A1 (fr) * 1988-02-19 1989-09-27 The Grass Valley Group, Inc. Commutateur de vidéo avec traitement individuel des signaux de vidéo sélectionnés

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5818349A (en) * 1990-11-15 1998-10-06 Nvision, Inc. Switch composed of identical switch modules
EP1199885A2 (fr) * 2000-10-17 2002-04-24 Gennum Corporation Circuit de re-synchronisation améliorée et cellule de routage
EP1199885A3 (fr) * 2000-10-17 2004-02-18 Gennum Corporation Circuit de re-synchronisation améliorée et cellule de routage
US6791977B1 (en) 2000-10-17 2004-09-14 Gennum Corporation Reclocker circuit and router cell
CN114362785A (zh) * 2021-12-29 2022-04-15 贸联电子(昆山)有限公司 一种高频讯号切换装置及具有其的测试仪、测试系统
CN114362785B (zh) * 2021-12-29 2023-11-17 贸联电子(昆山)有限公司 一种高频讯号切换装置及具有其的测试仪、测试系统

Also Published As

Publication number Publication date
GB8927207D0 (en) 1990-01-31
CA2030895A1 (fr) 1991-06-02
EP0430405A3 (en) 1992-07-01

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