EP0422920A2 - Empfindlichkeitsanzeiger für einen Funkempfänger - Google Patents

Empfindlichkeitsanzeiger für einen Funkempfänger Download PDF

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Publication number
EP0422920A2
EP0422920A2 EP90311108A EP90311108A EP0422920A2 EP 0422920 A2 EP0422920 A2 EP 0422920A2 EP 90311108 A EP90311108 A EP 90311108A EP 90311108 A EP90311108 A EP 90311108A EP 0422920 A2 EP0422920 A2 EP 0422920A2
Authority
EP
European Patent Office
Prior art keywords
reception
data
selective call
call receiver
quality
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP90311108A
Other languages
English (en)
French (fr)
Other versions
EP0422920A3 (en
EP0422920B1 (de
Inventor
Robert John Schwendeman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of EP0422920A2 publication Critical patent/EP0422920A2/de
Publication of EP0422920A3 publication Critical patent/EP0422920A3/en
Application granted granted Critical
Publication of EP0422920B1 publication Critical patent/EP0422920B1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G08—SIGNALLING
    • G08B—SIGNALLING OR CALLING SYSTEMS; ORDER TELEGRAPHS; ALARM SYSTEMS
    • G08B3/00—Audible signalling systems; Audible personal calling systems
    • G08B3/10—Audible signalling systems; Audible personal calling systems using electric transmission; using electromagnetic transmission
    • G08B3/1008—Personal calling arrangements or devices, i.e. paging systems
    • G08B3/1016—Personal calling arrangements or devices, i.e. paging systems using wireless transmission
    • G08B3/1025—Paging receivers with audible signalling details
    • G08B3/1066—Paging receivers with audible signalling details with other provisions not elsewhere provided for, e.g. turn-off protection

Definitions

  • This invention relates to an indicator for a radio receiver, such as a pager or other selective call receiver, for indicating quality of reception and/or out of range probability.
  • Some pagers have an out-of-range indicator, which provides to the pager user an indication of the out-of-­range condition when a specific signature signal available within the signaling protocol (such as POCSAG) does not appear for a specified length of time. This indication disappears upon a single occurrence of the signature signal until the time again elapses.
  • An out-of-range indicator of the type described will show a pager to be within range, even when the true probability of message reception may be very low, e.g. only 10 or 20%.
  • a selective call system comprising a transmitter and at least one selective call receiver, the transmitter comprising means for transmitting a predetermined sequence of data, and the receiver comprising means for storing the same predetermined sequence of data, means for receiving the sequence of data transmitted by the transmitter and means for comparing the data received with the data stored and for providing a displayed indication of the comparison, indicative of the quality of reception.
  • the receiver may comprise control means for initiating a test mode of operation which, when initiated, causes the reception of the predetermined data, the comparison of the received and stored data and the displaying of the reception quality indication. At times other than during the control mode, the control means allows the receiver to receive other data, characteristic of normal pager operation.
  • the transmitter preferably comprises means for transmitting the predetermined data preceded by a predetermined identification code and the receiver comprises means for identifying said code and initiating reception of the predetermined data, comparison of the received and stored data and displaying of the reception quality indication on receipt thereof.
  • the receiver comprises first and second counters, the first counter being arranged to count at the rate of receipt of received data and the second counter being arranged to count correct correlations between the received and the stored data.
  • the receiver further comprises means for dividing a count value of the second counter by a count value of the first counter to provide a relative figure of merit or a percentage indication of quality of reception.
  • a reception indicator for a radio receiver which receives messages having recognizable signals extending over a period of time, e.g. over the length of one POCSAG synchronization word.
  • the reception indicator comprises: timing means (e.g. a shift register) for providing a time interval smaller than the said period of time, detecting means for detecting the number of recognizable signals received during said time interval, whereby the detected number represents the quality of reception; and indicating means for displaying the quality of reception.
  • the indicator is provided with second timing means for providing a second time interval greater than a frame period and means for freezing the indicating means for said second period of time after the end of said first period of time. In this manner a continuous indication of quality of reception is displayable from frame to frame.
  • an advantage of the present invention is that it gives a qualitative indication of the actual probability of message reception in the actual environment which can be regularly updated.
  • a paging system comprising a paging terminal 10, a paging transmitter 11 and a pager 12.
  • the pager 12 is a numeric or alphanumeric display pager, with certain additional programs and features as are now explained.
  • the pager comprises receiver circuitry as shown in the inset of Fig. 1, as well as a microprocessor 13 and a display 14.
  • the microprocessor 13 comprises a central processing unit 15, an arithmetic and logic unit 16 and at least two counters 17 and 18.
  • the pager 12 is capable of being placed in a test mode.
  • the manner of entering a test mode is by way of a unique button sequence, such as by depressing the read switch and the reset switch simultaneously while the pager 12 is being turned on.
  • the test mode may alternately be entered by means of a menu displayed on the pager display.
  • the pager of the present invention has an additional test mode, over and above existing test modes, such as described in U.S. Patents Nos. 4,599,615 and 4,649,538, and U.K. Patent Application No. 2 124 001 A.
  • This additional test mode may be referred to as a page sensitivity utility.
  • the paging terminal 10 causes a specific series of data words to be transmitted by the transmitter 11 at predetermined intervals at a desired baud rate, such as 300, 600, or 1200 bits per second which may be representative of the actual paging data bit rate currently in service, or to be placed into service.
  • the predetermined data words are illustrated in Fig. 1 and comprise a unique ID followed by 100 data words.
  • the ID corresponds to a unique address to which the pager 12 is responsive when the pager has been placed in the test mode. This ID and the data words D1-D100 are preprogrammed in the pager 12.
  • the pager 12 When the pager 12 is in the page sensitivity utility mode it receives and identifies this ID in a manner well known in the art, and compares the 100 received data words with the corresponding data words stored in memory. When the transmission is complete and the pager 12 has carried out the comparison, the pager 12 displays the number of data words correctly received. This number provides a "figure of merit" having no units, but which can be interpreted as representing the effective paging probability, or probability of receiving a page, expressed as a percentage. It can be used for comparison against other readings from different locations using the pager 12, or with different pagers, assuming such a comparison can be readily made with the other pagers.
  • the service engineer or operator When a comparison of readings is to be made, the service engineer or operator simply moves to a new location, and when at that location, the pager receives a retransmission of the predetermined sequence of words, and a new reception quality indication is displayed.
  • the tests can also be repeated at different transmitter powers, different antennas etc, and provide the service operator an indication of the actual area of coverage provided being provided by the system under the different measurement conditions.
  • Fig. 2 shows a flow diagram illustrating the operation of the above described embodiment.
  • the operation of the flow diagram calls for two counters 17 and 18, as shown in Fig. 1, embodied in the pager 12.
  • the pager After the test mode has been entered by the user, the pager begins searching for the ID start code.
  • counter 17 is incremented in step 21.
  • counter 17 is incremented each time the program executes loop 22. This loop is executed once for each period of time a data word is expected to be thereafter received, such as every eight bits for an eight bit data word. If one of the data words D1-D100 is correctly detected in step 23, counter 18 is incremented in step 24.
  • the figure of merit is calculated in step 25 and this figure is displayed on the radio display 14 of Fig. 1 in step 26.
  • a pager in accordance with a second embodiment of the present invention comprising receiver circuitry 30 as for Fig. 1.
  • the recovered data bit stream from the receiver circuitry 30 is coupled to a microprocessor 31.
  • the microprocessor 31 performs a number of functions, the relevant ones of which are represented by boxes on the diagram. These elements do not necessarily form identifiable elements of hardware.
  • the recovered data bit stream from the receiver circuitry 30 is first fed to a pattern detector means 32, which detects the synchronization codeword, such as when the POCSAG signaling format is being transmitted, or any other representative bit pattern within the received protocol.
  • the output of pattern detector 34 is set to a logic 1 state, remaining in that state until reset to a logic 0 state by a clock pulse generated by clock 43.
  • a logic 1 pulse is also provided to the input of shift register 34 at the time the clock pulse is generated. Should the synchronization codeword fail to be subsequently detected, the output of pattern detector 34 would then remain in the logic 0 state, and a logic 0 pulse will also be provided to the input of shift register 34. This operation allows a synchronous detection of the synchronization codewords. The detections are then loaded into a software shift register 34 each time the clock pulse is generated.
  • timer A and timer B respectively are provided in the microprocessor 31 together with a display interrupt unit 38 and an display driver 39.
  • the display driver drives a display 40, which includes a visual indicator, which in the preferred embodiment of the present invention is in the form of a bar indicator 41.
  • the display interrupt unit 38 causes the display to momentarily blink each time the expected pattern, such as the synchronization codeword, is successfully detected, thereby providing positive feedback that measurements are being made. Failure of the display to periodically blink for an extended length of time, such as a thirty second time interval, would indicate such circumstances, as the absence of channel activity or an out-of-range condition.
  • FIG. 4 shows two programs which run consecutively.
  • a program which receives the pulses generated at the output of pattern detector 34 for each successful detection of the synchronization codeword (step 100). These pulses are loaded into the shift register 34 as previously described.
  • a logic 1 pulse is loaded into the shift register 34 and timer A 36 is reset in step 102.
  • a logic 0 pulse is passed to the shift register 34, which results in the timer A count being advanced one clock time interval by clock 43.
  • timer A is reset each time a synchronization codeword is detected, and advanced each time a synchronization codeword is not detected in the allotted time interval.
  • the shift register 34 has a length Y
  • the period of timer B is less than the period of timer A and is greater than the time length of the period between the pattern codewords to be measured.
  • timer B is sufficiently long to enable detection of at least ten pattern codewords.
  • timers A and B are advanced in step 110, and a pulse is loaded into the shift register as previously described at step 112. If timer A has expired, the program passes from step 114 to step 116 at which the shift register 34 stages are cleared and a zero indication is displayed on the display 41. From this, and from step 102, it can be seen that timer A only expires if a series of zeros are received into the shift register, indicating no match with the synchronization codeword for a predetermined period of time. If timer A has not expired at step 114, the program passes to decision 117 and, because in the first instance timer B has expired as a result of a previous cycle, the program passes to step 118 and the last stage of the shift register is read.
  • step 124 timer B is reset at step 125 so that on the next execution of decision 117, step 130 will be reached. Until such time as the first detect appears in the last stage of the register, the program waits for the next pulse.
  • the first detection percentage for the desired pattern is calculated in step 126 as 100X/Y for codewords in which the probability of detection of the desired pattern equals the probability of detection of an address (this is approximately true for POCSAG).
  • the result is then displayed on display 41 by a graph number or other suitable means.
  • X or 100X/Y may be used to provide an address for a ROM (read-only memory) which stores a tabulation of the address detection percentage corresponding for the detection percentage derived by the measurement of the desired patterns.
  • the display changes upon each execution of step 126, i.e. after each count.
  • step 126 causes display interrupt unit 38 to blink the display 41 for a short blank period, such as a 1/10 second time interval.
  • logic 1's are clocked into shift register 34.
  • a logic 0 is clocked into the shift register 34.
  • timer B is started, and a computation of the detection percentage is made and displayed. Thereafter, the detection percentage is updated and displayed for each new detection determined by a logic 1 being shifted into the first stage of shift register 34, and counter B is reset. The detection percentage continues to be updated as long as timer B is reset prior to its timing out.
  • Fig. 5 illustrates the operation of the present invention using a shift register having a length of ten bits.
  • Fig. 5 shows a typical data pattern 150 transmitted by a transmitter such as transmitter 11 of Fig. 1.
  • the data pattern comprises a sequence of message batches 151 such as would be transmitted using the POCSAG signaling format. Within each of the message batches the unique pattern codeword, in this instance, the POCSAG synchronization codeword is transmitted at the beginning of each batch. The synchronization codeword is repeated periodically as additional message batches are transmitted on the channel.
  • the data pattern 150 also illustrates the fact that there may be time interval 152 during which no transmissions are being made, or during which time other signaling formats may be transmitted on the channel.
  • the output from the pattern detector 32 is shown as signal 154, each pulse indicating a successful detection of the synchronization codeword.
  • Timer A has a period substantially greater than timer B and acts as a fail safe. If no additional synchronization codewords are received during the period before timer A expires, the display will continue to read the last calculated detection percentage count. When timer A expires, it indicates no additional successful synchronization detections have been made for a substantial period of time and consequently the display is set to zero. In contrast, timer B maintains the last percentage detection reading on the display for long enough for the next synchronization codeword to be received.
  • the data is transmitted in a single signaling format, such as POCSAG.
  • a single signaling format such as POCSAG.
  • Such a condition would exist on a fully loaded system which does not share the channel with other signaling formats.
  • timer A is not required, making the flow diagram somewhat more simplified.
  • Step 200 corresponds to step 100 of Fig. 4, with the received pulses passing directly from the pattern detector to the shift register 34.
  • Step 208 corresponds to step 108.
  • step 212 the shift register is loaded in step 212 and all the ones in the shift register are counted in step 214, whereupon in step 216 the display is blinked and a new value of 100 X/Y is calculated and displayed.
  • step 212 the shift register is stepped regardless of whether a detect is received or not. While the shift register length has been described as ten bits in length, it will be appreciated that the length of the shift register can be changed, to provide greater or lesser resolution to the calculation of the detection percentages. A longer shift register is particularly applicable to the embodiment described in Fig. 6, since the shift register is not regularly reset.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Input Circuits Of Receivers And Coupling Of Receivers And Audio Equipment (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Circuits Of Receivers In General (AREA)
  • Burglar Alarm Systems (AREA)
  • Monitoring And Testing Of Transmission In General (AREA)
EP90311108A 1989-10-10 1990-10-10 Empfindlichkeitsanzeiger für einen Funkempfänger Expired - Lifetime EP0422920B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US41955289A 1989-10-10 1989-10-10
US419552 1989-10-10

Publications (3)

Publication Number Publication Date
EP0422920A2 true EP0422920A2 (de) 1991-04-17
EP0422920A3 EP0422920A3 (en) 1992-04-29
EP0422920B1 EP0422920B1 (de) 1995-08-23

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EP90311108A Expired - Lifetime EP0422920B1 (de) 1989-10-10 1990-10-10 Empfindlichkeitsanzeiger für einen Funkempfänger

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Country Link
EP (1) EP0422920B1 (de)
AT (1) ATE126949T1 (de)
DE (1) DE69021820T2 (de)
HK (1) HK1000481A1 (de)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3973242A (en) * 1975-02-27 1976-08-03 Gte Sylvania Incorporated Digital receiver
US4086537A (en) * 1975-01-24 1978-04-25 Nippon Telegraph & Telephone Public Corporation Time division multiplex communication receiving apparatus
US4649538A (en) * 1984-09-28 1987-03-10 Motorola, Inc. Radio paging device with improved test modes
WO1989004527A1 (en) * 1987-10-30 1989-05-18 Fernandez Emilio A Improved paging device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4086537A (en) * 1975-01-24 1978-04-25 Nippon Telegraph & Telephone Public Corporation Time division multiplex communication receiving apparatus
US3973242A (en) * 1975-02-27 1976-08-03 Gte Sylvania Incorporated Digital receiver
US4649538A (en) * 1984-09-28 1987-03-10 Motorola, Inc. Radio paging device with improved test modes
WO1989004527A1 (en) * 1987-10-30 1989-05-18 Fernandez Emilio A Improved paging device

Also Published As

Publication number Publication date
EP0422920A3 (en) 1992-04-29
ATE126949T1 (de) 1995-09-15
EP0422920B1 (de) 1995-08-23
HK1000481A1 (en) 1998-03-27
DE69021820T2 (de) 1996-04-18
DE69021820D1 (de) 1995-09-28

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