EP0422294A1 - Anzeigesystem - Google Patents

Anzeigesystem Download PDF

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Publication number
EP0422294A1
EP0422294A1 EP89310454A EP89310454A EP0422294A1 EP 0422294 A1 EP0422294 A1 EP 0422294A1 EP 89310454 A EP89310454 A EP 89310454A EP 89310454 A EP89310454 A EP 89310454A EP 0422294 A1 EP0422294 A1 EP 0422294A1
Authority
EP
European Patent Office
Prior art keywords
pixel
bit
display
format
word
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP89310454A
Other languages
English (en)
French (fr)
Inventor
Roger Timothy Wood
Roy Bernard Harrison
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Priority to EP89310454A priority Critical patent/EP0422294A1/de
Priority to CA 2021829 priority patent/CA2021829A1/en
Priority to JP2233441A priority patent/JPH03134699A/ja
Publication of EP0422294A1 publication Critical patent/EP0422294A1/de
Withdrawn legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/22—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of characters or indicia using display control signals derived from coded signals representing the characters or indicia, e.g. with a character-code memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/22—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of characters or indicia using display control signals derived from coded signals representing the characters or indicia, e.g. with a character-code memory
    • G09G5/30—Control of display attribute

Definitions

  • the present invention relates to a display system having an all points addressable (APA) display buffer for the storage of information compatible with a display output screen.
  • a display system can be a computer system itself, or an optional, peripheral adapter, such as a display adapter card, installed in a computer system.
  • a display character is typically selected from a character font of 256 available characters by a coded character byte.
  • the coded character byte can be stored in a coded text buffer or a computer program instruction.
  • the display character is represented by a set of pixels which are arranged in pixel rows to form a pixel matrix.
  • the character code byte selects the pixel matrix from a character font table in which each pixel in the pixel matrix is represented by a binary bit.
  • the binary bit specifies whether the pixel is in the foreground of the display character or in the background on which the display character is superimposed.
  • An attribute byte can be supplied in conjunction with the coded character byte. Four bits of the attribute byte specify a foreground pixel colour and the remaining four bits specify a background pixel colour. Such attributes are added to the display character information by attribute combining logic prior to output on the display output screen.
  • a feature of a display system operating in an APA display mode is that a pixel is represented in the APA display buffer by a binary word. This binary word can be representative of either a foreground colour or a background colour. It therefore follows that a character font table for storing such pixel representations requires a large amount of storage space in comparison with an equivalent character font table for a display system operating in a character display mode.
  • first order and second order character fonts corresponding to “first” and “second” pixel code formats.
  • first and second are used in reference to methods of storing pixels in first and second memory structures.
  • first map pixels physically located to the left on a display output screen are stored in higher order bits of a byte
  • second map such pixels are stored in lower order bits of a byte.
  • certain display systems operating in an APA display mode are responsive to picture manipulation instructions for a second pixel code format. This can cause problems when a first order character font table is supplied. Therefore, in such situations it is desirable to translate a "first order” character font table into a "second order” expanded format.
  • the aim of the present invention is to provide a translation means by which a display system operating in an APA display mode, can make use of a character font table associated with a character display mode which may be stored in either a first order or a second order RAM structure.
  • a display system comprising an all points addressable display buffer, in which a pixel is represented by an n bit, where n is an integer greater than zero, pixel word; and in which a display character is represented by a pixel matrix comprising a plurality of pixels arranged in a plurality of pixel rows, a character font table for storing a plurality of such character pixel matrices representative of display characters of a font, and control logic responsive to a character code word for selecting a desired pixel matrix from the character font table, wherein that each pixel matrix is stored in the character font table in an m bit, where m is an integer greater than zero, (m ⁇ n) per pixel format whereby the pixel is represented by an m bit word; and in that the display system comprises translation means for translating a pixel row arranged in the m bit pixel format to a pixel row arranged in an n bit per pixel format compatible with the APA display buffer.
  • the translation means has attribute combining logic by which the n bit pixel word can be changed in accordance with an n bit attribute word, which can be stored in association with the character code word in the coded text buffer for specifying an attribute of the pixel.
  • a pixel attribute such as a foreground colour associated with one pixel status or a background colour associated with another pixel status
  • the display processor can accommodate an existing pixel attribute during any translation by reading an n bit attribute word representative of a pixel in the APA display buffer instead of a new n bit attribute word.
  • the translation means can include code transforming means wherein a first order m bit per pixel format, associated with a first memory structure, is transformed into a second order n bit per pixel format associated with a second memory structure.
  • the translation means may include a translation table wherein the pixel row arranged in the m bit per pixel format corresponds exclusively to a pixel row in the n bit per pixel format according to a translation requirement. This achieves the advantage that by using different translate tables, different pixel formats can be translated.
  • This computer system includes a central processing unit (CPU) (1) for executing program instructions.
  • a bus architecture (2) provides a data communication path between the CPU and other components of the computer system.
  • a read only memory (3) provides secure storage of data.
  • a fast random access memory (4) provides temporary storage of data.
  • Data communication with a host computer system (5) is provided by a communication adapter 6).
  • An I/O adapter (7) provides a means for communicating data both to and from a mass storage device (8).
  • a user can operate the computer system using a keyboard (9) which is connected to the bus architecture via a keyboard adapter (10).
  • a display device (11) provides a visual output from the computer system. The visual output is generated by a display adapter (12).
  • the display adapter comprises the display system for font expansion in accordance with the present invention which will now be described with reference to Figure 2.
  • a display character is represented by an eight pixel row (33) by fourteen pixel column (34) pixel matrix (32).
  • a one bit per pixel character font table (22) contains 256 such character representations, from which a particular pixel matrix can be selected by a coded character byte (26) stored at a text address (31) in a coded text buffer (21).
  • An attribute byte (27), associated with the coded character byte, is also stored in the coded text buffer.
  • the four most significant bits of the attribute byte specify a foreground pixel colour (28) while the four least significant bits specify a background pixel colour (29).
  • the pixel matrix is composed of fourteen eight bit rows which can be separately processed via a translation table (23) to sequentially translate the pixel matrix into a four bit per pixel format.
  • An eight bit row can contain one of 256 possible eight bit patterns.
  • a translation table (23) for translating each bit in the eight bit row into four similar bits, has 256 translation addresses for storing 32 bit row representations of all possible eight bit patterns.
  • Each four bit pixel representation is stored in an APA display buffer (25) starting at an APA display buffer address (30) corresponding to the text address in the coded text buffer.
  • This routine is based around a display system in which all four bits representing a pixel in the APA display buffer are directly accessible in a "first order" addressing format with adjacent pixels stored as adjacent four bit words.
  • a source index register indicates the next pixel row of the pixel matrix character code byte, to be translated.
  • a destination index register stores a display buffer address indicating where the next pixel row of the character is to be drawn in the APA display buffer.
  • register a", “register b”, and "register c” are general registers in the display processor which are used for data storage during execution of the routine.
  • all foregrounds (40) is the four bit foreground colour specification repeated eight times to form an 32 bit foreground specification.
  • the foreground colour (41) is “5"x, therefore "all foregrounds” is “55555555”x.
  • all backgrounds (42) is the four bit background colour specification repeated eight times to form an 32 bit background specification.
  • the background colour (43) is “9"x, therefore "all backgrounds” is "99999999”x.
  • the foreground colour specification, or the background colour specification, or both can be read from bit patterns representative of foreground and background in the APA display buffer.
  • linear offset is an incremental integer added to the contents of the DIR to point to the location in the APA display buffer where the next pixel row of the pixel matrix is to be drawn.
  • the translation table which is shown in Figure 4, is a look up table, stored in a memory in the display system, in which an eight bit row of a pixel matrix specifies an address for a corresponding 32 bit word in which each bit of the eight bit row is represented by for similar bits in the 32 bit word.
  • Step S1 loads the number of bit rows in the pixel matrix into "register c”.
  • Step S2 resets "register a”.
  • Step S3 loads the next eight bit row (44), representing an eight pixel row of the pixel matrix into "register a”.
  • the appropriate eight pixel row is specified by the contents of the SIR.
  • Step S4 increments the contents of the SIR in preparation for the next program iteration.
  • Step S5 translates each bit stored in "register a" into four similar bits according to a particular 32 bit pattern specified in "translate table".
  • Step S6 copies the contents of "register a”; inverts it via a logical NOT (47) operation; and places the inverted version (48) in "register b".
  • Step S7 sets each four bit foreground pixel specification in "register a” to a four bit representation of foreground colour (49).
  • a logical AND operation is used for this purpose (50).
  • Step S8 sets each four bit background pixel specification in "register b” to a four bit representation of background colour (51) through application of another logical AND operation (52).
  • Step S9 reassembles the eight pixel row using a logical OR (54) operation, wherein each pixel is now specified by four bits (53), according to foreground (41) and background (43) colour information.
  • Step S10 writes the eight pixel row to an APA display buffer address specified in register edi.
  • Step S11 increments the contents of the DIR by "line offset" to specify the next eight pixel row of the APA display buffer to be written to.
  • Step S12 reiterates the process on the next eight bit row of the pixel matrix.
  • Step S13 decrements the contents of "register c" on each program iteration until all composite bit rows of the pixel matrix have been processed, whereupon the display processor can be instructed to perform another task as appropriate.
  • This implementation uses 1k bytes to store a set of four bit per pixel character fonts; each of which would otherwise require 14k bytes of memory space for storage.
  • a first order one bit per pixel character font table can be translated into a second order four bit per pixel character font table.
  • the following eight pixel row translations are provided by way of example.
  • Figure 5 illustrates the first pixel format (80) of four pixels represented by two bytes, B0 and B1, stored next to each other in an APA display buffer.
  • B1 represents two pixels to the right of those pixels represented by B0 as displayed on a display output screen.
  • the same pixels are also shown in the second pixel format (81) wherein the stored bit pattern representing B1 and B0 is reversed.
  • the translation table shown in Figure 4 can therefore be rearranged to translate an eight pixel row, as shown in Figure 6, from the first order one bit per pixel format (82) to a second order four bit per pixel format by changing the order of the appropriate 32 bit pattern (83).

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
EP89310454A 1989-10-12 1989-10-12 Anzeigesystem Withdrawn EP0422294A1 (de)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP89310454A EP0422294A1 (de) 1989-10-12 1989-10-12 Anzeigesystem
CA 2021829 CA2021829A1 (en) 1989-10-12 1990-07-24 Display system
JP2233441A JPH03134699A (ja) 1989-10-12 1990-09-05 デイスプレイ・システム及びピクセル・マトリツクス変換方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP89310454A EP0422294A1 (de) 1989-10-12 1989-10-12 Anzeigesystem

Publications (1)

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EP0422294A1 true EP0422294A1 (de) 1991-04-17

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Family Applications (1)

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EP89310454A Withdrawn EP0422294A1 (de) 1989-10-12 1989-10-12 Anzeigesystem

Country Status (3)

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EP (1) EP0422294A1 (de)
JP (1) JPH03134699A (de)
CA (1) CA2021829A1 (de)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1995022813A1 (de) * 1994-02-21 1995-08-24 Vobis Microcomputer Ag Verfahren zur textdarstellung im cga-graphikmodus auf einem bildschirm eines personalcomputers
WO1999019860A1 (en) * 1997-10-16 1999-04-22 Phoenix Technologies, Ltd. Bios rom with table for expanding monochrome image into color image
KR100809088B1 (ko) * 1999-11-30 2008-03-03 노키아 모빌 폰즈 리미티드 터치 감지 슬라이드를 갖는 전자 디바이스

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0253352A2 (de) * 1986-07-14 1988-01-20 Hitachi, Ltd. System zur Verarbeitung von graphischen Daten
EP0256838A2 (de) * 1986-08-11 1988-02-24 Tektronix, Inc. System zur Verbesserung der Funktion von Zwei-Farben-Anzeigen
EP0269174A2 (de) * 1986-11-17 1988-06-01 Koninklijke Philips Electronics N.V. Logischer Schaltkreis zur Erweiterung einfarbiger Bildmuster in Farbe und Video-Prozessor mit einem solchen logischen Schaltkreis

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5919993A (ja) * 1982-07-27 1984-02-01 株式会社東芝 キヤラクタ表示回路
JPS60173585A (ja) * 1984-02-20 1985-09-06 株式会社リコー 表示制御方式
JPS60258589A (ja) * 1984-06-06 1985-12-20 株式会社日立製作所 文字図形表示回路

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0253352A2 (de) * 1986-07-14 1988-01-20 Hitachi, Ltd. System zur Verarbeitung von graphischen Daten
EP0256838A2 (de) * 1986-08-11 1988-02-24 Tektronix, Inc. System zur Verbesserung der Funktion von Zwei-Farben-Anzeigen
EP0269174A2 (de) * 1986-11-17 1988-06-01 Koninklijke Philips Electronics N.V. Logischer Schaltkreis zur Erweiterung einfarbiger Bildmuster in Farbe und Video-Prozessor mit einem solchen logischen Schaltkreis

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1995022813A1 (de) * 1994-02-21 1995-08-24 Vobis Microcomputer Ag Verfahren zur textdarstellung im cga-graphikmodus auf einem bildschirm eines personalcomputers
US5726680A (en) * 1994-02-21 1998-03-10 Vobis Microcomputer Ag Process for displaying text in the CGA graphic mode on the screen of a personal computer
WO1999019860A1 (en) * 1997-10-16 1999-04-22 Phoenix Technologies, Ltd. Bios rom with table for expanding monochrome image into color image
US6069613A (en) * 1997-10-16 2000-05-30 Phoenix Technologies Ltd. Basic input-output system (BIOS) read-only memory (ROM) including expansion table for expanding monochrome images into color image
GB2346307A (en) * 1997-10-16 2000-08-02 Phoenix Tech Ltd BIOS ROM with table for expanding monochrome image into color image
GB2346307B (en) * 1997-10-16 2002-08-07 Phoenix Tech Ltd BIOS ROM with table for expanding monochrome image into color image
KR100809088B1 (ko) * 1999-11-30 2008-03-03 노키아 모빌 폰즈 리미티드 터치 감지 슬라이드를 갖는 전자 디바이스

Also Published As

Publication number Publication date
CA2021829A1 (en) 1991-04-13
JPH03134699A (ja) 1991-06-07

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