EP0408234A2 - A non-volatile counter - Google Patents
A non-volatile counter Download PDFInfo
- Publication number
- EP0408234A2 EP0408234A2 EP90307241A EP90307241A EP0408234A2 EP 0408234 A2 EP0408234 A2 EP 0408234A2 EP 90307241 A EP90307241 A EP 90307241A EP 90307241 A EP90307241 A EP 90307241A EP 0408234 A2 EP0408234 A2 EP 0408234A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- counter
- word
- fault
- memory cells
- cells
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K21/00—Details of pulse counters or frequency dividers
- H03K21/40—Monitoring; Error detection; Preventing or correcting improper counter operation
- H03K21/403—Arrangements for storing the counting state in case of power supply interruption
Definitions
- the present invention relates to a non-volatile counter which makes efficient use of its memory cells by transferring a data word from an imperfect area of memory to another area of the memory.
- Prior art electronic counters are known which incorporate counter decades implemented as twisted ring counters (supporting five-bit Johnson coding) or which include decades represented simply by a word in an array of non-volatile RAM (NVRAM) (as disclosed in EP-273954).
- Such prior art counters achieve their function by reading the contents of the word into a Central Shifting Unit (CSU) where the word is incremented (shifted) and then written back into the memory word.
- CSU Central Shifting Unit
- This arrangement saves memory area by avoiding the need for many separate non-volatile shift registers.
- CSU Central Shifting Unit
- the CSU addresses each decade in turn, from least significant to most significant, performing increments as necessary. All this is done under the control of a sequencer circuit. On completion of this sequence the whole NVRAM array is written into its non-volatile shadow, where it remains until the next counting operation is triggered.
- Such prior art counters, and counters according to the present invention are used for applications such as odometers, elapsed time recorders and event counters.
- the present invention is designed to improve the confidence with which high numbers of counts may be made. With this in mind, since such uses by nature incorporate a "macro cell", the present invention can be included in many circuits with minimal modification, thus reducing chip design time.
- a non-volatile counter comprising: an array of memory cells incorporating groups of cells, each group of cells being divided into word strings capable of storing data words and associated fault flags; sensing means for checking the status of the memory cells and for issuing fault signals to the fault flags; and logic means responsive to the fault signals and fault flags for selecting the word strings; wherein the memory cells each include at least two non-volatile transistors and wherein on detection of a fault in a word string the stored data word is written into a second word string.
- Non-volatile memory cells (each having two or more non-volatile transistors) which are suitable for incorporating in a counter according to the present invention are disclosed in detail in U.K. Patent application (Hughes reference no. PD-H88004).
- the design of the counters according to the present invention differ from the prior art in that most of the strings of cells in the memory array are duplicated, and a system exists for selecting between the default and spare string for each data word.
- a preferred embodiment of the invention which has six counting decades (100K's, 10K's, IK's, 100's, 10's and 1's)
- only the lower four decades are provided with back up data word strings on the basis that the 100K and 10K registers are not worked sufficiently heavily to justify it.
- the non-volatile transistors suffer from endurance limitations; as the number of reprogrammings increases, so the performance of a transistor is impaired until failure becomes probable.
- the spare data word string is brought into action once one of the transistors in the default word fails (though, thanks to two-transistor redundancy, data is not lost). The counting then continues in a new, un-endured string of memory cells.
- each sensing means and each logic means are associated with only a single group of memory cells.
- Fault flags associated with the two highest decades are preferably hard-wired out of the memory array for providing "overflow” or “tamper” information or, alternatively, a "world fault report”.
- the sensing means associated with a group of memory cells is preferably activated each time a string of cells in the group stores a data word having the value "0".
- each string of cells includes six memory cells, five for storing the data word and one for the fault flag.
- each string is utilized sequentially such that no one string is over-endured.
- An improvement which is preferably included in the counter system is that of "mapping", disclosed in U.K. Patent 2171543, which involves rotating the significance of the decades. By sharing the work load among the lower decades, such that there is no one decade which suffers heavy endurance, the life of the counter is extended. Mapping may be applied very easily to the counter of the present invention, as each pair of default and spare words is addressed along a single word line. Selection of default or spare word preferably takes places after the mapping process.
- the counter includes an array of memory cells formed as groups 1a-1e of cells, sensing means 3a-3d, logic means 5a-5d, an address decoder/mapper 7 and a central shifting unit (CSU) 9.
- Each group 1 of cells is divided into two strings X, X′ of cells, each string having five non-volatile memory cells for storing a data word and a sixth memory cell which acts as a fault report flag (FR).
- FR fault report flag
- fault flags are assigned to special functions: for the 100K decade, the fault flag represents "overflow” or “tamper” to indicate when the maximum number of counts has been reached, inhibiting further counting; for the 10K decade, the fault flag is used as a "world fault report", being set upon the failure of any of the four lower decades and wired out to a pad, for example. This latter feature indicates the status of the counter, and hence whether special action is required.
- each logic means 5 is shown in detail in figure 2a. As can be seen, the circuitry includes 5 NAND gates and a NOT gate.
- the Truth table shown in figure 2b summarises the effect of the logic circuitry of figure 2a which controls the choice of word string X, X′ accessed in each group 1 of cells in the memory array at any time.
- the states of the fault flags of each group 1 of cells are fed back via a NOR gate to the logic means.
- the counter is originally set such that FRX and FRX' are set to "0" where X represents any of A, B, C or D (this may be achieved in the factory set-up routine).
- This configures the logic circuitry to select WX if X is activated by the address decoder; this is for normal read or write operations.
- the fault flag memory cell (FR) is not included in the SERIAL check because it may well hold a "1" while the rest of the word is "00000". As this memory bit is not heavily used it is not necessary to check it.
- the sensing circuit 3 puts the FAULT signal high. This causes the sequencer to toggle the fault flag of the corresponding string of cells, thus ensuring that the logic means 5 selects the spare string X′in the same group 1 of cells.
- the FAULT signal from the sensing circuit 3 also overrides the X/X′ selection performed by the spare-select logic means 5 such that, when the word is written back into the array , it is written into both X and X′ simultaneously.
- FRX NOR FRX′ When the word has been written back into both the strings X, X′ of the group, FRX and FRX′ hold the same value, so FRX NOR FRX′ is used as a logical input to the logic circuitry 5. As the counter progresses in its normal read/write routine, FRX NOR FRX′ selects which of the strings of cells X or X′ should be used.
- the spare register also fails, the procedure is identical.
- the fault is detected, so FAULT is set high by the sensing circuitry 3 and the corresponding fault flag is toggled in the string via the CSU toggler.
- the new word is written into both string X and X′, and the new state of the default flag causes operation to revert to the original word string.
- the strings of memory cells are still working because of the two-transistor redundancy in each memory cell.
- the system described above ensures that the one word string is used until it includes a memory cell having a failed non-volatile transistor, the second word string is then used until it includes a memory cell having a failed non-volatile transistor, after which the two strings are used alternately.
- LZB leading-zero-blanking bit
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Read Only Memory (AREA)
- Hardware Redundancy (AREA)
Abstract
an array of memory cells incorporating groups 1 of cells, each group 1 of cells being divided into word strings X, X′ capable of storing data words and associated fault flags FR,
sensing means 3 for checking the status of the memory cells and for issuing fault signals to the fault flags, and
logic means 5 responsive to the fault signals and fault flags for selecting the word strings,
wherein the memory cells each include at least two non-volatile transistors and wherein on detection of a fault in a word string X the stored data word is written into a second word string X′.
Description
- The present invention relates to a non-volatile counter which makes efficient use of its memory cells by transferring a data word from an imperfect area of memory to another area of the memory.
- Prior art electronic counters are known which incorporate counter decades implemented as twisted ring counters (supporting five-bit Johnson coding) or which include decades represented simply by a word in an array of non-volatile RAM (NVRAM) (as disclosed in EP-273954). Such prior art counters achieve their function by reading the contents of the word into a Central Shifting Unit (CSU) where the word is incremented (shifted) and then written back into the memory word. This arrangement saves memory area by avoiding the need for many separate non-volatile shift registers. When a decade changes from its highest state to zero, a carry is recorded and the next decade is incremented. The CSU addresses each decade in turn, from least significant to most significant, performing increments as necessary. All this is done under the control of a sequencer circuit. On completion of this sequence the whole NVRAM array is written into its non-volatile shadow, where it remains until the next counting operation is triggered.
- Such prior art counters, and counters according to the present invention, are used for applications such as odometers, elapsed time recorders and event counters. The present invention is designed to improve the confidence with which high numbers of counts may be made. With this in mind, since such uses by nature incorporate a "macro cell", the present invention can be included in many circuits with minimal modification, thus reducing chip design time.
- According to the present invention there is provided a non-volatile counter comprising:
an array of memory cells incorporating groups of cells, each group of cells being divided into word strings capable of storing data words and associated fault flags;
sensing means for checking the status of the memory cells and for issuing fault signals to the fault flags; and
logic means responsive to the fault signals and fault flags for selecting the word strings;
wherein the memory cells each include at least two non-volatile transistors and wherein on detection of a fault in a word string the stored data word is written into a second word string. - Non-volatile memory cells (each having two or more non-volatile transistors) which are suitable for incorporating in a counter according to the present invention are disclosed in detail in U.K. Patent application (Hughes reference no. PD-H88004).
- The design of the counters according to the present invention differ from the prior art in that most of the strings of cells in the memory array are duplicated, and a system exists for selecting between the default and spare string for each data word. In a preferred embodiment of the invention which has six counting decades (100K's, 10K's, IK's, 100's, 10's and 1's), only the lower four decades are provided with back up data word strings on the basis that the 100K and 10K registers are not worked sufficiently heavily to justify it. In this regard, the non-volatile transistors suffer from endurance limitations; as the number of reprogrammings increases, so the performance of a transistor is impaired until failure becomes probable. The spare data word string is brought into action once one of the transistors in the default word fails (though, thanks to two-transistor redundancy, data is not lost). The counting then continues in a new, un-endured string of memory cells.
- Preferably each sensing means and each logic means are associated with only a single group of memory cells.
- Fault flags associated with the two highest decades (100K and 10K decades) are preferably hard-wired out of the memory array for providing "overflow" or "tamper" information or, alternatively, a "world fault report".
- The sensing means associated with a group of memory cells is preferably activated each time a string of cells in the group stores a data word having the value "0".
- In a preferred embodiment of the invention, each string of cells includes six memory cells, five for storing the data word and one for the fault flag.
- If all of the strings of cells in a particular group of memory cells have their fault flags activated, it is preferable that each string is utilized sequentially such that no one string is over-endured.
- An improvement which is preferably included in the counter system is that of "mapping", disclosed in U.K. Patent 2171543, which involves rotating the significance of the decades. By sharing the work load among the lower decades, such that there is no one decade which suffers heavy endurance, the life of the counter is extended. Mapping may be applied very easily to the counter of the present invention, as each pair of default and spare words is addressed along a single word line. Selection of default or spare word preferably takes places after the mapping process.
- A specific embodiment of the present invention is now described purely by way of example with reference to the accompanying drawings, in which:
- Figure 1 is a schematic diagram of a counter according to the present invention;
- Figure 2a is a schematic diagram of the logic circuitry included in the embodiment shown in figure 1; and
- Figure 2b is a Truth table corresponding to the logic circuit shown in figure 2a.
- With reference to the drawings, the counter includes an array of memory cells formed as
groups 1a-1e of cells, sensing means 3a-3d, logic means 5a-5d, an address decoder/mapper 7 and a central shifting unit (CSU) 9. Eachgroup 1 of cells is divided into two strings X, X′ of cells, each string having five non-volatile memory cells for storing a data word and a sixth memory cell which acts as a fault report flag (FR). - Four of the
groups 1 of memory cells represent counting decades, whilst the two strings in thefifth group 1e of cells are used to store two further decades (the 10K and 100K decades). In this embodiment, which has six counting decades (100K's, 10K's, 1K's, 100's, 10's and 1's), only the four lower decades are provided with back-up strings of memory cells on the basis that the 100K and 10K registers are not worked sufficiently heavily to justify it. - Even though the 100K and 10K decades are not provided with any backup strings of cells, the strings are still provided with fault report flags since all the memory cells are arranged in an array and it is easier therefore to do so. These fault flags are assigned to special functions: for the 100K decade, the fault flag represents "overflow" or "tamper" to indicate when the maximum number of counts has been reached, inhibiting further counting; for the 10K decade, the fault flag is used as a "world fault report", being set upon the failure of any of the four lower decades and wired out to a pad, for example. This latter feature indicates the status of the counter, and hence whether special action is required.
- The logic circuitry incorporated in each logic means 5 is shown in detail in figure 2a. As can be seen, the circuitry includes 5 NAND gates and a NOT gate. The Truth table shown in figure 2b summarises the effect of the logic circuitry of figure 2a which controls the choice of word string X, X′ accessed in each
group 1 of cells in the memory array at any time. - The states of the fault flags of each
group 1 of cells are fed back via a NOR gate to the logic means. - In use, the counter is originally set such that FRX and FRX' are set to "0" where X represents any of A, B, C or D (this may be achieved in the factory set-up routine). This configures the logic circuitry to select WX if X is activated by the address decoder; this is for normal read or write operations.
- Each time the decade holds the value "0", which is "00000" (five bits), then all the non-volatile transistors in the memory cells are ON. At this stage a SERIAL check is performed, such as described in co-pending U.K. Patent application no. (Hughes reference PD-H88004) to determine whether any of the non-volatile transistors has failed. This is achieved by configuring all the non-volatile transistors in the word in series and checking the existence of a current path. The sensing means 3, which is an electronic circuit, shown in figure 1 performs this detection.
- The fault flag memory cell (FR) is not included in the SERIAL check because it may well hold a "1" while the rest of the word is "00000". As this memory bit is not heavily used it is not necessary to check it.
- If a fault is detected in the periodic check, then the sensing circuit 3 puts the FAULT signal high. This causes the sequencer to toggle the fault flag of the corresponding string of cells, thus ensuring that the logic means 5 selects the spare string X′in the
same group 1 of cells. The FAULT signal from the sensing circuit 3 also overrides the X/X′ selection performed by the spare-select logic means 5 such that, when the word is written back into the array , it is written into both X and X′ simultaneously. - When the word has been written back into both the strings X, X′ of the group, FRX and FRX′ hold the same value, so FRX NOR FRX′ is used as a logical input to the logic circuitry 5. As the counter progresses in its normal read/write routine, FRX NOR FRX′ selects which of the strings of cells X or X′ should be used.
- If then the spare register also fails, the procedure is identical. The fault is detected, so FAULT is set high by the sensing circuitry 3 and the corresponding fault flag is toggled in the string via the CSU toggler. The new word is written into both string X and X′, and the new state of the default flag causes operation to revert to the original word string. In this regard, although memory cells in both strings have faults, the strings of memory cells are still working because of the two-transistor redundancy in each memory cell. As the fault flags of both X and X′ will continue to show a fault, the system will cause the data to be toggled from one word string to the other regularly as counting continues to take place in the group of memory cells recording the particular decade, thus sharing the work-load evenly between two non-perfect data word strings.
- The system described above ensures that the one word string is used until it includes a memory cell having a failed non-volatile transistor, the second word string is then used until it includes a memory cell having a failed non-volatile transistor, after which the two strings are used alternately.
- The scheme described is not dependent on array size, so any number of words in an array of any size can be equipped with spare words and associated fault report flags. This is rendered straight forward by the fact that the spare selection activity is invisible to the addressing and mapping circuitry.
- Also possible with this system is the inclusion of a "leading-zero-blanking" bit (LZB) in each decade. This is set to (say) "0" during factory set-up, and is set to "1" the first time the decade is used. The hardware involved in providing the display can then differentiate between a leading zero (which is not displayed) and a non-leading zero (which is). The inclusion of LZB in the present scheme is straight forward, although the LZB bits must not be included in the periodic SERIAL check as they will frequently be at "1" when the rest of the word is at "00000". The same form of cell as that used for the fault flag bit may be employed. Possibly the sequencer may use the LZB bit as a periodic check inhibit signal; if the LZB bit is "0" then it is not worth checking the word as it has not yet been incremented from zero.
- The present invention has been described above purely by way of example and modifications of detail can be made within the scope of the present invention.
Claims (12)
an array of memory cells incorporating groups of cells, each group of cells being divided into word strings capable of storing data words and associated fault flags,
sensing means for checking the status of the memory cells and for issuing fault signals to the fault flags, and
logic means responsive to the fault signals and fault flags for selecting the word strings,
wherein the memory cells each include at least two non-volatile transistors and wherein on detection of a fault in a word string the stored data word is written into a second word string.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB8916017 | 1989-07-13 | ||
GB898916017A GB8916017D0 (en) | 1989-07-13 | 1989-07-13 | A non-volatile counter |
Publications (3)
Publication Number | Publication Date |
---|---|
EP0408234A2 true EP0408234A2 (en) | 1991-01-16 |
EP0408234A3 EP0408234A3 (en) | 1991-10-30 |
EP0408234B1 EP0408234B1 (en) | 1996-03-20 |
Family
ID=10659969
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP90307241A Expired - Lifetime EP0408234B1 (en) | 1989-07-13 | 1990-07-03 | A non-volatile counter |
Country Status (7)
Country | Link |
---|---|
US (1) | US5105449A (en) |
EP (1) | EP0408234B1 (en) |
JP (1) | JPH03116600A (en) |
CA (1) | CA2019581C (en) |
DE (1) | DE69025996T2 (en) |
ES (1) | ES2084661T3 (en) |
GB (1) | GB8916017D0 (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5386533A (en) * | 1990-11-21 | 1995-01-31 | Texas Instruments Incorporated | Method and apparatus for maintaining variable data in a non-volatile electronic memory device |
CN1217299C (en) * | 1998-09-30 | 2005-08-31 | 因芬尼昂技术股份公司 | Circuit and method for authenticating the content of a memory location |
US9595343B1 (en) | 2016-06-05 | 2017-03-14 | Apple Inc. | Early prediction of failure in programming a nonvolatile memory |
US10318416B2 (en) | 2017-05-18 | 2019-06-11 | Nxp B.V. | Method and system for implementing a non-volatile counter using non-volatile memory |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2171543A (en) * | 1985-02-27 | 1986-08-28 | Hughes Microelectronics Ltd | Counting circuit which provides for extended counter life |
WO1988000775A1 (en) * | 1986-07-10 | 1988-01-28 | Hughes Microelectronics Limited | An electronic counter |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3331058A (en) * | 1964-12-24 | 1967-07-11 | Fairchild Camera Instr Co | Error free memory |
US4483001A (en) * | 1982-06-16 | 1984-11-13 | International Business Machines Corporation | Online realignment of memory faults |
JPH0670880B2 (en) * | 1983-01-21 | 1994-09-07 | 株式会社日立マイコンシステム | Semiconductor memory device |
US4566102A (en) * | 1983-04-18 | 1986-01-21 | International Business Machines Corporation | Parallel-shift error reconfiguration |
JPS6049218A (en) * | 1983-08-30 | 1985-03-18 | Nippon Denso Co Ltd | Cyclometer for vehicle |
DE3532768A1 (en) * | 1985-09-13 | 1987-03-19 | Bosch Gmbh Robert | CIRCUIT ARRANGEMENT FOR ADDITION, STORAGE AND PLAYBACK OF ELECTRICAL NUMBER |
US4757522A (en) * | 1986-10-01 | 1988-07-12 | Vdo Adolf Schindling Ag | Counting circuit employing more equatably used plural counters for extended life |
US4774712A (en) * | 1986-10-01 | 1988-09-27 | International Business Machines Corporation | Redundant storage device having address determined by parity of lower address bits |
US4947410A (en) * | 1989-02-23 | 1990-08-07 | General Motors Corporation | Method and apparatus for counting with a nonvolatile memory |
-
1989
- 1989-07-13 GB GB898916017A patent/GB8916017D0/en active Pending
-
1990
- 1990-06-21 CA CA002019581A patent/CA2019581C/en not_active Expired - Lifetime
- 1990-07-03 DE DE69025996T patent/DE69025996T2/en not_active Expired - Fee Related
- 1990-07-03 EP EP90307241A patent/EP0408234B1/en not_active Expired - Lifetime
- 1990-07-03 ES ES90307241T patent/ES2084661T3/en not_active Expired - Lifetime
- 1990-07-05 JP JP2176520A patent/JPH03116600A/en active Pending
- 1990-07-17 US US07/554,045 patent/US5105449A/en not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2171543A (en) * | 1985-02-27 | 1986-08-28 | Hughes Microelectronics Ltd | Counting circuit which provides for extended counter life |
WO1988000775A1 (en) * | 1986-07-10 | 1988-01-28 | Hughes Microelectronics Limited | An electronic counter |
Also Published As
Publication number | Publication date |
---|---|
EP0408234B1 (en) | 1996-03-20 |
JPH03116600A (en) | 1991-05-17 |
GB8916017D0 (en) | 1989-08-31 |
DE69025996T2 (en) | 1996-10-02 |
CA2019581A1 (en) | 1991-01-13 |
US5105449A (en) | 1992-04-14 |
DE69025996D1 (en) | 1996-04-25 |
EP0408234A3 (en) | 1991-10-30 |
ES2084661T3 (en) | 1996-05-16 |
CA2019581C (en) | 2000-05-16 |
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