Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L12/00—Data switching networks
  • H04L12/54—Store-and-forward switching systems 
  • H04L12/56—Packet switching systems
  • H04L12/5601—Transfer mode dependent, e.g. ATM
  • H04L12/5602—Bandwidth control in ATM Networks, e.g. leaky bucket
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04J—MULTIPLEX COMMUNICATION
  • H04J3/00—Time-division multiplex systems
  • H04J3/24—Time-division multiplex systems in which the allocation is indicated by an address the different channels being transmitted sequentially
  • H04J3/247—ATM or packet multiplexing
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L12/00—Data switching networks
  • H04L12/54—Store-and-forward switching systems 
  • H04L12/56—Packet switching systems
  • H04L12/5601—Transfer mode dependent, e.g. ATM
  • H04L2012/5629—Admission control
  • H04L2012/5631—Resource management and allocation
  • H04L2012/5636—Monitoring or policing, e.g. compliance with allocated rate, corrective actions
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L12/00—Data switching networks
  • H04L12/54—Store-and-forward switching systems 
  • H04L12/56—Packet switching systems
  • H04L12/5601—Transfer mode dependent, e.g. ATM
  • H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
  • H04L2012/5684—Characteristics of traffic flows

Definitions

• the present invention relates to a statistical measurement equipment to determine the value of a
• ATM i.e. wherein data are transmitted under the form of cells or packets of bits and with a variable cell rate.
• An individual cell stream is allowed to be multiplexed on a same telecommunication link together with a plurality of other individual cell streams already multiplexed thereon, if an allocation formula is satisfied.
• This formula is based on the expected values of the mean and variance of the probability distribution function of the cell rate of the individual cell stream, on the expected values of the mean and variance of the probahility distribution function of the cell rate of each of the above mentioned other individual cell streams already multiplexed on the link, as well as on the maximum allowable bandwidth on this link.
• This allocation formula is based on the assumption that a multiplex of a relatively high number of uncorrelated probahility distribution functions leads to the normal probability distribution function, as follows from the Central Limit Theorem. However, because the mean and variance do not sufficiently define an arbitrary
• probability distribution function may be far from a normal one.
• use of the above allocation formula may give rise to an overload of the communication link.
• the known statistical measurement equipment is able to measure the values of the mean end variance of the cell rate of each individual cell stream of a multiplex.
• the purpose of this measurement is to check if the source of this individual cell stream operates within the limits on the basis of which its multiplexing on the link was allowed.
• the measurement equipment more particularly determines the value of the mean and variance of the cell rate of each individual cell stream at the receipt of each cell of this individual cell stream and compares the thus measured values with the above mentioned respective expected values thereof. Depending on the result of this comparison the received cell is then either allowed for further processing or discarded. But because the probability distribution function of the cell rate of the multiplex is not a normal one it may happen that the equipment erroneously allows a cell to be processed further.
• An object of the present invention is to provide a statistical measurement equipment of the above type, but which allows the probability distribution function of the variable to be defined in a more accurate way than by the above known mean and variance parameters.
• the present statistical measurement equipment includes means for measuring the value of said variable at least at the end of each measurement interval and means for then stepping at least one counter by a step which is function of the value thus measured? the steps being so determined that after a plurality of time
• said counter is in a position indicative of the deviation, from one or more expected values, of the
• predetermined values of said variable separate intervals to which distinct ones of said counter steps are assigned, that said measurement means measure said variable by determining the interval to which it belongs, and that said counter position is indicative of the deviation, from expected values, of the probabilities to exceed said predetermined values of said variable.
• Still another characteristic feature of the present statisticsl measurement equipment is that said counter is stepped in the one or other direction depending on the measured value of said vari ⁇ ble belonging to an interval at the one or other side of a selected one of said
• Yet another characteristic feature of the present statistical measurement equipment is thet it further includes means associated to said counter and able to detect when said counter reaches a position indicative of a maximum allowable deviation and means coupled to said detecting means and able to reduce said deviation and therefore said probabilities by chariging the value of said variable when said detecting means have detected said maximum allowable deviation.
• Another characteristic feature of the present statistical measurement equipment is that it includes a plurality of said counters able to perform distinct sets of steps assigned to distinct sets of intervals, and that the intervals of all said sets are separated by successive predetermined values of said variable.
• detecting means has detected a maximum sllowable deviation and when the variable then has a value exceeding the selected predetermined value.
• the present invention also relates to a
• telecommunication switching system with a plurality of user stations coupled to a switching network through a
• variable being the cell rate of a cell stream generated bv at least one of said user stations.
• Fig. 1 is a schematic diagram of a statistical measurement equipment SME snd of part of a
• Figs. 2 and 3 together represent in detail a statistical measurement circuit SMC forming part of the statistical measurement equipment SME of Fig. 1 ;
• Fig. 4 represents a comlementary cumulative Gaussian probability distribution function of the variable cell rate and other parameters used to illustrate the operation of the equipment of Fig. 1;
• Figs. 5 shows a probability distribution function of the variable cell rate also used to illustrate this
• Fig. 6 shows part of the memory MEM of Fig. 1 in more detail.
• the ATM (Asynchronous Transfer Mode) data packet or data cell telecommunication system shown therein includes a digital switching network DSN which is for instance of the type disclosed in the Belgian patent No 905 982.
• This digital switching network DSN has a plurality of inputs I1 to IN and outputs 01 to ON which are coupled to user stations (not shown) via input and output multiplex links and statistical measurement
• a user station is connected to the input I1 of DSN via an input multiplex link ML and a statistical measurement equipment SME having an input I and an output I1.
• the statistical measurement equipment SME comprises a receive port RX and a transmit port TX which are connected in cascade between the input I and the output I1.
• the receive port RX includes a receive buffer RBUF, a processor PR, a memory MEM, a statistical measurement circuit SMC and a clock extraction circuit CEC, whilst the transmit port TX includes a transmit buffer TBUF.
• the receive and transmit buffers RBUF and TBUF are connected in cascsde between the input I and output I1.
• the processor PR has access to these buffers as well as to the
• the clock extraction circuit CEC is connected to the input I and has a bit clock output BCL and a cell clock output CL which are both connected to the measurement circuit SMC.
• This circuit SMC which is shown in detail in Figs. 2 and 3, includes a control circuit CC, a cell counter CR to count all the cells on the above link ML, a cell counter CCR to count the cells of each of the individual cell streams of the multiplex, a measurement interval counter MIC, a cell rate interval counter CRI, a measurement interval selection register MIS, decoder circuits DEC1 and DEC2, registers REG0/5, credit counters CR0/3, increment registers IRO/14, intermediate storage circuits ISO/4, adder circuits ADO/3, comparator circuits COO/5, a
• the cell clock output CL and the bit clock output BCL of the clock extraction circuit CEC are connected to the control circuit CC having outputs T1 to T11 which control various circuits of the equipment, as indicated in a schematic way. This control will become clear from the operation of the equipment.
• the cell clock output CL is also connected to the input of the cell counter CR through the divider circuit DIV which is able to divide by 1024.
• the cell counter CR comprises 12 stages SO/11 whose outputs s0/11 are subdivided in four groups s0/2, s3/5, s6/8 and s9/11, the three outputs of each group being connected to respective data inputs of the multiplexers MUX 1/3.
• Each of these multiplexers MUX1/3 has two selection inputs sa and sb provided by the measurement interval selection register MIS.
• the outputs of the multiplexers MUX1/3 are connected to first inputs of the comparator CO4 whose second inputs are connected to the output of the
• the outputs of the cell rate interval counter CRI are connected to the decoder circuits DEC1 and DEC2 as well as to the gating circuit GC15.
• the decoder circuit DEC1 is able to translate the 4-bit cell rate interval code CRI provided at the output of CRI into a 4-out-of-15 increment code 10/14 according to the following table wherein CRI is represented in decimal form.
• the bits IO/14 of the increment code thus provided by the decoder DEC1 control the respective gating circuits GCO/14 (Fig.3) interconnecting the increment registers IRO/14, storing the respective increment values INO/14, to a first input the adder circuits ADO/3. More particularly IRO/5, IR6/8, IR9/11 and IR12/14 are connected to the first inputs of the adder circuits AD0, AD1, AD2 and AD3 via the gating circuits GCO/5, GC6/8, GC9/11 and GC12/14 and the intermediate storage circuits ISCO/3 respectively. These adder circuits ADO/3 further have an enable input
• counters CRO/3 has a further output which is connected to the first input of 3 respective one of the comparators COO/3 whose second inputs are connected to the outputs of the registers REGO/3 respectively.
• Each of these registers stores all 1's.
• the comparators COO/3 have outputs ALO/3 which are connected, together with other input signals which are continuously on 0 and 1 respectively, to the data inputs of the multiplexer MUX4 whose selection inputs are connected to the outputs of the decoder circuit DEC2.
• the latter is able to translate the 4-bit cell rate interval code CRI provided at the output of CRI into a 6-bit selection code which selects one of said inputs 0, ALO/3 and 1 according to the following table, wherein CRI is represented in decimal form :
• the multiplexer MUX4 has an output AL which is connected through gate G4 to the clock input CL of the D-flipflop DFF whose data input D is contineously on 1 and whose reset input R is controlled by the timing pulse T1.
• the multiplexer MUX4 also has an output ALB providing an output signal which is the complement of that generated on AL and which controls the gate G5 connecting the output of the comparator CO5 to the increment input of CRI as well as to the reset input of CCR.
• the flipflop DFF has a status output ST as well as a complementary status output STB which is connected to the increment input of the cell counter CCR through the gate G6.
• the above mentioned gating circuit GC15 is able to detect the presence of the code 0000 at the output of CRI and has an output ID which controls both the gating
• circuits GC16 and GC17 interconnecting the respective registers REG4 and REG5 to a first input of the comparator CO5 via the intermediate storage circuit ISC4.
• the second input of this comparator CO5 is connected to the output of the cell counter CCR.
• - CR2 is able to be incremented by one of three increment value IN9/11 under the control of 19/11.
• IN9, IN10 and IN11 are used for the cell rate intervsls 0/6, 7 and 8/11 respectively;
• Fig. 4 also a represents a staircase function comprising the points A0 to A11 and approximating the curve CCP versus CR. For these points the cell rates are equal to 0, (M-S)/A, (M-S/2)/A, ..., (M+4S)/A respectively, whilst the corresponding complementary cumulative
• PA0 1
• PA1 P1+P2+P3+P4+P5+P6+P7+P8+P9+P10 (6)
• PA2 P2+P3+P4+P5+P6+P7+P8+P9+P10 (7)
• PA3 P3+P4+P5+P6+P7+P8+P9+P10 (8)
• PA5 P5+P6+P7+P8+P9+P10 (9)
• PA7 P7+P8+P9+P10 (10)
• PA9 P9+P10 (11)
• the above described equipment is able to monitor the above staircase approximation A0 to A11 of the
• the cell rate interval CRIO/11 to which it belongs is measured 3nd for each cell received at the end of a measurement time interval the credit counter CR3 is
• decremented bv IN12, IN13 and IN14 is pruportional to the probability P0+P1+ .... +P8 that the cell rate is smaller than (M+3S)/A, to the probability P9 that this cell rate is comprised between (M+3S)/A and (M+75/2)/A, and to the probability P10 that the cell rate is comprised between (M+7S/2)/A and (M+4S)/A respectively.
• increment/decrement values IN12/14 are now so chosen that after such a large number of measurements, and supposing that the counter CR3 was started from its zero position, it is then again in this zero position. This happens when :
• increment values IN13 and IN14 are for instance so chosen that :
• the contents of the counter CR3 are indicative of the deviation of the real probabilities in the points A9 and A10 from their expected values. More particularly, the counter is negative or zero when these expected probabilities are not exceeded whereas it becomes positive when at least one of these probabilities exceeds its expected value PA9 or PA10. For this reason the counter CR3 may be used to monitor the probabilities in the points A9 and A10.
• IN1 IN2 + IN'1 (32) wherein IN'0 and IN'1 are positive values.
• PA3 1-PO-P1-P2, also in the points A1, A2 and A3 thereof.
• the user station (not shown) connected to the input multiplexer link ML is able to multiplex thereon a
• the cells of a same data stream belong to a same communication and are identified by a same label.
• this user station wants to transmit such a data stream towards a destination user station via the input link ML, the
• each of the counters CRO/3 will normally be in a negative position, but will reach a positive position when at least one of the monitored probabilities is exceeded, as described above.
• MIS measurement interval select
• M an 8-bit number of cells with label L1 such that the expected value of the mean m is equal to M/A;
• the processor PR stores the values M-S and S/2 in the above mentioned portion of the memory MEM shown in Fig. 6 and subsequent to this storage operation it controls the transmission of the path setup control cell to the transmit buffer TBUF of the transmit port TX which afterwards transfers the control cell to the digital switching network DSN.
• the processor PR stores the values M-S and S/2 in the above mentioned portion of the memory MEM shown in Fig. 6 and subsequent to this storage operation it controls the transmission of the path setup control cell to the transmit buffer TBUF of the transmit port TX which afterwards transfers the control cell to the digital switching network DSN.
• the processor PR When following the receipt of a data cell with label L1 in the buffer circuit RBUF of the receive port RX, the processor PR detects the presence of this data cell it transmits to the memory MEM a partial memory address PA which is function of the label L1 contained in the data cell. It also stores the following parameters which are updated upon the receipt of the dats cells, as will become clear later:
• MIC a 3-bit counter value indicating the measurement interval during which the last data cell having label L1 was received;
• CRI a 4-bit cell rate interval indicating one of 12 cell rate intervals CRI0 to CRI11 (Figs 5, 6),
• the clock extraction circuit CEC extracts a bit clock BCL and a cell clock CL from the incoming data cell stream and applies both BCL and CL to the control circuit CC which in response thereat provides at its outputs T1 to T11 a set of 11 successive non-overlapping timing pulses T1 to T11 (not shown) which cover a period equal to the duration of the received data cell and which are used to control various circuits of the SMC, as already mentioned.
• the cell clock signal CL is also applied to the divider circuit DIV which realises a division by 1024 the resulting clock signal CL increments the cell counter CR by 1 each time 1024 cells have been counted.
• BCL and CL are respectively equal to 600 Megabits/sec and 2,14 Megacells/sec.
• each cell has a duration of 466.67 nanoseconds and T1 to T11 each have a duration of 1/11th of this value.
• the control of SMC by the timing pulses T1 to T11 is now considered :
• the processor PR loads the parameters MIC, MIS and CCR from the memory MEM into the like named circuits of SMC. Assuming that MIS is equal to 01 the selection outputs S3 and sb of the measurement interval selection register MIS controlling the multiplexers MUX1/3 are on 0 and 1 respectively, so that only the outputs s3, s4 and s5 of the stages S3, S4 3nd S5 of the counter CR are connected to the associated comparator CO4. This means that the cell counter CR and the multiplexers MUX1/3 are used to provide the successive identities of measurement intervals having each a duration of 1024 x 8 data cells. The 3-bit value MIC identifying the last measurement time interval during which a data cell with label L1 was received is applied to the comparator CO4. Finally, the cell counter value CCR is applied to the comparator CO5.
• timing pulse T1 By the timing pulse T1 also the D-fli ⁇ flop DFF is reset. Thus the ststus output signal ST of this flipflop is brought in the condition 0 indicating that the cell with label L1 is in principle allowed to be transmitted further. Timing pulse T2
• the processor PR loads the cell rate interval value CRI and the credit value CRO from the memory MEM into the like named circuits CRI and CRO of SMC. Also the
• comparator CO4 is ensbled so that the 3-bit value MIC identifying the last measurement interval during which a dats cell with label L1 was received is compared with the value stored in the stages S3, S4 and S5 of the counter CR and constituting the identity of the measurement time interval during which the data cell which is being
• both the compared identities ar e equal the output signal MTI of CO4 is on 0 and in this case MIC is the identity of the present measurement interval. On the contrary, when both the compared identities are different the output MTI is on 1 indicating that the measurement interval has elapsed and that the value MIC has to be updated.
• the processor PR losds the values M-S and S/2 from the memory MEM into the respective registers REG4 and REG5 and enables the operstion of the decoder circuits DECl and DEC2. As a consequence the latter decodes the cell rate interval CRI into the 15-bit increment code 10/14 according to the Table 1.
• one gating circuit is enabled for operation in each of the groups GCO/5, GC6/8. GC9/11 and GC12/14 (Fig. 3)
• the processor PR enables the gating circuit GC15 so that it is checked if the cell rate interval CRI is 0 or not. In the former case the output ID of GC15 is on 0, whereas in the latter case it is on 1. As a result either the gating circuit GC16 or GC17 is enabled, so that either the value M-S or S/2 stored in REG4 or REG5 is stored in the intermediate storage circuit ISC4 associated to the comparator CO5.
• the processor PR also loads the credit value CR3 from the memory MEM into the like named credit counter CR3.
• interval stored in the counter MIC is incremented by 1 so that this counter then stores the identity of the new interval
• interval counter CRl is reset due to its reset input R being activated.
• the counter CRI indicates the identity 0000 of the first cell rate interval.
• the processor PR loads the credit value CR2 from the memory MEM into the like named credit counter CR2 and enables the intermediate storage circuit ISC3 associated to the adder circuit AD3.
• the increment values IN12/14 stored in the increment registers IR12/14 is transferred via GC12/14 into this intermediate storage circuit ISC3.
• the processor PR loads the credit value CR1 from the memory MEM into the like named credit counter CR1 and ensbles the intermediate storage circuit ISC2 associated to the adder cicuit AD2.
• the increment values IN9/11 stored in the increment registers IR9/11 is
• an input T6 of the gate G3 is activated so that if the measurement interval has elapsed, MTI being then on 1, the adder circuit AD3 is operated. As a consequence it adds the increment values stored in ISC3 to the credit value stored in ISC3, the result of this operation being stored in CR3. However, in case this adding operation exceeds a predetermined positive credit value, i.e. when AD3 overflows, it changes the contents of CR3 to all l's.
• the comparator CO3 compares the contents of CR3 and REG3 which stores all l's and produces an output signal AL3 which is on 1 when an equality is detected and on 0 in the other case. This means that AL3 is on 1 when the adder circuit AD3 has detected an overflow.
• the processor PR loads the credit value CR3 stored in CR3 back into the memory MEM. It further enables the intermediate storage circuits ISCl and ISCO associated to the adder circuits AD1 and AD0 respectively. Thus one of the increment values IN6/8 stored in the increment
• registers IR6/8 and one of the increment values INO/5 stored in the increment registers IRO/5 are transferred via GC6/8 and GCO/5 into the intermediate storage circuits ISCl and ISCO respectively. Also the input T7 of the gate G2 is activated so that if the measurement interval has elapsed, the output MTI of CO4 being then on 1, the adder circuit AD2 is operated. This operation as well as that of CO2, REG2 is similar to that of AD3, CO3, REG3 considered above. This means that the output AL2 is on 1 when AD2 has
• the processor PR loads the credit value CR2 stored in CR2 back into the memory MEM. Because the inputs T8 of the gates G0 and G1 are activated and if the measurement interval has elapsed, the output MTI of CO4 being then on 1, the adder circuits AD0 and AD1 are operated. This operation as well as that of COO. REGO and C01, REG1 is similar to that of AD3, CO3, REG3 considered above. Hence, the output AL2 or AL3 on 1 when AD0 or AD1 has detected art overflow respectively.
• the processor PR loads the credit value CR1 stored in CR1 back into the memory MEM and enables the operation of the multiplexer MUX4.
• this multiplexer is connected to the output AL if the cell rate interval CR1 is 0, 1 or 2;
• the comparator CO5 is enabled so that it compares the cell counter value stored in CCR with either the value M-S or S/2 depending on the cell rate interval stored in CRI being the interval 0 or one of the intervals 1-10 respectively. If the values compered are equal this is indicative of the fact that the cell interval has elapsed. In this case and when the output AL is on 0, or ALB on 1, then the cell rate interval counter CRI is incremented by 1 via the gate G5. Also the cell counter CCR is reset via the same gate G5 in order that a new cell count should be started.
• the processor PR loads the credit value CRO stored in CRO bsck into the memory MEM. In a first portion of T10 and via the gate G4 it brings the D-fli ⁇ flo ⁇ in the
• the processor PR during a second portion of T10 increments the cell counter CCR by 1 via the gate G6
• the processor PR stores the values of the parameters MIC, MIS and CCR back into the memory MEM.
• the cell rate interval CRI is made equal to 0 and the new cell is counted by CCR.
• the measurement interval is the same as the previous one MIC, CRI and CCR are not changed.
• it is checked by GC15 if CRI is on 0 or not and accordingly M-S or S/2 is registered in ISC4 ;
• the multiplexer MUX4 connects one of the inputs 0, ALO/3 and 1 to its output AL. More
• AL0, AL1, AL2, AL3 and 1 are connected to AL if the cell rate interval is 0, 1 or 2; 3 or 4; 5 or 6; 7 or 8; 9 or 10, 11. In this way cells will only be dropped when CRO/3 overflows and the cell rate is higher than M/A, (M+S)/A, (M+2S)/A and (M+3S)/A
• the status bit ST is changed to 1 indicating that the received cell has to be dropped.
• the cell rate counter CRI is incremented by 1 so as to indicate a new cell rate interval and the cell counter CCR is reset so that a new count can start;

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• 1988
  • 1988-11-10 WO PCT/EP1988/001037 patent/WO1990005416A1/en not_active Application Discontinuation
  • 1988-11-10 AU AU26223/88A patent/AU622424B2/en not_active Ceased
  • 1988-11-10 EP EP88909762A patent/EP0396562A1/de not_active Withdrawn
• 1989
  • 1989-11-10 ES ES8903834A patent/ES2018741A6/es not_active Expired - Lifetime
• 1990
  • 1990-05-23 NO NO90902268A patent/NO902268L/no unknown

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