EP0391672A1 - Schaltkreis, um die Energieversorgung einer CMOS-Einrichtung automatisch abzugschalten im Fall eines "Latch up" - Google Patents

Schaltkreis, um die Energieversorgung einer CMOS-Einrichtung automatisch abzugschalten im Fall eines "Latch up" Download PDF

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Publication number
EP0391672A1
EP0391672A1 EP90303571A EP90303571A EP0391672A1 EP 0391672 A1 EP0391672 A1 EP 0391672A1 EP 90303571 A EP90303571 A EP 90303571A EP 90303571 A EP90303571 A EP 90303571A EP 0391672 A1 EP0391672 A1 EP 0391672A1
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EP
European Patent Office
Prior art keywords
latch
current path
power supply
detection circuit
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP90303571A
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English (en)
French (fr)
Inventor
James W. Ratz
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Honeywell Inc
Original Assignee
Honeywell Inc
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Filing date
Publication date
Application filed by Honeywell Inc filed Critical Honeywell Inc
Publication of EP0391672A1 publication Critical patent/EP0391672A1/de
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/205—Substrate bias-voltage generators

Definitions

  • Latch-up occurs due to parasitic transistors which are inadvertently established in the substrate and well regions during the construction of integrated circuits.
  • a pair of parasitic transistors can interact through the intrinsic resistances of the device and form a circuit which operates similar to an SCR.
  • the parasitic transistors are biased off and thus do not conduct substantial current.
  • the parasitic "SCR" is never intentionally activated during the operation of the integrated circuit. If, however, a transient causes the base of either parasitic transistor to go high, current is allowed to flow from a power supply through that transistor. The current flow causes a voltage drop across the inherent well resistance or substrate resistance which turns on the other corresponding transistor. Both transistors are consequently "latched” on and remain on until the voltage supplied by the power supply is removed or the current is limited such that the transistors are forced to turn off.
  • the present invention provides an integrated circuit protection device for resetting an integrated circuit when latch-up occurs.
  • a switching means is connected in series with a current path to selectively control the flow of current through the integrated circuit.
  • a voltage comparison means monitors changes in voltage which correspond to changes in the current flowing through the integrated circuit.
  • the voltage comparison means operates cooperatively with a storage means to provide an output signal which controls the switching means. When latch-up is detected, the output signal to the switching means causes it to restrict current flow through the integrated circuit.
  • Figure 1 shows a cross sectional view of a portion of an integrated circuit with a schematic diagram of the parasitic transistors forming an SCR circuit within that portion of the integrated circuit.
  • a power supply which powers the integrated circuit is connected at terminals V+ and V ⁇ .
  • V+ and V ⁇ When a transient causes the base of either parasitic transistor to go high, current will flow from V+ through the transistors to V ⁇ .
  • the integrated circuit will consequently be latched-up.
  • the integrated circuit is latched-up, the current flowing through the integrated circuit from the power supply must be restricted in order to deactivate the internal SCR. This process is hereinafter referred to as "resetting" the integrated circuit from its latched-up state.
  • an integrated circuit 11 susceptible to being latched-up is connected to a power supply 12 through a power supply current path 13.
  • a switching means 14 is connected in series with the power supply current path 13 to selectively control the flow of current through the integrated circuit 11.
  • a storage means 15 is energized or charged through the charging path 16, and accordingly, a signal is provided to the control input of the switching means 14.
  • the signal at the control input correspondingly closes the switching means 14 to allow current to flow from the power supply 12 to the integrated circuit 11.
  • a voltage comparison means 17 is connected to the current path 13 and to the storage means 15.
  • the voltage comparison means 17 monitors the sudden increase in current flow by measuring a corresponding drop in the voltage level at the terminal V+. If the integrated circuit 11 goes into latch-up, a drop in the voltage at V+ will be detected by the voltage comparison means 17.
  • the voltage comparison means 17 will provide for or activate a discharging current path 18 through which current can flow to discharge or deenergize the storage means 15.
  • the signal applied at the control input of the switching means 14 will cause the switching means 14 to open and restrict current flow through the integrated circuit 11.
  • the integrated circuit 11 will consequently be reset since the internal SCR-type circuit activated in the integrated circuit 11 is starved of current and hence will turn off.
  • the time following latch-up detection during which the switching means 14 interrupts current flow is adjustable and controllable depending upon the characteristics of storage means 15 and charging path 16.
  • FIG. 3 there is shown a specific schematic diagram of a circuit which corresponds to the block diagram of Figure 2.
  • the circuit is connected to control the current flowing through an integrated circuit 11. Specifically, the circuit interrupts the power supply current path 23 through the integrated circuit 11 when the supply voltage drops a certain amount in a given time interval.
  • a field effect transistor (FET) 22 is connected in series from drain to source in the power supply current path 23.
  • the FET 22 is an N channel enhancement type with a threshold voltage of approximately 1.5 volts in this particular application.
  • the supply voltage at V+ is at a certain voltage level and stable. During this time, the same voltage level is present across capacitor 24 due to charging current through resistor 25. Negligible current flows through the gate of the unijunction transistor 26 and hence the voltage at the gate is nearly equal to the voltage level at V+. The unijunction transistor 26 is consequently biased off since its gate voltage is equal or substantially equal to the voltage level at its anode established across capacitor 24.
  • bipolar transistor 27 When the unijunction transistor 26 is biased off, current is not allowed to flow from the anode to the cathode of the device, and consequently, base current is not available to turn on bipolar transistor 27. Hence, during normal operation of the integrated circuit 11, the bipolar transistor 27 is biased off.
  • the power drawn by the circuit of the present invention is quite insubstantial. This characteristic is particularly important in applications where a source of power for the circuit is a battery.
  • a drop in the voltage at V+ when latch-up occurs causes a corresponding drop in voltage at the gate of the unijunction transistor 26. Since the time constant of the RC network comprising capacitor 24 and resistor 25 is relatively slow (.33 sec. in this application), and the voltage across the capacitor 24 does not change instantaneously, the drop in the initial supply voltage level is represented across the anode and gate of the unijunction transistor 26. If the drop in V+ is sufficiently large to cause the gate voltage to drop below the anode voltage by approximately .6 volts, the unijunction transistor 26 will trigger on.
  • the capacitor 24 will not recharge quickly since the time constant established by the resistor 25 connecting the capacitor to the power supply at V+ is relatively slow. It is also important to note that once the unijunction transistor 26 has been turned on, it does not turn back off until the current flowing from its anode to cathode falls below the valley current level of the device. In addition, the current flowing through the resistor 25 is sufficiently less than the valley current level of the unijunction transistor 26 such that current flowing from the supply V+ cannot maintain the on state of the unijunction transistor 26.
  • the FET 22 will turn back on when the voltage at its gate rises above its threshold voltage of approximately 1.5 volts. When this occurs, current to supply the integrated circuit 11 with power is again allowed to flow through the power supply current path 23.
  • the amount of time during which the FET 22 is off and current flow through the integrated circuit 11 is restricted is determined by the RC time constant established by the resistor 25 and capacitor 24. Hence, by selecting different values of resistor 25 and capacitor 26, the amount of time during which current flow is restricted is adjustable and controllable. For different microprocessors or other CMOS devices, it may be desirable to vary the time constant in order to achieve optimum results.
  • the delay time provided by the RC network during which current flow is impeded could be essential in assuring that the latch-up condition of the integrated circuit 11 will be reset. This could be of particular importance if parasitic capacitances within the device maintained sufficient capacity to keep on one of the parasitic transistors within the SCR-type circuit for a period of time.
  • Another feature of the present invention is the one-shot triggering of the circuit provided by the unijunction transistor 26 when latch-up is detected. Once the voltage at the gate of the unijunction transistor 26 falls below approximately 0.6 volts with respect to the anode, the device turns on. It will not turn back off if the voltage at its gate momentarily rises. Hence, the possibility of "chattering" of the circuit is eliminated. This is of particular importance if the same circuit is to be adapted for use with a variety of both microprocessors and power supplies.
  • the latch-up detection circuit monitors sudden changes in current flow within a certain time interval, as opposed to merely monitoring when the current exceeds a certain level.
  • the identical latch-up detection circuit can be used with different integrated circuits even though they each may have substantially unequal current demands during normal operation. Furthermore, gradual changes in current demand will not trigger the latch-up monitoring circuit.
  • the power supply is capable of providing a substantially constant voltage level at V+ as current varies, it may be required to increase the source resistance.
  • an additional resistor could be connected in series with the power supply current path 23 such that the voltage comparison means would monitor the voltage drop occurring across it.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Electronic Switches (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Measuring Or Testing Involving Enzymes Or Micro-Organisms (AREA)
EP90303571A 1989-04-07 1990-04-03 Schaltkreis, um die Energieversorgung einer CMOS-Einrichtung automatisch abzugschalten im Fall eines "Latch up" Withdrawn EP0391672A1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US33542089A 1989-04-07 1989-04-07
US335420 2002-12-31

Publications (1)

Publication Number Publication Date
EP0391672A1 true EP0391672A1 (de) 1990-10-10

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Family Applications (1)

Application Number Title Priority Date Filing Date
EP90303571A Withdrawn EP0391672A1 (de) 1989-04-07 1990-04-03 Schaltkreis, um die Energieversorgung einer CMOS-Einrichtung automatisch abzugschalten im Fall eines "Latch up"

Country Status (2)

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EP (1) EP0391672A1 (de)
CA (1) CA2011287A1 (de)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005119777A1 (de) * 2004-06-01 2005-12-15 Deutsches Zentrum für Luft- und Raumfahrt e.V. Verfahren zum löschen von in einer schaltung auftretenden latch-ups sowie anordnungen zum durchführen des verfahrens
DE102005059795A1 (de) * 2005-12-14 2007-06-28 Siemens Ag Vorrichtung und Verfahren zur Inbetriebnahme von Baugruppen
EP1811568A1 (de) * 2006-01-24 2007-07-25 Stmicroelectronics Sa Schutzschaltung für eine integrierte Schaltung gegen parasitäre latch-up Phänomene
CN116430212A (zh) * 2023-06-13 2023-07-14 飞腾信息技术有限公司 芯片闩锁状态的监测方法、微处理器和相关设备

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4109161A (en) * 1976-02-09 1978-08-22 Nippon Electric Company, Ltd. Memory circuit with protection circuit
US4260909A (en) * 1978-08-30 1981-04-07 Bell Telephone Laboratories, Incorporated Back gate bias voltage generator circuit
EP0175152A2 (de) * 1984-08-21 1986-03-26 Lattice Semiconductor Corporation Verfahren und Apparat um ein "Latchup Effekt" in einem CMOS-Kreis zu verhindern
EP0202074A1 (de) * 1985-05-09 1986-11-20 Advanced Micro Devices, Inc. Vorspannungsgeneratorkreis

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4109161A (en) * 1976-02-09 1978-08-22 Nippon Electric Company, Ltd. Memory circuit with protection circuit
US4260909A (en) * 1978-08-30 1981-04-07 Bell Telephone Laboratories, Incorporated Back gate bias voltage generator circuit
EP0175152A2 (de) * 1984-08-21 1986-03-26 Lattice Semiconductor Corporation Verfahren und Apparat um ein "Latchup Effekt" in einem CMOS-Kreis zu verhindern
EP0202074A1 (de) * 1985-05-09 1986-11-20 Advanced Micro Devices, Inc. Vorspannungsgeneratorkreis

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005119777A1 (de) * 2004-06-01 2005-12-15 Deutsches Zentrum für Luft- und Raumfahrt e.V. Verfahren zum löschen von in einer schaltung auftretenden latch-ups sowie anordnungen zum durchführen des verfahrens
US7310211B2 (en) 2004-06-01 2007-12-18 DEUTSCHES ZENTRUM FüR LUFT-UND RAUMFAHRT E.V. Method for suppressing latch-ups occurring in a circuit, and systems for carrying out said method
DE102005059795A1 (de) * 2005-12-14 2007-06-28 Siemens Ag Vorrichtung und Verfahren zur Inbetriebnahme von Baugruppen
EP1811568A1 (de) * 2006-01-24 2007-07-25 Stmicroelectronics Sa Schutzschaltung für eine integrierte Schaltung gegen parasitäre latch-up Phänomene
US7692906B2 (en) 2006-01-24 2010-04-06 Stmicroelectronics Sa Device for protecting an integrated circuit against latch-up phenomena
CN116430212A (zh) * 2023-06-13 2023-07-14 飞腾信息技术有限公司 芯片闩锁状态的监测方法、微处理器和相关设备
CN116430212B (zh) * 2023-06-13 2023-08-22 飞腾信息技术有限公司 芯片闩锁状态的监测方法、微处理器和相关设备

Also Published As

Publication number Publication date
CA2011287A1 (en) 1990-10-07

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