EP0379186B1 - Speicherdaten - Synthesizer - Google Patents

Speicherdaten - Synthesizer Download PDF

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Publication number
EP0379186B1
EP0379186B1 EP19900100952 EP90100952A EP0379186B1 EP 0379186 B1 EP0379186 B1 EP 0379186B1 EP 19900100952 EP19900100952 EP 19900100952 EP 90100952 A EP90100952 A EP 90100952A EP 0379186 B1 EP0379186 B1 EP 0379186B1
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EP
European Patent Office
Prior art keywords
data
address
output
signals
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP19900100952
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English (en)
French (fr)
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EP0379186A3 (de
EP0379186A2 (de
Inventor
Takeshi C/O Mitsubishi Denki K. K. Shibasaki
Hiroshi C/O Mitsubishi Denki K. K. Kobayashi
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Publication date
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Publication of EP0379186A2 publication Critical patent/EP0379186A2/de
Publication of EP0379186A3 publication Critical patent/EP0379186A3/de
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Publication of EP0379186B1 publication Critical patent/EP0379186B1/de
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/22—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of characters or indicia using display control signals derived from coded signals representing the characters or indicia, e.g. with a character-code memory
    • G09G5/222—Control of the character-code memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/22—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of characters or indicia using display control signals derived from coded signals representing the characters or indicia, e.g. with a character-code memory
    • G09G5/24—Generation of individual character patterns

Definitions

  • the present invention relates to a memory data synthesizer which can be applied, for example, to a display controller etc. for displaying arbitrary characters or patterns on the screen of a display unit.
  • Fig. 1 is a block diagram showing a conventional display controller of this type.
  • horizontal and vertical synchronizing signals are input through a synchronizing signal input circuit 1, and supplied both to an oscillation circuit 2 and an H-counter 3.
  • the oscillation circuit 2 is reset for every horizontal synchronizing signal, to oscillate at a prescribed frequency.
  • An oscillation output signal from the oscillation circuit 2 is supplied to a timing generator 4, which in turn produces timing signals required for operations of respective parts and components of the controller and outputs the same to the respective parts.
  • the H-counter 3 is reset for every vertical synchronizing signal, in order to count the horizontal synchronizing signals.
  • the count value of the H-counter 3 is supplied to a display position detecting circuit 5 for detecting display positions of characters or patterns to be displayed.
  • data and addresses for displaying desired characters or patterns are input through an input control circuit 6.
  • An address control circuit 7 addresses a display control register 8 and a display data RAM 9 in accordance with the input addresses.
  • the display control register 8 and and the display data RAM 9 are arranged on the same address space with assignment of different addresses, whereby the input data are written in designated addresses of the display control register 8 and the display data RAM 9 through a data control circuit 10.
  • Such data include character code data, color information data, display mode data, display position data and the like.
  • the display position detecting circuit 5 compares display position data stored in the display control register 7 with the count value of the H-counter 3, and supplies a coincidence signal to a read address control circuit 11 when the data coincide with the count value.
  • the read address control circuit 11 is activated to address the display data RAM 9, thereby to start reading of precedingly written data.
  • the display data RAM 9 supplies addresses corresponding to precedingly written character code data to a character ROM 12, so that corresponding fonts are read from the character ROM 12 responsively.
  • Each font is formed by pixels of l x m dots, as shown in Fig. 11, for example. Assuming that the character ROM 12 stores such fonts for n characters, its capacity corresponds to l x m x n dots.
  • Data of the fonts read from the character ROM 12 are synthesized in a synthesizing circuit 13 at need.
  • Output data from the synthesizing circuit 13 are converted from a parallel system into a serial system in a shift register 14, and supplied to a display control circuit 15.
  • the display control circuit 15 receives color information data expressing character colors, background colors etc. from the display data RAM 9 and display mode data expressing character attribution etc. from the display control register 8 in addition to the font data from the shift register 14, in order to control the font data and the color information data in accordance with a display mode indicated by the display mode data.
  • output signals representative of red, green and blue color, a luminance control signal and the like are derived from the display control circuit 15, so that desired characters or patterns are displayed on the screen in accordance with these signals.
  • the character ROM 12 includes a read control circuit 16 and a ROM part 17 as shown in Fig. 2, for example.
  • the read control circuit 16 is formed by an address decoder 18 and an output address circuit 19 as shown in Fig. 3, and the ROM part 17 is formed by m storage areas 17a to 17m as shown in Fig. 3, too.
  • Fig. 4 shows the storage area 17b, for example, in detail.
  • the remaining storage areas 17a and 17c to 17m are similar in structure.
  • it is assumed that the character ROM 12 stores fonts of l x m dots for n characters.
  • the storage area 17b includes l x n storage elements M11 to Mln, which are arranged in the form of a matrix. Each storage element is formed by an N-channel MOS transistor.
  • the storage elements ( M11 to Ml1), (M12 to M 2), ..., (M1n to Mln) in respective columns have gates which are commonly connected to word lines WL1, WL2, ..., WLn, while the storage elements (M11 to M1n), (M21 to M2n), ..., (Ml1 to Mln) in respective rows have drains which are commonly guided to bit lines BL1, BL2, ..., BLl.
  • a storage element of a bit having data as a font has a drain connected to a corresponding bit line BL.
  • the drain of the storage element M31 is connected to the bit line BL3. This corresponds to writing of font data in a chequered position shown in Fig. 11.
  • the word lines WL1 to WLn are commonly connected to all of the storage areas 17a to 17m.
  • the bit lines BL1 to BLl are connected to a power source through P-channel MOS transistors C1 to Cl respectively.
  • Data lines DL1 to Dlm for the respective storage areas 17a to 17m are connected to a power source through P-channel MOS transistors E1 to Em respectively.
  • the timing generator 4 supplies a precharge signal PC to the gates of the P-channel MOS transistors C1 to Cl and E1 to Em for a prescribed period, whereby the transistors C1 to Cl and E1 to Em responsively conduct to precharge the bit lines BL1 to BLl and the data lines DL1 to DLm.
  • the address decoder 18 supplies one of address decode signals A1 to An to a corresponding word line WL in reponse to an address from the display data RAM 9. Assuming that the address decode signal A1 is supplied to the word line WL1, for example, all of storage elements connected with the word line WL1 conduct. In the storage area 17b shown in Fig. 4, the storage elements M11 to Ml1 conduct so that the charge precharged in the bit line BL3 is extracted through the storage element M31 which is connected to the bit line BL3.
  • bit lines BL1 to BLl are commonly connected to the data line DL2 of the storage area 17b through output gate transistors G1 to Gl which are formed by N-channel MOS transistors.
  • the gates of the output gate transistors G1 to Gl are connected to control lines CL1 to CLl respectively.
  • the control lines CL1 to Cll are commonly connected with all of the storage areas 17a to 17m.
  • the output address circuit 19 sequentially supplies signals BL to Bl to the control lines CL1 to CLl in response to a timing signal from the timing generator 4. In response to this, the output gate transistors G1 to Gl sequentially conduct in the storage area 17b shown in Fig. 4, so that information in the bit lines BL1 to BLl is sequentially read on the data line DL2.
  • Similar operation is simultaneously performed with respect to the remaining storage areas 17a and 17c to 17m, whereby m -bit data are read in parallel from the storage areas 17a to 17m on the data line DL1 to DLm.
  • a signal B3 is supplied to the control line CL3
  • data on third bit lines BL3 of the storage areas 17a to 17m are read in parallel on the data lines DL1 to Dlm. This corresponds to reading of m data on the third line in Fig. 11.
  • one font is accessed upon every addressing.
  • a display controller may synthesize a font 1 (Fig. 12A) and another font 2 (Fig. 12B) which are stored in the character ROM 12 with each other, in order to display a synthetic font shown in Fig. 12C on the screen in case of cursor display or underline display, for example.
  • Fig. 5 is a timing chart of data reading in such case.
  • the display data RAM 9 supplies an address 1 to the address decoder 18, so that data on the corresponding font 1 is read from the ROM part 17 in response.
  • the display data RAM 9 supplies an address 2 to the address decoder 18, so that data on the corresponding font 2 is read from the ROM part 17 in response.
  • the data of the fonts 1 and 2 are supplied in parallel to the synthesizing circuit 13, which is formed by m RS flip-flops, which are arranged in parallel with each other, for example.
  • the RS flip-flops are first set by the data of the font 1 and then set by the data of the font 2.
  • the data of the fonts 1 and 2 are thus synthesized and latched.
  • the synthetic font shown in Fig. 12C is produced.
  • EP-A-0 136 819 discloses a semiconductor memory comprising a plurality of data lines and a plurality of word lines which are arranged to intersect the plurality of data lines. A plurality of memory cells is provided at the intersection points. A row decoder selects at least one of the plurality of word lines and a column decoder generates a signal for connecting one of the plurality of data lines to an input/output line.
  • the data must be read from the character ROM 12 in real time with scanning, and hence high-speed access is required.
  • it has been extremely difficult to access the character ROM 12 a plurality of times and synthesize the data read from the same in real time with scanning of the television set.
  • the object underlying the present invention is to provide a memory data synthesizer which can produce synthetic fonts in application to a display controller in a highly efficient manner as set out in the appended claims.
  • a plurality of data stored in memory means are accessed at the same timing to automatically generate synthetic data, which are the logical sum of the data, in the memory means.
  • synthetic fonts can be efficiently produced when a memory data synthesizer according to the present invention is applied to a character ROM for a display controller, for example.
  • Fig. 6 is a block diagram showing an embodiment of a display controller, to which a memory data synthesizer according to the present invention is applied.
  • This embodiment is different from the conventional circuit shown in Fig. 1 in that a character ROM 21 is different in its structure from the character ROM 12 shown in Fig. 1, in that the synthesizing circuit 13, which is provided in the conventional apparatus, is omitted.
  • the structure of this embodiment is similar to that shown in Fig. 1.
  • Fig. 7 is a block diagram schematically showing the exemplary structure of the character ROM 21, and Fig. 8 is a circuit showing the structure of the character ROM 21 in further detail.
  • the character ROM 21 includes a first read control circuit 22, a second read control circuit 23 and a ROM part 24.
  • the first read control circuit 22 corresponds to a first address decoder 25 and an output address circuit 27 shown in Fig. 8
  • the second read control circuit 23 corresponds to a second address decoder 26 and the output address circuit 27 shown in Fig. 8.
  • the output address circuit 27 is common to the first and second read control circuits 22 and 23.
  • the first address decoder 25 outputs one of address decode signals A1 to An-1 in response to a prescribed address from the diplay data RAM 9, while the second address decoder 26 outputs an address decode signal An in response to another prescribed address from the display data RAM 9.
  • the ROM part 24 is formed by m storage areas 24a to 24m, as shown in Fig. 8.
  • Fig. 9 is a circuit diagram showing the storage area 24b, for example, in detail.
  • the remaining storage areas 24a and 24c to 24m are similar in structure.
  • the character ROM 21 stores fonts of l x m dots for n characters, and one of specific (n-1) characters corresponding to word lines WL1 to WLn-1 is read in response to the address decode signals A1 to An-1 from the first address decoder 25, while a specific character corresponding to a word line WLn is read in response to the address decode signal An from the second address decoder 26.
  • the storage area 24b shown in Fig. 9 is similar in structure to the storage area 17b shown in Fig. 4, hence redundant description is omitted.
  • the timing generator 4 supplies a precharge signal PC to gates of P-channel MOS transistors C1 to Cl and E1 to Em for a prescribed period, whereby the transistors C1 to Cl and E1 to Em responsively conduct to precharge bit lines BL1 to BLl and data lines DL1 to DLm.
  • the display data RAM 9 supplies addresses corresponding to desired characters or patterns to the first address decoder 25 or to the second address decoder 26.
  • the first address decoder 25 or the second address decoder 26 supplies one of the address decode signals A1 to An to the corresponding word line WL.
  • the first address decoder 25 supplies the address decode signal A1 to the word line WL1, for example, all of the storage elements connected with the word line WL1 conduct.
  • storage elements M11 to Ml1 conduct so that a charge precharged in the bit line BL3 is extracted through a storage element M31, which is connected to the bit line BL3.
  • the output address circuit 27 sequentially supplies signals B1 to Bl to control lines CL1 to CLl .
  • output gate transistors G1 to Gl sequentially conduct in the storage area 24b shown in Fig. 9, so that information in the bit lines BL1 to BLl is sequentially read on the data line DL2.
  • Similar operation is simultaneously performed also with respect to the remaining storage areas 24a and 24c to 24m, whereby m -bit data are read in parallel from the storage areas 24a to 24m on the data lines DL1 to DLm.
  • the signal B3 is supplied to the control line CL3
  • data on third bit lines BL3 of the storage areas 24a to 24m are read in parallel on the data lines DL1 to DLm. This corresponds to reading of m data on the third line in Fig. 11.
  • Data of desired fonts thus read from the character ROM 21 are converted from parallel data into serial data in the shift register 14, and supplied to the display control circuit 15.
  • the display control circuit 15 receives color information data expressing character colors, background colors and the like and display mode data expressing character modification etc. from the display control register 8 in addition to the font data from the shift register 14, to display-control the font data and the color information data in accordance with a display mode indicated by the display mode data.
  • output signals representative of red, green and blue color, a luminance control signal and the like are derived from the display control circuit 15, so that desired characters or patterns are displayed on the screen in accordance with these signals.
  • the synthetic font shown in Fig. 12 is read through single access along a timing chart shown in Fig. 10. It is assumed here that the font 1 shown in Fig. 12A is stored in a storage element which is connected to the word line WL1, and the font 2 shown in Fig. 12B is stored in a storage element which is connected to the word line WLn.
  • character code data corresponding to the fonts 1 and 2 are input through an input control circuit 6. These character code data are written in designated areas of the display data RAM 9 through a data control circuit 10 in accordance with addressing by an address control circuit 7, similarly to the conventional apparatus shown in Fig. 1. In addition to the character code data, color information data display mode data, display position data and the like are written in the display control register 8 or the display data RAM 9, similarly to the conventional apparatus shown in Fig. 1.
  • a read address control circuit 11 When scanning of the screen reaches a display position, a read address control circuit 11 is activated in response to a coincidence signal from a display position detecting circuit 5. After the bit lines BL1 to BLl and the data lines DL1 to DLm have been precharged in the storage areas 24a to 24m in accordance with a precharge signal PC, the display data, RAM 9 simultaneously supplies two addresses (addresses 1 and 2) corresponding to precedingly written two character code data in accordance with a command from the read address control circuit 11 to the character ROM 21, to address the same.
  • the address 1 is supplied to the first address decoder 25 of the character ROM 21, while the address 2 is supplied to the second address decoder 26.
  • the first address decoder 25 outputs the address decode signal A1 in response to the address 1, while the second address decoder 26 outputs the address decode signal An in response to the address 2.
  • All storage elements connected with the word lines WL1 and WLn conduct in response to this.
  • the storage elements M11 to Ml1 and M1n to Mln conduct.
  • Information responsively appearing on the bit lines BL1 to BLl is the logical sum of information in the storage elements M11 to Ml1 and that in the storage elements M1n to Mln.
  • the data of the font 1 and the data of the font 2 are synthesized on the bit lines BL1 to BLl. Similar operation is also simultaneously performed on the remaining storage areas 24a and 24c to 24m. Thus, data of the synthetic font are automatically generated in the character ROM 21.
  • the data of the synthetic font are sequentially read from the character ROM 21 in a parallel system for every row ( m bits) through the data lines DL1 to DLm of the respective storage areas 24a to 24m by sequential conduction of the ouput gate transistors G1 to Gl in response to signals B1 to Bl which are sequentially supplied to the control lines CL1 to CLl from the ouput address circuit 27.
  • the parallel data are converted into serial data in the shift register 14, and supplied to the display control circuit 15.
  • the display control circuit 15 performs an operation similar to the above, whereby the synthetic font shown in Fig. 12C is displayed on the screen.
  • two address decoders are provided in the character ROM 21, which has a structure to be capable of obtaining the logical sum of outputs, to access two fonts in the character ROM 21 at the same timing for automatically generating a synthetic font, which is the logical sum thereof, in the character ROM 21 and outputting the same.
  • the synthesizing circuit 13 provided in the conventional apparatus shown in Fig. 1 can be omitted.
  • the character ROM 21 can be provided with three or more address decoders. In this case, three or more fonts in the character ROM 21 can be accessed at the same timing, to automatically generate a synthetic font, which is the logical sum thereof. Further, the second address decoder 26 can decode a plurality of addresses dissimilarly to the above embodiment, to increase the number of combination of synthesis.
  • the memory data synthesizer according to the present invention is also effective in the case of synthesizing ROM data for another object.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Studio Circuits (AREA)

Claims (5)

  1. Speicherdaten-Synthesizer, umfassend:
    - eine Adressensignal-Erzeugungseinrichtung (9) zum gleichzeitigen Bereitstellen einer Vielzahl von Adressensignalen;
    - eine Vielzahl von Identifizierungssignal-Ableitungseinrichtungen (25, 26) zum Empfangen der Vielzahl von Adressensignalen, um Identifizierungssignale (Al bis An) abzuleiten, die den jeweils empfangenen Adressensignalen entsprechen;
    - Speichereinrichtungen (24a bis 24m) mit Ausgangs-Bitleitungen (BL1 bis BLℓ), wobei die Speichereinrichtungen eine Vielzahl von vorgeschriebenen Daten unter verschiedenen Adressen speichern und die abgeleiteten Identifizierungssignale (A1 bis An) für die verschiedenen Datenadressen gleichzeitig empfangen; und
    - Ausgabeeinrichtungen (27) zum Ausgeben der adressierten Daten;
    dadurch gekennzeichnet,
    daß die mit den Identifizierungssignalen (A1 bis An) adressierten Daten als logische Summe auf den jeweiligen Ausgangs-Bitleitungen (BL1 bis BLℓ) erscheinen und daß die Ausgabeeinrichtungen eine Ausgangs-Adressenschaltung (27) zum aufeinanderfolgenden Anlegen von Leitungssignalen (B1 bis Bℓ) an die jeweiligen Ausgangs-Bitleitungen (BL1 bis BLℓ) aufweisen, um die adressierten Daten als synthetisierte Daten auszugeben.
  2. Speicherdaten-Synthesizer nach Anspruch 1,
    worin die Speichereinrichtungen (24a bis 24m) folgendes aufweisen:
    - Speicherzellen (M11 bis Mℓn), die in Form einer Matrix mit Spalten und Zeilen angeordnet sind,
    - Wortleitungen (WL1 bis WLn), die für jeden Satz von Speicherzellen (M11 bis Mℓn) in den jeweiligen Spalten zum Empfangen der Identifizierungssignale (A1 bis An) vorgesehen sind, und
    - Bitleitungen (BL1 bis BLℓ), die für jeden Satz von Speicherzellen (M11 bis Mℓn) in den jeweiligen Zeilen als Ausgangs-Bitleitungen vorgesehen sind.
  3. Speicherdaten-Synthesizer nach Anspruch 2,
    worbei jeder Satz von Speicherzellen (M11 bis Mℓn) in den jeweiligen Spalten einen vorbestimmten Datensatz speichert.
  4. Speicherdaten-Synthesizer nach einem der Ansprüche 1 bis 3,
    wobei jede Wortleitung (WL1 bis WLn) mit einer der Identifizierungssignal-Ableitungseinrichtungen (9, 21) verbunden ist,
    wobei jede Identifizierungssignal-Ableitungseinrichtung (9, 21) das Identifizierungssignal (A1 bis An) an eine der entsprechenden Wortleitungen (WL1 bis Wln) anlegt, um den vorbestimmten Datensatz zu lesen.
  5. Speicherdaten-Synthesizer nach einem der Ansprüche 1 bis 4,
    wobei die Identifizierungssignal-Ableitungseinrichtungen (9, 21) einen Adressendekoder (25, 26) zum Dekodieren des Adressensignals enthalten, um ein Adressen-Dekodiersignal (A1 bis An) als Identifizierungssignal auszugeben.
EP19900100952 1989-01-18 1990-01-17 Speicherdaten - Synthesizer Expired - Lifetime EP0379186B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP1009013A JPH02189080A (ja) 1989-01-18 1989-01-18 メモリデータ合成装置
JP9013/89 1989-01-18

Publications (3)

Publication Number Publication Date
EP0379186A2 EP0379186A2 (de) 1990-07-25
EP0379186A3 EP0379186A3 (de) 1991-03-06
EP0379186B1 true EP0379186B1 (de) 1995-07-19

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Application Number Title Priority Date Filing Date
EP19900100952 Expired - Lifetime EP0379186B1 (de) 1989-01-18 1990-01-17 Speicherdaten - Synthesizer

Country Status (3)

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EP (1) EP0379186B1 (de)
JP (1) JPH02189080A (de)
DE (1) DE69020913T2 (de)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6054471A (ja) * 1983-09-05 1985-03-28 Hitachi Ltd 半導体メモリ
JPS5894193A (ja) * 1981-11-27 1983-06-04 Ricoh Co Ltd リ−ド・オンリ−・メモリ
JPS61289600A (ja) * 1985-06-17 1986-12-19 Fujitsu Ltd 半導体記憶装置
CA1317041C (en) * 1987-12-24 1993-04-27 Ncr Corporation Apparatus for creating a cursor pattern by strips related to individual scan lines

Also Published As

Publication number Publication date
DE69020913T2 (de) 1996-04-18
DE69020913D1 (de) 1995-08-24
EP0379186A3 (de) 1991-03-06
EP0379186A2 (de) 1990-07-25
JPH02189080A (ja) 1990-07-25

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