EP0364409A1 - Fabrication de contacts de petites dimensions par piliers conducteurs formés sur une plaquette et aplanie - Google Patents

Fabrication de contacts de petites dimensions par piliers conducteurs formés sur une plaquette et aplanie Download PDF

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Publication number
EP0364409A1
EP0364409A1 EP89830379A EP89830379A EP0364409A1 EP 0364409 A1 EP0364409 A1 EP 0364409A1 EP 89830379 A EP89830379 A EP 89830379A EP 89830379 A EP89830379 A EP 89830379A EP 0364409 A1 EP0364409 A1 EP 0364409A1
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EP
European Patent Office
Prior art keywords
layer
conducting
pillars
depositing
wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP89830379A
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German (de)
English (en)
Inventor
Fabio Gualandris
Andrea Marmiroli
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
SGS Thomson Microelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics SRL filed Critical SGS Thomson Microelectronics SRL
Publication of EP0364409A1 publication Critical patent/EP0364409A1/fr
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs

Definitions

  • This "plug” process contemplates the definition of the contact areas by masking and etching an insulating dielectric layer and the filling of the contact "holes" with tungsten or heavily doped polycrystalline silicon or tungsten silicide depo­sited by chemical vapor deposition (CVD).
  • CVD chemical vapor deposition
  • the deposited film of conducting material is removed leaving the contact holes in the dielectric layer partially filled (plugged) with conducting material. A metal layer is subsequently deposi­ted.
  • the method disclosed is essentially based on the formation of trenches in the dielectric material to be filled with a me­tal through a single metal deposition step through which also contact holes an the bottom of the trenches are simul­taneously filled by the metal which is then etched back to leave a metal residue in the trenches (interconnections) and in the contact holes (plugs).
  • a main objective of the present invention is to provide a method for forming contacts or interconnecting paths bet­ween conducting layers of different level in a wafer been fabricated, capable of sensibly reducing photolithographic definition problems for submicron areas as well as step coverage problems and which may be easily practiced with common apparatuses and materials.
  • the method of the invention relies upon the formation of conducting pillars in the respective areas of contacts to be formed before forming the insulating dielec­tric layer on the semiconducting or on the conducting layer to be contacted.
  • the dielectric layer is formed around the preformed conducting pillars using a planarization proce­dure.
  • An upper level conducting layer may then be deposited over a planarized surface and in contact with the peaks of the pillars surfacing from the planarizing dielectric layer.
  • the method of the present invention has the advantages of using a definition of submicron "islands" instead of holes which can be carried out deci­sively with less lithographic difficulties, of completely eliminating step coverage problems and of requiring less fabrication steps in respect to the known "plug” techniques using tungsten or heavily doped polycrystalline silicon or tungsten silicide deposited by chemical vapor deposition for filling (plugging) submicron holes formed through the thick­ness of the insulating layer of dielectric material.
  • Figures from 1 to 8 depicts the basic steps of the pro­ cess of the invention for forming contacts or interconnec­tions between different semiconducting or conducting levels.
  • any gate oxide layer present on the source and drain areas is etched until exposing the monocrystalline silicon 1 within the active areas and simultaneously providing, by the same etching treatment, a "cleaning" of the surface of the pre­viously defined polycrystalline gate silicon runner 3.
  • the etching is carried out in a RIE type plasma, using a plasma of C2F6/O2; i.e.
  • etching may be protracted until peeling off for a maximum depth of about 100 Angstroms both the monocrystalline silicon 1 within the active areas and the surface of the polycrystalline silicon gate runner 3.
  • an annealing treat­ment under nitrogen at about 600°C for about three hours may be performed in order to eliminate possible traces of fluorine and/or carbon which could have remained absorbed at the end of the etching process of the gate oxide layer in the source and drain areas.
  • a layer of titanium 4 with a thickness preferably comprised between 800-900 Angstroms is deposited by a sputter deposi­tion process (or by any equivalent process).
  • the titanium film 4 has the double function of an etch stop layer and of a metallurgical barrier layer, as it will be discussed later (Fig. 2).
  • a layer of polycrystalline sili­con 5 with a thickness comprised preferably between 4000 and 6000 Angstroms is deposited by chemical vapor deposition conducted at about 580°C.
  • the polycrystalline silicon layer 5 is heavily doped in order to lower its bulk resistivity.
  • the underlaying titanium film 4 prevents diffusion of the dopant species in the active areas of the monocrystalline silicon substrate 1.
  • any other suitable conducting material may also be used, e.g. tungsten or tungsten silicide, depo­sited by chemical vapor deposition (Fig. 3).
  • the superim­posed conducting layers 4 and 5 constitute a multilayer con­ducting matrix for the contacts to be formed.
  • plugs 6 of photoresist having a cross section substantially identical to the de­sired cross section of the contacts or interconnections (substantially of submicron dimensions) are projectively de­fined over the areas of the contacts to be formed (Fig. 4).
  • the conducting layer 5 is anisotropically etched in a RIE type plasma until exposing the underlying titanium film (etch stop), which is particularly effetive in generating a distinct signal when the etching reaches the titanium.
  • the residual titanium layer exposed at the bottom of the etch hole through the conducting layer 5 is then removed so as the residual masking photoresist.
  • the cross section becomes as shown in Fig. 5.
  • conductive pillars having a submicron cross section and constituted by a titanium barrier layer portion 4 and by a riser portion of a different conducting material 5, such as doped polycrystalline silicon, are so formed.
  • TEOS tetraethylor­thosilicate
  • LPCVD low pressure chemical vapor deposi­tion process
  • a second planarization dielectric layer 8 is deposited, e.g. a Spun On Glass (SOG) formed by using a siloxane diluted in alco­hol and applied in a liquid state by a rotating plate di­spenser similar to those used for dispensing photoresist material and successively heat treated for converting it into a dielectric glass having a desired morphologically smoothed surface.
  • SOG Spun On Glass
  • the planarization SOG is distributed over the surface of the wafer in a quantity sufficient to sub­stantially submerge completely the existing superficial morphological features of the wafer, in particular the con­ducting pillars 5 already covered by the first insulating TEOS layer 7. By an etch-back process the peaks of the con­ ducting pillars 5 are exposed, as depicted in Fig. 7.
  • the second level metal layer 9 may then be deposited over the planarized surface of the wafer and in contact with the surfacing peaks of the distinct preformed conduc­ting pillars 5, as depicted in Fig. 8.
  • a customary masking step for geometrically defining the runners or conducting paths of the second metal level will ensue and the fabrication process may then continue in accordance with a standard sequence of steps.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
EP89830379A 1988-09-14 1989-09-06 Fabrication de contacts de petites dimensions par piliers conducteurs formés sur une plaquette et aplanie Withdrawn EP0364409A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
IT8883660A IT1225618B (it) 1988-09-14 1988-09-14 Formazione di contatti sub-micrometrici mediante pilastri conduttori preformati sul wafer e planarizzati
IT8366088 1988-09-14

Publications (1)

Publication Number Publication Date
EP0364409A1 true EP0364409A1 (fr) 1990-04-18

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
EP89830379A Withdrawn EP0364409A1 (fr) 1988-09-14 1989-09-06 Fabrication de contacts de petites dimensions par piliers conducteurs formés sur une plaquette et aplanie

Country Status (3)

Country Link
EP (1) EP0364409A1 (fr)
JP (1) JPH02114549A (fr)
IT (1) IT1225618B (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02281736A (ja) * 1989-04-24 1990-11-19 Sony Corp 多層配線形成方法
DE69211329T2 (de) * 1992-03-27 1996-11-28 Ibm Verfahren zum Herstellen von pseudo-planaren Dünnschicht PFET-Anordnungen und hierdurch erzeugte Struktur
JP2017131179A (ja) * 2016-01-29 2017-08-03 Ｋｙｂ株式会社 ブーム変位装置及びブームスプレーヤ

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0129389A2 (fr) * 1983-06-16 1984-12-27 Plessey Overseas Limited Procédé pour fabriquer une structure à couches

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0129389A2 (fr) * 1983-06-16 1984-12-27 Plessey Overseas Limited Procédé pour fabriquer une structure à couches

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
1986 PROCEEDINGS THIRD INTERNATIONAL IEEE VLSI MULTILEVEL INTERCONNECTION CONFERENCE, Santa Clara, CA, 9th-10th June 1986, pages 506-515, IEEE, New York, US; L.B. VINES et al.: "Interlevel dielectric planarization with spin-on glass films" *
EXTENDED ABSTRACTS, vol. 87-1, no. 1, Spring 1987, page 274, abstract no. 191, Philadelphia, PA, US; E.D. CASTEL et al.: "Multilevel metallization with pillar interconnects and planarization" *
S.J. MOSS et al.: "The chemistry of the semiconductor industry", 1987, pages 117-118, Blackie and Son Ltd, Glasgow, GB *
SOLID STATE TECHNOLOGY, vol. 27, no. 12, December 1984, pages 93-100, Port Washington, New York, US; A.N. SAXENA et al.: "VLSI multilevel metallization" *

Also Published As

Publication number Publication date
JPH02114549A (ja) 1990-04-26
IT1225618B (it) 1990-11-22
IT8883660A0 (it) 1988-09-14

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