EP0361583A1 - Electrical detonator for a projectile - Google Patents

Abstract

Conventional electrical or electronic detonators for projectiles with an electromagnetic generator have too high a current consumption to ensure delay times of over 15 seconds, with the result that the usual mechanical detonators cannot or can rarely be replaced. Now an electrical projectile detonator is presented which has a single low- frequency RC oscillator and a pulse counter, the outputs of which provide control signals for fore-tube safety, penetration delay and for the self-disintegration of blind shells, delay times of the order of several minutes being obtained without any problems. A programmable logic circuit with interconnected logic gates selects the desired delays by connecting to the associated output of the pulse counter, and passes the control signal on to the pyrotechnical release mechanism. <IMAGE>

Description

The invention relates to an electrical detonator for a projectile with an electrical ignition generator and a capacitor storing the ignition energy, to which an ignition chain with a switch-on element and an electronic circuit arrangement is connected, which monitors and controls the safety of the front pipe, the penetration delay of the projectile and its self-disassembly.

An electronic igniter is known which stores the ignition energy of the generator in a capacitor and compensates for the fluctuations in the consumer current by means of a voltage stabilizer (CH-A5-608 604). Two oscillators with different frequencies are provided to carry out the various functions of the fore-tube security, the self-dismantling and the impact delay, in particular of 500 Hz for the fore-tube security and of 35 kHz for the impact delay. The two oscillators are each connected to a counter and are switched on one after the other, i.e. First of all, the downtube safety and the self-disassembly time are counted down with the first oscillator and afterwards the impact delay is counted down by switching over to the other oscillator and switching off the first oscillator. The circuit of the electronic detonator is a solid-state circuit, i.e. especially designed with CMOS transistors.

Due to the high power consumption, the above-mentioned electronic detonator allows maximum delay times for downtube security, self-dismantling and impact delay of at most 15 seconds. In addition, there is no actual self-disintegration of unexploded ordnance with the circuit described, since the self-disintegration there occurs in time between the fore-pipe security and the impact delay is classified. The possible settings for the delay times for projectile ignition are therefore very limited, so that the aforementioned electronic detonator can only be suitable for very specific types of ammunition.

The invention is based on the object of providing an electrical detonator which can be used very widely, i.e. is programmable for a large number of different types of ammunition. This means that the electronic circuit of the electric detonator is designed to be particularly energy-saving, so that delay times in the order of minutes can be achieved.

According to the invention, this object is achieved in the case of an electrical detonator for a projectile in that
a single low-frequency RC oscillator applies a pulse train to a pulse counter,
- The pulse counter provides a plurality of the control signals derived from the incoming pulse train at several outputs, and
- A programmable logic circuit with a circuit of logic gates by connecting to the associated output of the pulse counter selects a control signal for the pipe safety, a control signal for the penetration delay and a control signal for the self-disassembly and passes it on to a logic switching network for the pyrotechnic trigger mechanism.

The invention is based on the fundamental knowledge that the various control signals for the functions of the fore-pipe safety, the penetration delay and the self-decomposition can all be generated by a suitable choice of the oscillator frequency and by frequency division by a single low-frequency RC oscillator and a pulse counter. This allows a particularly power-saving design and a Easy programming of the desired delay signals, as well as high resistance to shocks and vibrations.

Because of the high launch accelerations and impact delays of 50,000 g, only electromagnetic or piezoelectric generators with a capacitor storing the ignition energy are suitable as energy sources for the types of ammunition mentioned. Because of the inventive, particularly energy-saving design of the electric detonator, delay times in the order of magnitude of 10 minutes can be achieved in a reproducible and reliable manner. The electrical detonator according to the invention is therefore suitable for a large number of different types of ammunition without special adaptations and can therefore be produced in large series at a substantially lower cost.

The preferred oscillator frequency of 300 to 700 Hz, in particular around 500 Hz, is particularly advantageous and energy-saving for an RC oscillator.

The design of the pulse counter with D flip-flops according to claim 3 is particularly suitable for a current and space-saving circuit design.

It has proven itself in practice to build the programmable logic circuit according to claim 4 with groups of parallel AND gates and / or NAND gates. Such a circuit allows the desired delays to be derived from the pulse counter in a simple and easily adjustable manner.

The integrated electronic circuit based on CMOS according to claim 5 minimizes the quiescent current, so that the entire circuit arrangement has a very low power consumption and is therefore extremely suitable. The construction of such a CMOS circuit with programmable standard cells according to claim 6 has the great advantage that it is very short Connections are created between the electronic components and thus the power consumption is reduced even further.

The input circuit according to claim 7 has a safe control of the ignition element and at the same time a further current reduction.

The structure with flip-flop circuits according to claim 8 has proven particularly good in practice.

The housing of the electrical detonator according to claim 9 ensures high mechanical stability in the launch acceleration and on impact and can be made very small, in particular in the case of an electrical detonator with a CMOS circuit constructed from standard cells.

The special design of the housing according to claim 10 allows the programming of the logic circuit by soldering resistors and / or wire jumpers only at the end of the assembly.

• Fig. 1 ein Schema der Schaltungsanordnung eines elektri­schen Zünders, und
• Fig. 2 das Schema des in Fig. 1 angedeuteten Impulszählers.

Further advantages of the invention result from the following description. There, the invention is explained in more detail using an exemplary embodiment shown in the drawings. It shows:

• Fig. 1 is a schematic of the circuit arrangement of an electrical igniter, and
• Fig. 2 shows the scheme of the impulse counter indicated in Fig. 1.

In Fig. 1, various functions of the electrical igniter are designated on the left:
- NVZ is the circuit for instantaneous ignition and consists of a NAND flip-flop SR₁, two inverters I₁ and I₂, a driver B₁ and a programming switch S₁. The entrance S of the NAND flip-flop SR 1 is via the driver B 1 connected to the programming switch S₁ and the output Q is fed back with two inverters I 1 and I 2 connected in series, ie connected to the input of driver B 1. On the other hand is the exit Q the NAND flip-flop SR₁ connected to an AND gate A₂.
- PIEZO is the circuit for the piezoelectric ignition contact, ie the impact contact, and consists of a NAND flip-flop SR₂, a signal-storing D flip-flop F₁, two inverters I₃ and I₄ and a piezoelectric pulse generator PI. The input of the NAND flip-flop SR₂ is connected via the inverter I₃ to the piezoelectric pulse generator PI, and the output Q is fed back through the inverter I₄, ie connected to the input of the inverter I₃. The output Q of the NAND flip-flop SR₂ is connected to the input C of the D flip-flop F₁, the other input D is always applied with a logic one. The output Q of the D flip-flop F₁ is connected via an OR gate O₁ with AND gate A₂.
- ZK is the circuit for the normal ignition contact and consists of a NAND flip-flop SR₃, a D flip-flop F₂, two inverters I₅ and I₆, a driver B₂ and a contact switch K. The input S the NAND flip-flop SR₃ is connected via the driver B₂ to the grounding contact switch K, and the output Q is fed back via the two inverters I₅ and I₆, ie connected to the input of driver B₂. The output Q of the NAND flip-flop SR₃ is connected to the input C of the D flip-flop F₂, whose input D is in turn applied to a logic one. The output Q of the D flip-flop F₂ is connected via the OR gate O₁ with AND gate A₂.
- PROG is the circuit for setting the delay times for the front pipe safety, for the penetration delay and for self-dismantling and consists of the two programming switches S₂ and S₃ with downstream inverters I₇ and I₈ or I₉ and I₁₀. The programming switches S₂ and S₃ switch to the supply voltage + V. The outputs of the inverters I₈ and I₁₀ are connected to the inputs PROG of a pulse counter IZ - described in detail below.
- OSZ is the oscillator circuit for generating the correct clock frequency and consists of the drivers B₃ and B₄, the inverters I₁₁ to I₁₅, the capacitors C₁ and C₂ and the resistor R₁. In a first branch of the oscillator circuit, the inverter I₁₂, the driver B₃ and the resistor R₁ are connected in series. In a second branch, the inverter I₁₃, the inverter I₁₁ and the capacitor C₁ are connected in series, the output of the inverter I₁₁ being connected to ground via the capacitor C₂. In a third branch, the inverter I₁₄ and the driver B₄ are connected in series. The ends of the branches are connected to one another, the input of the inverter I₁₂ being connected to the output of the inverter I₁₃. The output of the driver B₄ is connected to the input of the inverter I₁₃ and another inverter I₁₅, which carries the oscillator signal or the clock frequency to the input OSZ of the pulse counter IZ and to an inverter I₂₃.
- RESET is the circuit of the reset of the flip-flop circuits and the pulse counter IZ and consists of an inverter I₁₆ connected to ground, two inverters connected to its output, series-connected inverters I₁₇ and I₁₈, and a charging capacitor C₃ at the output of the inverter I₁₆ . The output of the inverter I₁₈ is via an AND gate A₁ with the inputs R the NAND flip-flops SR₂ and SR₃ connected, via a further inverter I₁₉ to the reset inputs R of the D flip-flops F₃ to F₇ and via an inverter I₂₀ to the input R of the NAND flip-flop SR₁. The output of the inverter I₁₉ is also connected via an OR gate O₂ to the reset input RESET of the pulse counter IZ.

Furthermore, in Fig. 1, the output VS of the pulse counter, which provides the delay signal for the fore-pipe security, is connected to the input C of a D flip-flop F₃, the input D of which is supplied with a logic one. The output Q of the D flip-flop F₃ is connected to the input D of a further D flip-flop F₄ and to an EXOR gate X₁. The input C of the D flip-flop F₄ is applied via the inverter I₂₃ with the oscillator signal or the clock frequency. The output Q of the D flip-flop F₄ is connected to the EXOR gate X₁, the output of which is connected via an inverter I₂₁ to the AND gate A₁. In addition, the output Q of the D flip-flop F₄ is connected via an inverter I₂₂ to the reset inputs R of the D flip-flops F₁ and F₂. The clock frequency inverted after the inverter I₂₃ is also fed to the inputs C of two further D flip-flops F₅ and F₆, with a driver B₅ being interposed before the input C of the D flip-flop F₅. The input D of this D flip-flop F₅ is connected to the output of the OR gate O₁. The output Q of the D flip-flop F₅ is connected on the one hand to an EXOR gate X₂ and on the other hand to the input D of the D flip-flop F₆. The output Q of this D flip-flop F₆ is in turn connected to the EXOR gate X₂, the output of which is connected to the OR gate O₂. Furthermore, the output Q of the D flip-flop F₆ is connected to an AND gate A₃, which is also connected to the output VERZ of the pulse counter IZ, which provides the delay signal for the intrusion delay. The output of the AND gate A₃ is connected to an OR gate O₃, which is also connected to the output of the AND gate A₂ and to the output SZ of the pulse counter IZ, which provides the signal for self-decomposition. The output of this OR gate O₃ is connected to the input C of a signal-storing D flip-flop F₇. The output Q of this D flip-flop F₇ is applied to an AND gate A₄, which is also connected to the output of the inverter I₁₈. The output of the AND gate A₄ is connected via a driver B₆ to the gate of an ignition thyristor Th, whose anode is connected to a low-resistance ignition element ZE is connected to the supply voltage + V and its cathode is connected to ground. The gate of the thyristor Th is still connected to ground via a resistor R₂.

2 schematically shows the circuit structure of the pulse counter IZ, the inputs PROG, OSZ and RESET and the outputs VS, VERZ and SZ corresponding to the connections in FIG. 1.

The two PROG inputs are each connected to an inverter I₂₄ or I₂₅. The upper input PROG is additionally connected to two parallel AND gates A₅ and A₆, the lower input PROG to the AND gate A₅ and a parallel AND gate A₇. The output of the inverter I₂₄ is connected to the AND gate A₇ and a parallel AND gate A₈, and the output of the inverter I₂₅ to the AND gates A₆ and A₈. Thus, the four AND gates A₅ to A₈ form a first parallel group of AND gates which are connected in series with two further parallel groups of AND gates A₉ and A₁₂, or A₁₃ to A₁₆, i.e. AND gate A₅ is connected to AND gate A₉ and AND gate A₁₃, etc.

The actual pulse counter IZ or frequency divider consists of nineteen D flip-flops F₁₀ to F₂₈, which are connected as follows:
The input C of the D flip-flop F₁₀ is connected to the oscillator input OSZ. The exit Q is connected on the one hand to its input D and on the other hand to the input C of the subsequent flip-flop F₁₁. The exit Q this D-flip-flop F₁₁ is then connected to its input D and to the input C of the subsequent D-flip-flop F₁₂, etc.

The reset inputs R of these D flip-flops F₁₀ to F₂₈ are connected via an inverter I₂₉ and another inverter I₂₆, I₂₇ and I₂₈ to the RESET input of the pulse counter IZ. Selected outputs Q on subsequent D flip-flops are now connected to the inputs of the parallel groups of AND gates A₉ to A₁₂ or A₁₃ to A₁₆. In particular, the output Q of F₁₄ with A₉, of F₁₅ with A₁₂, of F₁₆ with A₁₀, of F₁₇ with A₁₁, and of F₂₂ with A₁₃, of F₂₃ with A₁₄, of F₂₆ with A₁₅ and of F₂₈ with A₁₆ are connected. The outputs of the second group of parallel AND gates A₉ to A₁₂ are combined via an OR gate O₄ and provide the delay signal VS of the fore-pipe safety. The outputs of the third group of parallel AND gates A₁₃ to A₁₆ are also combined via an OR gate O₅ and deliver the self-decomposition signal SZ. Since the penetration delay for the known types of ammunition is always constant - or is realized pyrotechnically with a very short delay time of the order of 0.2 to 0.5 ms - a single time delay is sufficient. Therefore, the output VERZ of the pulse counter IZ is always connected to the output Q of the D flip-flop F₁₇.

The functioning of the electric detonator is now as follows:

The oscillator OSZ delivers an oscillator signal at the input of the pulse counter IZ, here a rectangular pulse train with a frequency of 500 Hz, and is applied to the first D flip-flop F₁₀. Due to the special circuit of the D-flip-flops described above, the applied oscillator signal is passed on with a delay, so that when the second D-flip-flop F₁₁ arrives, an oscillator signal with half the frequency, i.e. 250 Hz, applied, etc. The circuit of the D flip-flops therefore also forms a frequency divider. Therefore, the pulse width of the pulse train at the output of the D flip-flop F₁₄ is 32 msec wide, at F₁₅ 64 msec, at F₁ F 128 msec, at F₁₇ 256 msec, at F₂₂ 8 seconds, at F₂₃ 16 seconds, at F₂₆ 128 seconds and on F₂₈ 512 seconds.

Depending on the position of the programming switches S₂ and S₃, one of the AND gates A₅ to A liefert provides a logical one and the other three AND gates a logical zero, ie that one of the AND gate A₉ to A₁₂ supplies a logic one when a positive edge of the square pulse sequence generated by the associated D flip-flop occurs. This generates the desired delay time for the foreline safety at the VZ output.

A similar explanation applies to the group of parallel AND gates A₁₃ to A₁₆, whereby the delay signal of self-decomposition is generated at the output SZ.

The delay signal of the front pipe security is now stored in the signal-storing D-flip-flop F₃, and delayed in the D-flip-flop F₄ by 1 msec. These two signals are passed on to the EXOR gate X 1, the output of which outputs a logical one before the delay and a logical zero after the delay.

After the projectile has been fired, the electromagnetic generator generates the supply voltage + V, which makes the reset circuit effective. The internal resistance of the inverter I₁₆ results as a pull-up voltage across the capacitor C₃, so that it charges. As soon as the drive threshold of the inverter I₁₇, actually a Schmitt trigger, is overcome, the reset signal is switched off, which applies after a few µsec.

As soon as the reset of the flip-flops is carried out by the reset circuit RESET, two signals with a logic one at the AND gate A 1 are present when a positive edge of the delay signal occurs, so that the signals from the switch-on elements PIEZO and ZK can be passed on, ie are stored in the storing D-flip-flop F₁ or F₂ and fed back in the NAND-flip-flop SR₂ or SR₃. This feedback has the effect that the applied input voltage is suppressed and that no more current flows through the ignition contact switch K or through the piezoelectric pulse generator PI. The feedback itself can be explained as follows using the example for the ignition contact:

The internal resistance of the inverter I₅ acts as a pull-up resistor for the ignition contact switch K. If there is now a short circuit at the switch K (ignition event), the NAND flip-flop SR₃ is set via the driver B₂ and the signal via its Q output pushed on the D flip-flop F₂. As soon as the NAND flip-flop SR₃ is set, the inverter I₆ is driven via the output Q and the internal resistance or pull-up resistor is inverted by the inverter I₅, i.e. to a pulldown resistor. This, however, bridges the short circuit present at the piezoelectric pulse generator PI, i.e. disabled so that no more current flows through the pulse generator PI.

This circuit with a pulse-controlled memory element (D flip-flop F₂) and a negative feedback control element (NAND flip-flop SR₃) therefore causes the positive switching edge of an applied pulse signal to be stored and then the power consumption is reduced. The pulse-controlled control element or D flip-flop F₂ also serves to suppress possible transient interference signals.

The output signal of the F flip-flop F₁ or F₂ is now passed through the OR gate O₁ to the AND gate A₂. From the circuit for undelayed ignition NVZ now follows, for example, a positive signal, so that the output signal to the OR gate O₃ is stored in the D flip-flop F₇ and is passed through the AND gate A₄ to the driver B₆, which Drives the gate of the firing thyrister Th, causing the ammunition to ignite. The condition for this is that there is a non-reset signal from the inverter I₁₈ at the AND gate A₄.

However, if a delay is desired, the AND gate A₂ is blocked by the circuit NVZ, whereby the output signal of the D flip-flop F₁ or F₂ is applied to the D input of the D flip-flop F₅. At the input C of this flip-flop F₅ is the inverted rectangular pulse train of the oscillator, whereby the Signal at the D input only after a delay of 1 msec. is passed on to the D input of the flip-flop F₆. With the EXOR gate X₂ it is determined whether there is an output signal of a closing device PIEZO or ZK, which then causes the reset of the pulse counter IZ, so that the time delay for, for example, the intrusion delay starts to run again. Is now the delay signal of the output VERZ of the pulse counter IZ and the output signal of the Q output of the flip-flop F₇ at the AND gate A₃ at the same time, a positive ignition signal is emitted and the ammunition is triggered.

Ultimately, if there is no - delayed or undelayed - ignition signal from one of the contact organs PIEZO or ZK, a self-dismantling signal occurs which causes the ammunition to ignite after a lengthy period of the order of minutes. This means that there is no longer any danger that unexploded bombs can still detonate after years, which is particularly important for practice ammunition.

It is understood that other similar designs of the electronic circuit arrangement are possible, which result in the delays described above. In particular, the programmable logic circuit with the groups of AND gates can also be constructed with groups of NAND gates.

The circuit arrangement described above was implemented with a customer-specific integrated circuit PACMOS IID from RCA. This circuit consists of blocks of standard cells based on CMOS, which are connected to one another by means of a computer program in accordance with the circuit diagram designed. These types of integrated circuits have particularly short connection paths and therefore allow a compact construction in a very small housing. This makes the above electrical detonator for artillery shells, mortar shells, projectiles from helicopter or aircraft on-board weapons as well as for anti-tank missiles, anti-aircraft projectiles and missiles.

The housing of the electric detonator, together with the pyrotechnic trigger mechanism, has a diameter of 20 mm and a height of 10 mm. It consists of a high-strength, electrically conductive metal alloy, such as Ti Al 6V4, and therefore has excellent protection against external electromagnetic radiation such as electromagnetic or nuclear electromagnetic pulses (EMP or NEMP). The ignition circuit shown in Fig. 1 is housed in its entirety in the housing - with the exception of the piezoelectric pulse generator PI and the ignition contact switch K - and is made with a casting resin of a high-strength plastic, such as with the resin CY 223, the hardener Hy 842 and Microdol as filler (Ciba Geigy), poured into the housing.

The electrical detonator manufactured in this way therefore has a very high mechanical stability and easily withstands launch accelerations and impact delays of up to 50,000 g. The reliability of the above electrical detonator with RC oscillator is much greater than that of a conventional detonator with a conventional quartz oscillator. Practical impact tests with an amplitude of 600 g with a rise time of 3 msec. and a similar drop time to 0 g have proven their full functionality in six different positions (regulation MIS-33158E). Vibration tests in three different axial directions were also unable to impair the function of the igniter. In a first test, the frequency of the sinusoidal vibrations applied was evenly increased from 600 Hz to 900 Hz with a deflection of 0.0254 mm (1/1000 inch). The test duration was 3 minutes and 40 seconds per axis. In a second test, the frequency was increased uniformly from 40 Hz to 312 Hz with a constant acceleration of 5 g, then simultaneously the frequency was increased uniformly to 1161 Hz and the acceleration to 75 g, and then the Fre frequency evenly increased with constant acceleration from 75 g to 2000 Hz. The test duration was 10 minutes per axis.

Claims (10)

1. An electrical detonator for a projectile with an electrical ignition generator and a capacitor storing the ignition energy, to which an ignition chain with a switch-on element and an electronic circuit arrangement is connected, which monitors and controls the safety of the front pipe, the penetration delay of the projectile and its self-disassembly, characterized in that that
a single low-frequency RC oscillator (OSZ) acts on a pulse counter (IZ) with a pulse train,
- The pulse counter (IZ) provides control signals derived from the incoming pulse train at several outputs, and
- A programmable logic circuit (PROG) with a circuit of logic gates by connecting to the associated output of the pulse counter (IZ) selects a control signal for the front pipe security, a control signal for the intrusion delay and a control signal for the self-decomposition and to a logic switching network for the pyrotechnic trigger mechanism continues. 2. Electrical igniter according to claim 1, characterized in that the low-frequency oscillator (OSZ) has a frequency in a range from 300 to 700 Hz, in particular 500 Hz. 3. Electrical detonator according to claim 1 or 2, characterized in that the pulse counter (IZ) provided with a plurality of outputs consists of a number of successive D flip-flop circuits (F₁₀ to F₂₈). 4. Electrical igniter according to one of claims 1 to 3, characterized in that the programmable logic circuit consists essentially of groups of parallel AND gates and / or NAND gates (A₉ to A₁₂; A₁₃ to A₁₆), which groups on the one hand with the associated outputs of the pulse counter (IZ) for the front pipe security, for the penetration delay and for the self-dismantling are connected and on the other hand with a same group of AND gates and / or NAND gates (A₅ to A₈) are connected in series, which the possible forms logical connections of the voltages dependent on the selected control signals and applied to their input. 5. Electrical igniter according to one of claims 1 to 4, characterized in that the electronic circuit arrangement is an integrated electronic circuit based on CMOS. 6. Electrical igniter according to claim 5, characterized in that the integrated electronic circuit consists of programmable standard cell-forming blocks based on CMOS. 7. Electrical detonator according to one of claims 1 to 6, characterized in that the input circuit of the switch-on element (PIEZO, ZK) has a pulse-controlled memory element (F₁; F₂) with a negative feedback control element (SR₂; SR₃), which the applied switch-on signal after Control of the memory element completely suppressed. 8. Electrical igniter according to claim 7, characterized in that the pulse-controlled memory element is a D flip-flop circuit (F₁; F₂) and the feedback control element is essentially a NAND flip-flop scarf device (SR₂; SR₃) with an inverter (I₄; I₆) as a feedback. 9. Electrical igniter according to one of the preceding claims, characterized in that a housing of a high-strength, electrically conductive metal alloy is provided, in which the electrical igniter is cast by means of a casting resin made of high-strength plastic. 10. Electrical detonator according to claim 9, characterized in that the housing is initially designed in the region of the programmable circuit (PROG) to be accessible from the outside.

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