Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
  • H03L7/00—Automatic control of frequency or phase; Synchronisation
  • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
  • H03L7/08—Details of the phase-locked loop
  • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
  • H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
  • H03L7/00—Automatic control of frequency or phase; Synchronisation
  • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
  • H03L7/08—Details of the phase-locked loop
  • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
  • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
  • H03L7/00—Automatic control of frequency or phase; Synchronisation
  • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
  • H03L7/08—Details of the phase-locked loop
  • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
  • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
  • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump

Definitions

• the present invention relates to Frequency Synthesisers and more particularly to Synthesisers including phase locking.
• a signal having a particular frequency may be synthesised digitally.
• Synthesisers have a local oscillator (L.O.) and may include a programmable or other divider, and the output of the local oscillator is locked in-phase to a reference source (typically a crystal type device the output of which may be divided by a reference divider).
• the local oscillator typically operates at several Megahertz or even Gigahertz whilst the frequency of the reference source is usually of the order of a few Kilohertz.
• Divided signals can then be phase compared in a phase detector which gives an output indicative of the phase imbalance of the divided signals. This allows frequency comparison by a digital function and so provides phase up or phase down error signal for use in controlling the local oscillator via an alteration of the applied voltage to a varactor diode.
• phase detector is part of a phase and frequency comparator including a digital phase detector and an analogue phase detector.
• the digital detector has advantages in high frequency applications in which output pulses produced thereby are used to drive a .charge pump circuit feeding or draining .an integrating capacitor whose voltage is used to control a voltage dependant resonance element, such as a varactor diode, of a voltage controlled oscillator (VCO).
• VCO voltage controlled oscillator
• a frequency synthesiser having a phase locked loop circuit including phase detector means, a digital phase detector and an analogue sample-and-hold detector where to first and second signals are applied for phase comparison, and control means for operating the detectors in tandem while a relatively large phase difference exists between the first and second signals, and for disabling the digital phase detector when a leasser phase difference is detected, the lesser phase difference being indicative of the loop approaching lock.
• the analogue sample-and-hold phase detector may comprise a capacitor, current sources for charging and draining the capacitor in accordance with phase errors fed thereto, an amplifier to a first input of which the voltage on the capacitor is applied, a feedback path between the output of the amplifier and a second input thereto, and a second capacitor between the output of the amplifier and ground, the first capacitor serving to integrate the error signals fed thereto and the second capacitor serving to integrate the output from the amplifier, whereby the detector has a linear output when the phase errors are within a predetermined range.
• Figure 1 is a schematic representation of a frequency synthesiser
• Figure 2a, 2b and 2c illustrate respectively, in graphical form, an ideal and a practical response and a response using a known solution to the distortion problem shown in Figure 2b;
• Figure 3 illustrates, in part-graphical and part-schematic view, an analogue phase detector arrangement for achieving frequency lock
• Figure 5 illustrates in schematic form a phase detector for achieving frequency lock according to an embodiment of the present invention.
• Figure 6 is a graphical representation of output voltage against phase error of a phase detector according to a preferred embodiment of the present invention.
• FIG. 7 is a block diagram of a combined phase detector incorporating the preferred analogue phase detector.
• Figure 8 is a block diagram of the analogue phase detector of Fig. 7.
• FIG. 1 shows, in schematic form, a frequency synthesiser arrangement. It can be seen that the arrangement comprises a local oscillator divider chain 1 and a reference divider chain 3 each feeding into a phase detector 5.
• the detector 5 outputs through an amplifier 7 and a filter " 9.
• the detector 5 output is used to control the local oscillator through a varactor diode 11 therein.
• the reference divider chain 3 comprises a reference frequency generator 15 providing a reference frequency which is divided in divider element 16.
• the divider element 16 divides the reference frequency by the operator K.
• the local oscillator chain comprises a local oscillator 17 which outputs a local oscillator frequency which is divided by a further divider element 19.
• the divider element 19 divides the oscillator frequency using a divisor N stored in a data latch 21.
• the output of phase detector 5, loop amplifier 7 and filter 9 is arranged to steer the LO 17 such that the phase and frequency of the two signals input to detector 5 are balanced with one another.
• Figure 2(a) illustrates an ideal frequency lock profile wherein the lock frequency FLO is accurately positioned along the curve with no "band ripple" due to the phase detector arrangement of the detector 5.
• Figure 2(b) illustrates a practical frequency response curve for a digital phase detector showing 'noise' associated with reset signals and differential delays causing ripple on the varactor control line.
• a solution Figure 2(c) has been proposed to overcome this by further processing which introduces a step in the response over the region of imprecise resolution. However, this provides a 'dead zone' around lock which is disadvantageous.
• the capacitor 50 samples the voltage in the reference cycle. If the capacitor 50 is as near ideal as possible then there will be little leakage especially if buffers (53, 55) are added. Thus, if the frequency lock condition corresponds to Vcc 2 (where Vcc is a rail voltage) and this " value is stored in capacitor 50 there will be little sag in the stored voltage value.
• the capacitor will be discharged and charged repeatedly over a set time span with a constant consequential finite phase error.
• the s/h detector is frequency locked but not phase locked.
• the analogue sample and hold phase detector is most useful when the synthesiser is near to the frequency lock situation as in-band ripple due to the digital detector may be eliminated.
• the digital detector is switched off when the synthesiser approaches frequency lock to avoid the generation of digital noise in the loop.
• FIG. 4 A symbolic diagram of a typical prior arrangement is shown in figure 4. As can be seen, the analogue sample-and-hold detector and digital detector are operated in tandem.
• the digital detector 71 receives the reference frequency and oscillator frequency. The up or down phase of these frequencies trigger a sample and hold detector 73. The digital and the analogue detector voltage outputs are then summed externally into an external amplifier 75. Once frequency lock has been achieved it is usual for the output of the digital detector to be disabled.
• the present invention couples the speed of digital detectors in approaching frequency lock with the inherently less noisy analogue type detectors such as sample-and- hold.
• Signals, from the reference source fref and the local oscillator fpd are initially directed as stated above, in tandem to a digital detector 81 and an analogue sample-and-hold detector 83. Output signals from respective detectors 81 and 83 are directed to signal processing means (not shown) whereby the voltage of the local oscillator can be adapted as stated previously.
• the sample and hold detector 83 additionally includes means to disable the digital detector 81 when the value of the S/H detector 83 approximates the preferred pre-determined value of Vcc/2. Switches 85, 87 and 89 may be added such that the digital detector may be disabled as follows :-
• FIG. 7 a combined phase detector incorporating, an analogue phase detector ( Figure 8) in accordance with a preferred embodiment of the present invention.
• the combined phase detector comprises a digital phase detector 110 arranged to receive signals at frequencies Fi and F2. One of these frequencies is derived from the output of a voltage controlled oscillator (VCO) 17 (Fig. 1) and the other frequency is derived from a stable source such as a crystal oscillator 15 (Fig. 1 also).
• VCO voltage controlled oscillator
• the digital detector 110 may be of conventional form and serves to provide phase up or phase down output signals when signals of a first of the frequencies lead or lag the signals from the other frequency source.
• the output phase error signals are fed to a charge pump 112 and to an analogue phase detector 114 in accordance with the preferred embodiment of the present invention.
• the charge pump 112 pumps current into or drains current from an integrating capacitor (not shown but forming part of the charge pump circuit).
• the output of the charge pump circuit is fed to a buffer amplifier 116 having variable feedback H s and hence to the
• VCO 11 (Fig. 1).
• a reference voltage (equal to Vcc/2) is differentially fed to the buffer amplifier 116 so that the output signal thereupon is dependant upon the difference between the voltage on the integrating capacitor and the reference voltage Vcc/2.
• the output (the phase error signal) from the digital phase detector 110 is also fed to the analogue phase detector 114.
• the phase error signal is input to a controller A which sets current levels of and is arranged to switch on and off current sources I s (up) and I s (down).
• a capacitor C is charged or drained in dependance upon which of the current sources is switched on.
• the voltage V ⁇ on the capacitor C is fed to an amplifier 120 having a feedback loop paralleled by a second capacitor C2.
• the output of the amplifier 110 is buffered by buffer amplifier 124 (which may be the same amplifier as the amplifier 116 of Figure 7 or which may feed the amplifier 116 of Figure 7).
• V i J _ • ⁇ (11 )
• V 0 _gm_ Vi
• Such an analogue phase detector has great use in the combined detector circuit of Figures 3 and 5 or 7.
• a lock detect 126 is provided.
• the lock detect is sensitive to the output voltage of the analogue detector 114.
• the lock detect is enabled and serves to disable the charge pump 112.
• the output of the detector 114 is then used to control the VCO. Any jitter or noise originating in the digital phase detector 110 is smoothed out, to a great extent, by the capacitors of the analogue detector 114.
• the analogue phase detector 114 of Figure 8 may be used in other circuits than that shown in Figure 27 (For example, Fig. 5). It will be appreciated that other feedback arrangements may be applied to the amplifier 120 of Figure 8 or to the amplifier 116 of Figure 7. Other variations are possible within the scope of the present invention, as defined by the. appended claims.

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• 1989
  • 1989-01-12 EP EP19890901578 patent/EP0354233A1/en not_active Withdrawn
  • 1989-01-12 JP JP50148589A patent/JPH02502960A/ja active Pending
  • 1989-01-12 WO PCT/GB1989/000023 patent/WO1989006881A1/en not_active Application Discontinuation

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