EP0349630A1 - Procede de dessin dans un systeme de restitution de graphique - Google Patents

Procede de dessin dans un systeme de restitution de graphique

Info

Publication number
EP0349630A1
EP0349630A1 EP19890901363 EP89901363A EP0349630A1 EP 0349630 A1 EP0349630 A1 EP 0349630A1 EP 19890901363 EP19890901363 EP 19890901363 EP 89901363 A EP89901363 A EP 89901363A EP 0349630 A1 EP0349630 A1 EP 0349630A1
Authority
EP
European Patent Office
Prior art keywords
framebuffer
array
pixel
update
respect
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP19890901363
Other languages
German (de)
English (en)
Inventor
Brian Kelleher
Thomas C. Furlong
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Digital Equipment Corp
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Publication of EP0349630A1 publication Critical patent/EP0349630A1/fr
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T11/00—2D [Two Dimensional] image generation
    • G06T11/20—Drawing from basic elements, e.g. lines or circles
    • G06T11/203—Drawing of straight lines or curves
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory

Definitions

  • This invention relates to single-instruction multiple-data (SIMD) graphics systems, and in particular to a method and means of performing graphics rendering operations in such a system.
  • SIMD single-instruction multiple-data
  • a system processor executing a graphics application program outputs signals representing matter to be displayed; this representation is generally abstract and concise in form. Such form is not suitable for the direct control of a display monitor; it is necessary to transform the relatively abstract representation into a representation which can be used to control the display. Such transformation is referred to as graphics rendering; in a system using a raster display monitor, the information comprising the transformed representation is referred to as a framebuffer. Signals specifying the framebuffer information are stored in framebuffer storage.
  • the framebuffer representation must be frequently updated, by rewriting its stored specification in part or completely, either to reflect dynamic aspects of the display, or to provide for the display of images generated from a different application program.
  • Each updating operation requires access to the memory in which the specification of the framebuffer is stored; generally a large number of locations in the framebuffer storage must be accessed for each updating operation.
  • the speed of rendering the display is limited by the requirement for graphics memory access; the greater the number of bits in the graphics memory (framebuffer storage) that can be read or written in a given time period (the "memory bandwidth") , the better the graphics performanc .
  • Graphics memory bandwidth depends on the number of memory packages (chips) comprising the graphics memory, multiplied by the number of i/o pins per package; the product is the maximum possible number of bits that can be accessed in one memory transaction. Bandwidth is then a function of this maximum number and of the time required for a memory transaction.
  • the present invention is employed in a graphics subsystem having framebuffer storage organized for storing signals specifying the pixels (x,y) of a X x Y raster framebuffer.
  • the storage is sequentially addressable as a plurality of framebuffer pixel update arrays, the set of update arrays tiling the framebuffer.
  • Each update array has a determined origin with respect to the framebuffer and comprises storage sites for specifications of a plurality of contiguously positioned framebuffer pixels.
  • Each storage site is specifiable by an offset with respect to the update array origin, the pixel specifications of an update array being concurrently updatable in a parallel memory transaction.
  • a method for selecting framebuffer pixels for drawing comprising the steps of specifying a directed line with respect to the framebuffer; accessing an update array; concurrently for all pixel sites of the accessed array (a) evaluating the sidedness of the framebuffer pixel whose specification is stored at the pixel site with respect to the directed line to derive a one-bit discriminant signal for each accessed array pixel site, and (b) using a first value of the discriminant signal to prevent writing to the accessed array pixel site.
  • the update array origin is specified as (origin x , ⁇ rigin v ) with respect to said framebuffer
  • the storage sites are specified as (offset x , offsety) with respect to the update array origin.
  • a method of drawing a convex geometric figure to the framebuffer storage comprises the steps: specifying a figure to be drawn to the framebuffer storage by specifying with respect to the framebuffer a set of directed lines such that the segments of the lines between their mutual intersections comprise the boundary of the figure, the directions of the lines being specified such that the segments perambulate- the boundary in a single sense, specifying each line as (x ⁇ , y ⁇ ) , (X , 2) ⁇ for each directed line of the set, calculating (X2 - Xi) * ⁇ _.
  • Fig. 1 is a block diagram of a data processing system in which the invention is employed
  • Fig. 2 is a block diagram of the memory chip bank of the data processing system of Fig. 1;
  • Fig. 3 is a conceptual showing of a framebuffer specified in the memory chip bank of Fig. 2, and a pixel thereof;
  • Fig. 4 is an illustrative showing of the mapping between the locations of a memory chip bank and a conceptual framebuffer
  • Fig. 5 is a block diagram of a memory controller according to the invention.
  • Fig. 6 illustrates a concept employed in the addressing means and method of the invention
  • Fig. 7 shows a geometric figure represented in terms of the concept illustrated in Fig. 6;
  • Fig. 8 shows a geometric figure tiled by a plurality of sequentially addressed framebuffer pixel arrays
  • Fig. 9 shows a geometric figure mapped to a particular framebuffer pixel array for generating an address for a next array
  • Fig. 10 shows a geometric figure mapped to a particular pixel array with an additional addressing condition imposed
  • Fig. 11 is a block diagram of an element of Fig. 5.
  • a graphics subsystem 10 (memory module) is connected by processor bus 14 to port 52 of a processor 50.
  • Bus 14 carries signals (specifying data or address) between processor 50 and subsystem 10,and is connected to subsystem 10 through a bus interface 12.
  • a subsystem data bus 16 (module bus) is connected to interface 12.
  • Each chip 24 (memory element) provides an equal plurality of storage locations, each location being addressable relative to the chip origin.
  • the random access ports of the chips of bank 20 are connected through a controller 18 to subsystem bus 16.
  • the serial output ports of the chips of bank 20 are connected by connector 150 to graphics output circuitry 22, which is.of conventional design and need not be described; signals output from circuitry 22 are connected to a conventional raster color display monitor 23.
  • Processor 50 executes a graphics application program, details of which are not pertinent to the present invention, which results in the specification of matter, such as geometric figures, to be displayed.
  • the images to be displayed are specified by processor 50 in a relatively abstract and concise form, which cannot be directly used to control the display monitor.
  • the specification must be converted to a suitable form, which for a raster display monitor is referred to as a framebuffer comprising an ordered array of framebuffer pixels, each corresponding to a display pixel of the display screen. Such conversion is referred to as rendering.
  • the rendering operations are carried out by graphics subsystem 10.
  • interface 12 comprises means for performing the usual functions of a bus interface, such as bus monitoring and support, and bus protocol.
  • interface 12 additionally provides timing means for controller 18, for output circuitry 22, for memory bank 20, and for the display monitor; means for controlling subsystem bus 16; and certain computational means whose purpose will become clear in what follows.
  • Memory module addressing means 17, responsive to signals from controller 18, provides location address signals 27 to bank 20. It should be understood that although for clarity of description memory module addressing means is shown in Fig. 1 as separate from interface 12 and controller 18, this arrangement is not significant. The necessary addressing functions may be provided by circuitry otherwise distributed, for example, distributed between interface 12 and controller 18.
  • the set of corresponding locations in the K chips (a,b) specified by a location address from module addressing means 17 comprises an addressed location array.
  • the framebuffer storage (and the corresponding framebuffer, which is conceptual rather than physical) of a graphics subsystem is mapped to the display screen in terms of pixels (picture elements) .
  • the raster display screen comprises a rectangular array of X x Y display pixels (x,y) .
  • each display pixel displays a color specified by a color value; signals specifying the color value are stored in the framebuffer storage at the (x,y) position of the framebuffer pixel corresponding to the display pixel.
  • the display is refreshed by output circuitry such as circuitry 22 in Fig.
  • a framebuffer 26 comprises an array, X framebuffer pixels across and Y framebuffer pixels vertically, corresponding to the X x Y display pixels of the display; at the specific framebuffer position (x,y) the framebuffer has n bits comprising a framebuffer pixel.
  • the framebuffer pixel is said to have depth n.
  • Module addressing means 17 and controller 18 control the storage of signals in the A x B video RAM chips 24 of bank 20 in addressed array locations such that signals specifying certain adjacent framebuffer pixels can be accessed in bank 20 in parallel through controller 18 responsive to a single location address relative to ' chip origin, supplied in parallel to all chips from module addressing means 17.
  • the framebuffer pixel signals are so stored that an update array of W x H pixels can be accessed in parallel, the update array being so specified that the entire X x Y framebuffer (and display) can be tiled by a plurality of such W x H update arrays having determined origins.
  • Each update array can be identified by an array origin identifier.
  • connections 150 between the serial output ports of chips 24 and video output circuitry 22 determine the mapping between chips 24 and the display screen; that is, the framebuffer pixels in memory 20, as located by the mapping between controller 18 and chips 24, must be serially accessed in raster order of (x,y) to refresh the display.
  • FIG. 4 by way of illustration the mapping is shown between a conceptual three- dimensional framebuffer and a corresponding physical chip bank laid out on a plane.
  • These two pixels are in the first update array, and can be accessed in parallel because they are in different chips in the chip array and are in corresponding locations in the respective chips.
  • framebuffer 26-E is tiled by four 5x5 update arrays of framebuffer pixels having array origins at (1,1), (6,1), (1,6) and (6,6), and that the signals representing all the framebuffer pixels of an update array, stored in the graphics subsystem memory, will be concurrently accessed in parallel in a single memory transaction, specified by a single location address from addressing means 17. In an actual graphics system of interest, many more than four update arrays are required to tile the display.
  • the framebuffer pixels are stored in a set of contiguous storage locations within chips 24-E.
  • controller 18 provides state machines 100 for controlling the state of the controller; state machines 100 receive timing signals from interface 12 on lines 80. Controller 18 further provides read/write enable generating means 102, which outputs to each of chips 24 of bank 20 read/write enable signals on lines 88, in the course of a controller graphics rendering operation.
  • controller 18 provides state machines 100 for controlling the state of the controller; state machines 100 receive timing signals from interface 12 on lines 80. Controller 18 further provides read/write enable generating means 102, which outputs to each of chips 24 of bank 20 read/write enable signals on lines 88, in the course of a controller graphics rendering operation.
  • data is transmitted on 40- bit parallel path 84 between controller 18 and subsystem bus 16; data is transmitted on 160-bit parallel path 86 between controller 18 and memory bank 20.
  • controller 18 For each memory chip of bank 20, controller 18 provides at 104 an internal logical processor for the execution of graphics operations, the processors of 104 operating in parallel (concurrently) .
  • graphics operations include, for example, writing a geometrical figure to the framebuffer, moving a figure from one part of the framebuffer to another part (which requires both portions of the framebuffer to be redrawn) , drawing a line, and the like.
  • three further logical processors 105 are provided, which operate in parallel with processors 104, as will be described.
  • the framebuffer is tiled by a number of updated arrays having determined origins.
  • a figure to be written to the framebuffer storage in general is mapped to only a subset of the update arrays.
  • the operation of writing a line or geometric figure to the framebuffer comprises two basic steps. First, it is necessary to determine which update arrays should be addressed to tile the figure, and to address each such array in turn; second, it is necessary to determine which pixel specifications within an addressed update array must be written and to write such pixel specifications. Means and methods for carrying out each of these steps will now be described.
  • a directed line divides a plane into left and right half-spaces.
  • a half-space evaluation decides on which side of a directed line any point (in a plane) lies.
  • all points shown as "+" are in the left half-space, all points shown as "-" are in the right half-space, with respect to the directed line.
  • the line has infinite length.
  • Equation (1) is true for values of x and y on the line; y > mx + b for points on one side of the line; and y ⁇ mx + b for points on the other side of the line.
  • Equation (2) is represented in the real number system. In the present operation, the equation must be evaluated for the specific locations of the framebuffer pixels, to decide whether a specific pixel is inside or outside a figure to be drawn, the figure being composed of a plurality of directed lines. From equation (2) is derived equation (3) :
  • equation (3) is 0 for (x,y) on the line, positive for (x,y) on one side of the line, and negative for (x,y) on the other side of the line.
  • equation (4) is advantageous because it minimizes computation and therefore minimizes both circuitry and computation time. Most of its terms can be calculated either once per half-space evaluation (that is, once for each directed line of a geometric figure to be written to the framebuffer) or once per array access. Of the terms in equation (4) , dx, dy, X2. a ⁇ -' ⁇ - Yi are constant for any particular half-space, and therefore (4c) need only be evaluated once per half-space. The value of this expression is unaffected by pixel position within the update array, or by change to another update array. The expression (4b) must be calculated once for each update array access.
  • Expression (4a) must be evaluated for all sites of the array.
  • the expressions offset x and offsety are positive integers specifying the site position within the array; as this is determined by hardware design, these values are built in to controller 18.
  • the value of (4a) can then be easily found in terms of dx and dy; the result (the "site value") is calculated by controller 18 for each half- space (i..e. for each directed line) and stored for each array site.
  • the site values do not depend upon the particular accessed array, but are constant for the particular lines comprising the figure being drawn.
  • the values of dx, dy are provided by interface 12.
  • the sum of (4b) and (4c) is called the "half-space constant.”
  • a new half-space constant must be specified for each accessed update array because the value depends on the origin of the array (originx, originy) .
  • the same value of the half-space constant is specified to every logical processor of 104.
  • the sign of the sum of the stored site value and the half-space constant functions as a discriminant which gives the sidedness of the pixel with respect to the line; since the sign bit is the only bit of interest, a comparator can be used instead of an adder. Therefore, referring to Fig.
  • each logical processor of 104 comprises a register 204 to store the site value, input at the commencement of a tiling operation; a magnitude comparator 200, to which the site value from register 204 is a first input; and a second input 202, on which the half-space constant for the array is input to comparator 200.
  • the discriminant signal is output on line 206.
  • the half-space evaluation must be made for each line bounding the figure to be drawn to the framebuffer.
  • the interior area of a triangle for example, can be represented as the intersection of three half-spaces with respect to the sides, represented as directed lines.
  • the segments of the lines between their mutual intersections comprise a closed boundary of a convex geometric figure.
  • the directions of the lines must be such that the segments perambulate the boundary in a single sense; that is, the line segments must all be "nose to tail”.
  • Ascertaining whether a pixel is inside the triangle is accomplished by concurrently evaluating its sidedness with respect to three directed lines.
  • a processor of the kind shown in Fig. 11 must be provided at 104 for each half-space evaluation to be made.
  • the output of the AND is used to condition the write enable 88 to the memory chip 24 on which the specification of the pixel is stored.
  • a first value of the result discriminant specifies insidedness of the pixel; the second value specifies outsidedness.
  • a write enable to the pixel site cannot be provided in the presence of a result discriminant of the second value.
  • Other conditions may be imposed on the write enable, for example, as a result of windowing, clipping and other operations.
  • the method can be generalized to n-sided convex polygons; more complex figures can be represented as composed of convex polygons. Line segments on a raster display can be modeled as the intersection of four half-spaces.
  • Data signals specifying the geometric figure to be drawn are transmitted by processor 50 to interface 12, which transmits the necessary data to controller 18.
  • Such specification must include, whether explicitly or implicitly in terms of the order of specifying the line segment end points, direction of each of the line segments, such that a closed figure is specified by the line segments between mutual intersections and the figure boundary is perambulated by the segments in a single sense.
  • the rendering operation can begin with any arbitrary location in the figure to be drawn; for example, a first vertex can be selected and the update array to which it is mapped first accessed. Alternatively,- a preliminary evaluation can be made to find the left ⁇ most (or right-most) point in the figure to be drawn, after which the update array to which that point is mapped is first accessed. This latter method offers certain economies of operation.
  • controller 18 begins operation by accessing the initial update array. Controller 18 outputs an appropriate address request at 94 to interface 17, which provides corresponding location address signals to memory bank 20. By concurrently performing half-space evaluations for the pixels of the first update array with respect to the corresponding portion of the figure to be drawn, processors 104 of controller 18 control write enable means 102 to output signals on 88 so as to permit the writing of the corresponding pixels.
  • a next update array must then be addressed, accessed and written, and so on until the geometric figure has been tiled.
  • a tiling operation is illustrated in Fig. 8 in which a triangle is shown tiled by 53 update arrays. The numbers in each box indicate the order in which the update arrays are accessed.
  • Array 1 is first accessed. In the method illustrated in Fig. 8, the initially accessed array is the one with the first vertex. In the alternative method, array 53 would be first accessed, as having the left-most element of the figure mapped to it.
  • Controller 18 stores the address of the initially accessed update array in storage 115.
  • the pixels of the initial array are written as described.
  • a test (to be described) is performed to decide whether the figure continues to the array below the initially accessed array; if it does, the stored array address is so marked (for example, by a flag) .
  • the test is performed to decide whether the figure continues to the array above the initial array; if so, the stored array address is so marked. If the figure to be drawn was not initially evaluated to find the left-most point in it, the test is performed to decide whether the figure continues to the array to the left of the initial array.
  • controller 18 If it does, controller 18 outputs address request signal 94, specifying the next array; in response, addressing means 17 outputs location address signal 27 to memory bank 20, addressing the specified next update array.
  • the pixels of this next array are written as a result of half-space evaluation operations as previously described. The tests (down, up and left) are performed again. However, if the address of any array in this row has previously been stored and flagged for down continuation of the figure, the address of this array will not be so flagged; similarly for up continuation. The operation is repeated until the result of the test indicates that the figure is not mapped to the next left array. For example, in Fig. 8, after writing array 1, it is found from the test that the array to the left of it is not mapped to the figure.
  • Controller 18 then (using the specification of the initial array stored at 115) performs the tests with respect to the array next on the right of the initial array. Again, if the figure is mapped to this array, it is accessed and the pixels are written by means of parallel half-space evaluation operations as previously described. As the specification of the starting point has been saved, no array is accessed or written twice.
  • every array in that row to which the figure is mapped has been accessed and written, and at most one array address has been flagged for up continuation and one for down continuation.
  • controller 18 When no further arrays in the row are found to be mapped to the figure, controller 18 operates with respect to the flagged array addresses, to access a downwardly adjacent array. This becomes the initial array of the next horizontal procedure. When no further arrays downwardly are found to be mapped to the figure, the process pops to the first stored array which has been flagged for upward continuation of the figure. When no further upward flags are found, the process has been completed. It will be understood that the upward flags could be first exhausted before moving to the downward flags; the requirement is simply that all arrays to which the figure is mapped should be accessed and written, without repeating any operation.
  • a border set of pixels is defined as the row or column of pixels in the previously addressed 4 x 4 array lying closest to the array in question. (The dimensions 4 x 4 are exemplary only.)
  • the pertinent half-space evaluations are performed by sampling each of the two pixels which bound the border set. However, as will be noted in Fig. 9, one (0,0) of the sampled pixels (considered to be located at its origin corner) is within the currently accessed update array, while the other (0,4) is outside it.
  • the (0,0) pixel evaluation is performed by the corresponding logical processor of 104 in the course of writing the figure to the update array; the additional three logical processors 105 are provided to perform the parallel evaluation of the three pixel locations (4,0), (0,4) and (4,4) which are all outside the currently accessed array. As these locations cannot be accessed concurrently with the locations of the currently accessed array, the three additional processors 105 do not control the write enable means.
  • the processors 105 are otherwise similar to those of 104, as shown in Fig. 11. The outputs of these co ⁇ processors 105 are used only for the purpose of tiling the figure by selecting further update arrays for access.
  • a triangle composed of three line segments I, II and III is shown mapped to a first array. The test is performed with respect to the decision whether to address the next array to the left. Each of the pixels (0,0) and (0,4) is evaluated with respect to each of the three line segments.
  • the criterion for left access is that every half- space defined by the figure has one of the sample pixels of the left border set inside.
  • the inside sample pixel need not be the same for any of the half-spaces; but no one of the line segments can exclude both pixels.
  • the sample pixel (0,4) is found to be in the inside half-space;
  • the sample pixel (0,0) is found to be in the inside half-space;
  • both sample pixels are found to be in the inside half-space. Since for each half-space at least one sample pixel is inside, the figure is considered to be mapped to the next left update array. Controller 18 therefore issues an address request signal 94 specifying such array to addressing means 17, which provides the corresponding location address signal to memory bank 20.
  • a final constraint is imposed. As shown in Fig. 10, a triangle composed of directed line segments I, II and III terminates at a vertex mapped to pixel (1,1) of the array. However, upon applying the test described above for deciding whether to address the array lying horizontally to the left of the illustrated array, it is found that the test is met, although in fact the figure ought not to be drawn into the next array. To prevent erroneous addressing, a specification of a "bounding box" which encloses the figure being drawn (derived from the vertex information initially transmitted from processor 50) is stored in 115. Before requesting addressing f the next array, controller 18 compares the (x,y) position of the array with the bounding box position. When the result shows that the next array lies outside the bounding box, the test result is overridden.
  • the described operation of selecting a next update array is particularly advantageous in that the half- space evaluation for one of the sample pixels is made in the operation of writing selected pixels within the accessed framebuffer update array, while the other is easily made concurrently with such writing operation. This permits the test to be made quickly and simply.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Image Generation (AREA)

Abstract

Sont décrits un procédé et des moyens pour tracer une figure géométrique convexe dans une mémoire tampon d'images séquentiellement adressable sous forme d'une pluralité de réseaux de mise à jour d'origines déterminées qui tapissent la mémoire tampon d'images. Un réseau comprend des sites de stockage de pixels, chacun pouvant être spécifié par un décalage par rapport à l'origine du réseau. Les sites sont concurremment actualisables. Une figure est spécifiée sous forme d'un ensemble de lignes dirigées; les segments de ligne entre des intersections mutuelles englobent les limites de la figure; les segments parcourent les limites dans un seul sens. Pour un réseau d'actualisation, de concert avec chaque site de pixel, et concurremment pour chaque ligne dirigée, la latéralité du pixel est évaluée par rapport à la ligne afin d'en déduire un signal de discriminant de ligne à un bit. Pour chaque site, les signaux de discriminants de ligne sont combinés dans une porte ET afin d'en déduire un signal de discriminants de résultat. Une première valeur spécifiant la non-latéralité du pixel par rapport à la figure empêche l'écriture sur le site. On répète ce processus pour les autres réseaux afin de couvrir la figure à tracer.
EP19890901363 1987-12-18 1988-12-14 Procede de dessin dans un systeme de restitution de graphique Ceased EP0349630A1 (fr)

Applications Claiming Priority (2)

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US13477387A 1987-12-18 1987-12-18
US134773 1987-12-18

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EP0349630A1 true EP0349630A1 (fr) 1990-01-10

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EP (1) EP0349630A1 (fr)
JP (1) JPH02500142A (fr)
CA (1) CA1312683C (fr)
WO (1) WO1989006031A2 (fr)

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Publication number Priority date Publication date Assignee Title
US5251296A (en) * 1990-03-16 1993-10-05 Hewlett-Packard Company Methods and apparatus for generating arbitrarily addressed, arbitrarily shaped tiles in computer graphics systems
GB9009127D0 (en) * 1990-04-24 1990-06-20 Rediffusion Simulation Ltd Image generator
FR2666165B1 (fr) * 1990-08-23 1995-02-03 Sextant Avionique Procede de presentation d'images sur un ecran matriciel et systeme pour la mise en óoeuvre du procede.
WO1992012496A1 (fr) * 1991-01-09 1992-07-23 Du Pont Pixel Systems Limited Systeme informatique presentant des capacites de traitement d'images et de graphismes ameliorees
US5774133A (en) * 1991-01-09 1998-06-30 3Dlabs Ltd. Computer system with improved pixel processing capabilities
US5864512A (en) * 1996-04-12 1999-01-26 Intergraph Corporation High-speed video frame buffer using single port memory chips
US6278645B1 (en) 1997-04-11 2001-08-21 3Dlabs Inc., Ltd. High speed video frame buffer
JP2007535066A (ja) * 2004-04-29 2007-11-29 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 画像処理装置及び方法

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US4590465A (en) * 1982-02-18 1986-05-20 Henry Fuchs Graphics display system using logic-enhanced pixel memory cells
JPS61261779A (ja) * 1985-05-14 1986-11-19 インタ−ナショナル　ビジネス　マシ−ンズ・コ−ポレ−ション 二次曲線信号発生装置
JP2737898B2 (ja) * 1986-01-20 1998-04-08 富士通株式会社 ベクトル描画装置

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CA1312683C (fr) 1993-01-12
JPH02500142A (ja) 1990-01-18
WO1989006031A2 (fr) 1989-06-29
WO1989006031A3 (fr) 1989-07-13

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