Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04W—WIRELESS COMMUNICATION NETWORKS
  • H04W84/00—Network topologies
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04W—WIRELESS COMMUNICATION NETWORKS
  • H04W52/00—Power management, e.g. Transmission Power Control [TPC] or power classes
  • H04W52/02—Power saving arrangements
  • H04W52/0209—Power saving arrangements in terminal devices
  • H04W52/0212—Power saving arrangements in terminal devices managed by the network, e.g. network or access point is leader and terminal is follower
  • H04W52/0216—Power saving arrangements in terminal devices managed by the network, e.g. network or access point is leader and terminal is follower using a pre-established activity schedule, e.g. traffic indication frame
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04W—WIRELESS COMMUNICATION NETWORKS
  • H04W52/00—Power management, e.g. Transmission Power Control [TPC] or power classes
  • H04W52/02—Power saving arrangements
  • H04W52/0209—Power saving arrangements in terminal devices
  • H04W52/0212—Power saving arrangements in terminal devices managed by the network, e.g. network or access point is leader and terminal is follower
  • H04W52/0219—Power saving arrangements in terminal devices managed by the network, e.g. network or access point is leader and terminal is follower where the power saving management affects multiple terminals
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04W—WIRELESS COMMUNICATION NETWORKS
  • H04W88/00—Devices specially adapted for wireless communication networks, e.g. terminals, base stations or access point devices
  • H04W88/02—Terminal devices
  • H04W88/022—Selective call receivers
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
  • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
  • Y02D30/00—Reducing energy consumption in communication networks
  • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Definitions

• This invention relates generally to battery saving methods suitable for use with radio paging communications systems, and more particularly to radio paging communications systems which include selectively called paging receivers which have assignable battery saver duty cycles.
• Radio paging communications systems which include selectively called paging receivers having battery saving operation are in widespread use today. Both tone coded and digital coded battery saving schemes are in use, providing a variety of system battery saving performance characteristics. These current communications systems have generally provided adequate battery saving operation for paging receivers which utilize N-cell size and larger batteries. However, the small physical size and form factor of paging devices, such as wrist worn pager/watch devices, preclude the use of batteries larger than button cells. Thus while battery saving performance is adequate in systems with the paging receivers incorporating substantial batteries, these systems are inadequate for paging devices operating from extremely limited energy sources, such as button cell batteries.
• the proposed system would also be very inefficient and costly, as extremely large paging call and message geues would have to be provided in the terminal handling the paging calls. Such a solution is not only expensive, but is sure to create tremendous customer dissatisfaction. Clearly, short message qeues and rapid system response times must be maintained throughout the system as a whole. The problem is how to satisfy these needs, and balance them with the requirement of adequate battery life cycles for all paging receivers in the system, including those paging devices operating from extremely limited energy sources.
• FIGS. 1A - 1C comprise descriptive diagrams for a conventional battery saving system.
• FIGS. 2A - 2C comprise descriptive diagrams for a battery saving system employing a coded sync signal in accordance with the present invention.
• FIGS. 3A - 3D comprise descriptive diagrams for a battery saving system illustrating the operation of a paging receiver employing a coded sync signal in accordance with the present invention.
• FIG. 4 is a simplified electrical schematic diagram of the preferred embodiment of the present invention.
• FIG. 5 is a functional diagram of a microcomputer utilized in the preferred embodiment of the present invention.
• FIGS. 6A - 6C are flowcharts describing the operation of the preferred embodiment of the present invention.
• the POCSAG code format as shown in FIG. 1A, utilizes a digital code format and consists of batches of pages transmitted at regular intervals. Each batch is shown to consist of a sync word followed by the pages to be transmitted. As can be seen in FIG. IB, following the sync word, pages are transmitted in eight separate frames of address codes, namely 1-8, each of which includes two address segments. All pagers in the system are assigned to operate in one of the eight frames.
• FIG. 1C shows an example of how battery saving is accomplished in the POCSAG signalling system.
• a pager has been assigned to frame 6.
• the pager intermitantly provides power to the receiver section for a period of time long enough to detect the sync word, thereby continuously maintaining synchronization with the system.
• power is removed from the receiver until the frame to which the pager has been assigned occurs, in this case, frame 6.
• Power is again supplied to the receiver section for the duration of frame 6 during which time the pager is evaluating the received addresses to determine if a page has been sent to it. If a page was not received during the assigned frame, power is again removed from the receiver until the next sync word is to be transmitted.
• the POCSAG signalling system provides approximately a one to eight battery saving ratio, i.e. the time the receiver is on to the time the receiver is off.
• the POCSAG signalling system described thus provides a battery saving format which delivers the same effective battery saver duty cycle to all pagers in the system. Such a system does not provide a method of varying the duty cycle which is required to improve battery life, unless the entire system is changed.
• an improved battery saver system is shown in FIG. 2 which provides for a substantial improvement in battery life. While the basic format shown in FIG. 2A and 2B is similar to the prior art systems, the sync signal, or word, is no longer a single fixed word. Any number of distinct batches are created by including a coded sync word including a sync word and a sync I.D. at the end of the sync word as shown in FIG. 2C.
• the format of the sync I.D. can be of any number of forms, such as a four bit binary word ranging from 0 to 15. It will be appreciated by those skilled in the art that the number of sync I.D.'s provided in the system is a matter of choice, based upon the largest battery saving ratio contemplated for use in the system. Sync I.D. 's are assigned to a common sync word identifying each batch, and batches are transmitted in proper sequence.
• pagers there are N coded sync words describing N different batches to which pagers can be assigned.
• pagers can be assigned to a frame transmitted in one or more of the N different batches previously described, thereby tailoring the battery saver duty cycle to the type of pager in service.
• FIG. 3 illustrates the flexibility of the battery saving system described.
• pagers can be assigned to operate in one, or any combination of unique batches, or sync groups, defined by the coded sync words assigned. If a pager is assigned in a conventional manner to receive pages during frame six, and specifically only during sync group two, as shown in FIG. 3B, then the pager will only turn on one out of 128 possible frames, for a battery saver duty cycle of 1:128. If the pager is assigned to two of the possible sync groups as shown in FIG.
• the pager turns on for two of the possible 128 frames, for a battery saver duty cycle of.1:64. It is possible to assign a pager to all sync groups as shown in FIG. 3D with a resultant battery saver duty cycle of 1:8, which is the same as provided by the prior art POCSAG code format.
• the sync groups to which a pager will respond can be individually assigned and stored in the pager in the same manner as individual addresses are assigned to the pagers.
• the terminal normally used to queue pages in the correct frame in which they are to be transmitted, would also queue the pages by the sync groups to which the individual pagers are programmed to respond.
• Pagers providing different battery saver duty cycles can be mixed on the same system without interfering with each other.
• Pagers, such as miniature wrist worn pagers could be assigned to long battery saving duty cycles, while other pagers could be assigned to a shorter battery saving duty cycle, such as the prior art battery saving duty cycle.
• Figure 4 shows an electrical block diagram of a pager constructed in accordance with the present invention.
• the pager 20 includes an antenna 22 and a receiver portion 24 used to receive the transmitted coded sync signals and pages, or addresses, to which the pager will respond, in a manner well known to those skilled in the art.
• the demodulated signals corresponding to the transmitted coded sync signals and addresses are presented as a bit stream of binary information 25 at the output of receiver 24.
• bit pattern detector 28 control logic 32, and programmable timer 36 may be readily implemented using a microcomputer 26.
• the binary information bit stream 25 is applied to bit pattern detector 28 of microcomputer 26 where the signals are compared with the sync groups and address codes, which are stored in address memory 30, to maintain system synchronization, to determine the time to the next assigned sync group, and to detect pages directed to the pager.
• the sync group and address codes are assigned to the pager by programmiing them into address memory 30 in a manner well known to those skilled in the art.
• Address memory 30 may be reprogrammable, such as an EEPROM memory, thereby allowing sync groups or addresses to be readily implemented and changed.
• Control logic 32 of microcomputer 26 interfaces to address memory 30 and to bit pattern detector 28 controlling the comparison of received sync codes with those stored in address memory 30.
• a crystal oscillator 34 provides the clock necessary for control logic 32 portion of microcomputer 26.
• An output of crystal oscillator 34 also provides a reference clock for programmable timer 36 of microcomputer 26.
• Programmable timer 36 generates the interval signals which are supplied to bit pattern detector 28 and control logic 32, allowing control of when the bit detector correlates for either the sync group, or addresses in any transmitted batch.
• the time intervals generated by the programmable timer 36 are controlled by control logic 32 corresponding to the sync groups stored in address memory 30.
• Power to the receiver 24 is controlled in a manner well known to those skilled in the art by the battery saver circuit 38 which is controlled by battery saver signal 31 which is generated by control logic 32 in a manner corresponding to the battery saver operation defined by the sync codes stored in address memory 30.
• An output annunciator 40 is provided, which may be an LCD display in the case of a display pager, or a transducer in the case of a tone only pager, for alerting the user when a page has been received.
• FIG. 4 a pager has been described in FIG. 4 corresponding to the preferred embodiment of the present invention which provides assignable battery saver duty cycles.
• the pager is capable of operating in any combination of sync groups, and battery saver operation is defined by sync codes stored in the pager address memory, thereby insuring no operation of the battery saver circuit, except during those sync group time intervals to which the pager is programmed.
• FIG. 5 shows a functional block diagram of microcomputer 26 which contains the firmware for implemention of assignable battery saver duty cycles.
• the microcomputer is a Motorola 146805 type.
• the bit clock signal from crystal oscillator 34 is suppled to a timer control unit 80 containing a prescaler and a timer and counter.
• An output of crystal oscillator 32 is also connected to a central processing unit (CPU) 82 which contains the central processing unit control circuit, an arithmetic logic unit designated ALU, an accumulator, index register, condition code register, stack pointer, program counter high and program counter low modules.
• CPU central processing unit
• ALU arithmetic logic unit designated ALU
• accumulator index register
• condition code register condition code register
• stack pointer program counter high and program counter low modules.
• I/O registers 86 and 86 Also connected to the central processing unit are data directional input/output (I/O) registers 86 and 86 having a plurality of input/output lines. In particular, eight lines are shown for each of two input/output ports.
• an output line of register 84 is connected to line 31 to provide control of battery saver circuit 38.
• An input line of register 84 is connected to receive the binary .information bit stream signal 25 from receiver 24.
• An output line of register 86 is connected to output annunciator 40.
• Four I/O lines of register 86 are connected to address code memory 30.
• ROM read-only memory
• RAM random access memory
• the on-chip RAM permits microcomputer 26 to operate without an external RAM memory.
• the parallel input/output capability includes programmable pins indicating whether it is to be an input or an output.
• the timer/counter 80 is normally an eight bit counter with a programmable prescaler which can be used as an event counter to generate interrupt signals at certain software-selected events or can by used for keeping timing.
• FIG. 5 also shows the arrangement of major firmware modules stored in ROM 88.
• the choice and arrangement of this module is a function of the specific program of the embodiments of the present invention.
• the use of RAM 90 is pricipally to contain variables accessed during the program and as a scratch-pad storage.
• FIGs. 6A-C are flowcharts describing the operation of the battery saving circuit for the preferred embodiment of the present invention.
• the system is first initialized, as shown at block 302.
• the code plug, or address, memory is read, as shown at block 304, the result of which is utilized to initialize the timing, such as shown at block 306.
• a search for bit sync is initiated, as shown at block 308. If bit sync is not found, the search routine is re-initiated.
• bit timing is established, as shown at block 310, which in turn is effective to start a time-out timer for detecting a sync word, as shown at block 312, which is used to effect the search for a sync word, as shown at block 314. If a sync word is not detected, as shown at block 314, the search will continue for a predetermined time, as shown at block 316, after which the routine reverts back to search for bit sync, as shown at block 308.
• sync I.D. or sync group
• the sync group timer is correlated with the sync groups assigned to the unit. If the sync group is not one of the sync groups assigned to the unit as shown at block 355, the timer is set up for the time to the next assigned sync group as shown at block 356.
• sync group time-out occurs as shown at block 358, a search for the next assigned sync word is initiated, as shown at block 360.
• the sync word flag is read, as shown at block 362. If the sync word detect flag was set, as shown at block 364, it indicates a second miss of sync word detection has occured, as shown at block 370, and a search for bit sync is re-initiated, as shown at block 308 of FIG. 6A.
• sync word detect flag is not set, as shown at block 364, then this was the first time sync word was missed, and the sync word detect flag is set, as shown at block 366. Address, decoding then begins at point B, as shown in FIG 6C. Similarly, if the sync word was detected during the sync word search, as shown at block 360, address decoding begins at point B, as,shown in FIG 6C.
• the timer is set up for address decoding, as shown at block 338, in FIG. 6C.
• the timer times-out as shown at block 340, indicating the proper frame is present in which to search address
• the address search is begun, as shown at block 342.
• the group sync timer is set up for the next assigned group sync interval, as shown at block 356 of FIG. 6B.
• the function bits are decoded, as shown at block 344. If the function bit indicates no message was transmitted, indicating a tone only page, as shown at block 346, an alert signal is generated, as shown at block 348.
• the group sync timer is set up for the next group sync interval, as shown at block 356 of FIG. 6B.
• the received message is stored, as shown at block 350, and an alert is generated, as shown at block 352.
• the group sync timer is set up for the .next group sync interval, as shown at block 356 of FIG. 6B.

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• Engineering & Computer Science (AREA)
• Computer Networks & Wireless Communication (AREA)
• Signal Processing (AREA)
• Mobile Radio Communication Systems (AREA)

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• 1987
  • 1987-01-02 EP EP87900707A patent/EP0347410A1/de not_active Ceased
  • 1987-01-02 JP JP87500690A patent/JPH02500154A/ja active Pending
  • 1987-01-02 WO PCT/US1987/000005 patent/WO1988005248A1/en not_active Ceased
• 1988
  • 1988-09-02 KR KR1019880701064A patent/KR890700993A/ko not_active Withdrawn

Non-Patent Citations (1)

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