EP0335113A2 - Einchip-Cache-Speicher und Cache-Speichervorrichtung mit mehreren parallel geschalteten Einchip-Cache-Speichern - Google Patents

Einchip-Cache-Speicher und Cache-Speichervorrichtung mit mehreren parallel geschalteten Einchip-Cache-Speichern Download PDF

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Publication number
EP0335113A2
EP0335113A2 EP89103323A EP89103323A EP0335113A2 EP 0335113 A2 EP0335113 A2 EP 0335113A2 EP 89103323 A EP89103323 A EP 89103323A EP 89103323 A EP89103323 A EP 89103323A EP 0335113 A2 EP0335113 A2 EP 0335113A2
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Prior art keywords
signal
memory
address
data
processor
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English (en)
French (fr)
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EP0335113A3 (de
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Kunio Uchiyama
Hirokazu Aoki
Tadahiko Nishimukai
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Hitachi Ltd
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Hitachi Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/601—Reconfiguration of cache memory

Definitions

  • the present invention relates to cache memories, which are high speed temporary memories located between a processor and a larger and slower main memory.
  • the cache will temporarily store frequently used instructions and/or data from the main memory to increase the speed of processing, as disclosed in: A 40K Cache Memory Management Unit, James Cho et. al., 1986 IEEE International Solid State Circuits Conference, Digest of Technical Papers, pages 50 and 51: U.S. Patent 4,493,026 to Howard T.
  • a cache memory as a buffer memory, is well known as a technique to fill the gap between the machine cycle time of a micro­processor unit (MPU) and the slower operation cycle time of a main memory in a computer system to improve the performance.
  • MPU micro­processor unit
  • the cache memory can increase the speed of the machine cycle, by increasing memory speed for frequently used data.
  • the cache memory has been constituted by combining a plurality of general purpose RAM components and integrated circuits having a logic function. Recently, attempts have been made to constitute the cache memory by a single chip with the improvement in the integration density of the integrated circuits.
  • the number of transistors that can be integrated into the single chip cache memory is limited so that a memory capacity of a single chip cache memory is often insufficient. Therefore, it is desirable, according to the present invention, that the cache memory chip can operate singly as a cache memory apparatus, and further, when a plurality of such single chips are connected and parallel, an expanded cache memory apparatus having an increased memory capacity corresponding to the number of cache chips can be constituted.
  • the present invention employs construction such that a code portion of the address signal from the processor, such as a MPU, coincides with a code of only one of the plurality of cache memory devices connected and parallel, so that access of only one of the parallel single chip cache memory devices to the main memory is accomplished by reading out instructions and/or data from the main memory and copying into the cache memory the instruction and/or data in the case of a cache miss-hit.
  • the specified code portion of the address signal does not coincide with the code of the other cache memories, such access of other cache memories to the main memory are inhibited during a cache miss-hit.
  • the access to the main memory on a cache miss-hit is permitted only for the cache memory device having the code that coincides with the code portion of the address signal, and access to the main memory for the remainder for the cache memory devices during the miss-hit is inhibited. This is accomplished by providing a specific different code to each one of the cache memory devices connected in parallel.
  • FIG. 1 shows the overall construction of a single chip cache memory device 10.
  • this device 10 will be referred to as the "cache chip”.
  • This cache chip 10 is disposed between a processor 600 (Fig. 3) for processing instructions and/or data and a main memory 601 (Fig. 3) for storing the instructions and/or data, and operates individually as a cache memory apparatus, for example, having a 64 K-byte capacity.
  • the basic data width is 4 bytes (32 bits) and a 4-GB (gigabyte) main memory space is supported as the address space.
  • the main memory is divided into a large number of sectors, each sector is in turn divided into a large number of blocks and each block is divided into a plurality of words. Furthermore, each word is divided into a plurality of bytes.
  • a "column field", a "tag field, a "word field” and a "byte field”, respectively see Fig. 2.
  • the cache memory chip 10 shown in Fig. 1 includes:
  • the signal of the column field is supplied to the second memory 20 through the first transmission path 502 and line 505.
  • This column signal becomes a cache search input signal and the tag fields stored in memory 20 at the column position corresponding to the input column field become cache search output signals and are taken out from output lines 520, 522, 524, 526, of the second memory 20.
  • a validity bit signal representing whether or not each tag field signal is valid is taken out simultaneously from the output lines 520, 522, 524, 526.
  • the tag field signals thus taken out from the output lines 520, 522, 524, 526, are compared by the first detector 71-74 with the signal of the tag field supplied from the processor through the first signal transmission path 502 and the line 504 to judge hit and miss-hit.
  • the corresponding instructions and/or data stored in the first memory 30 are transmitted to the processor through the second signal transmission path 501, the transmission device 150 and the second terminal 400.
  • control signal CS e.g., chip select
  • the control circuit 90,110 is always set to the fixed condition that does not inhibit the read-out operation of the instructions and/or data from the main memory and the write-in operation of the read information into the first memory 30.
  • a specified code is allotted to each cache chip 10.
  • four cache chips may be connected in parallel as shown in Fig. 3, although any number of cache chips may be suitably connected according to the present invention.
  • two bits may be used to provide a code that specifically identifies each of the four chips.
  • chip number 1 would be identified by the code 00, chip number 2 identified by the code 01, chip number 3 identified by the code 10, and chip number 4 identified by the code 11.
  • This code would be a code portion within the field of the address signal, and is specifically shown as the de-code field, bits number 14 and 15 in Fig. 2.
  • more than four cache chips more than 2 bits would be required for the de-code field, and correspondingly with only two cache chips the de-code field could be of a one bit length.
  • the write-in operation of the information read-out from the main memory into the first memory 30 is only permitted to the cache chip whose specified code is coincident with the specified decode field bits (A15, A14) of the address supplied from the processor in the tag field. These operations are inhibited for the rest of the cache chips not exhibiting this coincidence. The reason is as follows:
  • cache "hit" only one of the plurality of cache chips 10 has a real cache hit and the information read out from its first memory (data array 30) is transferred to the processor 600.
  • the other cache chips that do not have a hit are inhibited from reading out their information from their first memory.
  • miss-hit In the case of cache "miss-hit", however, miss-hit can occur for all the cache chips 10. In this case it is not efficient if all these cache chips 10 execute the information read-out from the main memory and transmission of the read information to the processor 600 (not the present invention). Furthermore, storage of the information read out from the main memory in the first memory (data array 30) of all cache chips 10 makes parallel connection of a plurality of cache chips 10 meaningless.
  • the information read-out operation from the main memory and the write-in operation of the read information into the first memory 30 is permitted for only one chip among the plurality of cache chips 10 in response to the specified code bits A15, A14 of the address signal generated from the processor in the case of cache miss-hit, and these operations are inhibited to the rest of chips.
  • signal transmission of the transmission device 150 of the cache chip 10 having a cache hit is permitted in response to the specified code bits A15,14 described above, and the information read out from the first memory 30 is transferred to the processor 600.
  • Signal transmission of the transmission device 150 of the rest of cache chips 10 not involving in a cache hit is inhibited. Accordingly, the information transferred from the cache chip 10 exhibiting a cache hit to the processor 600 is not disturbed.
  • the instructions and/or data stored in the main memory 601 are often re-written by an I/O device or a processor [e. g., a processor different from the processor 600 also connected (not shown) to main memory 601]. lf such information re-write occurs, the data already stored in the cache memory and having the same address as the address of re-write information is invalidated.
  • the cache chip shown in Fig. 1 further includes, referring to the list of elements above: (12) second detector 81-84 for detecting the correlation (hit or miss-hit) between the information (tag field) stored in the second memory 20 and the external address signal (tag field) supplied from outside the cache chip 10 to the third terminal 411; wherein the control circuit 90, 110, to invalidate the information, resets the validation bit to 0 in the tag field stored in the second memory 20 in response to the information (MR/W) on terminal 413 indicating a write cycle and to the second detector 81-84 if the relation described is under the hit condition.
  • the other processor or I/O apparatus writes data to the main memory, the information MR/W on terminal 413 is negated.
  • a control signal generator 610 With a plurality of cache chips 10 connected in parallel to constitute a large memory capacity cache memory apparatus as shown in Fig. 3, a control signal generator 610 generates a control signal (CS) for selecting only one of the plurality of cache chips 10 in response to the specified decode bits A14 and A15 in the tag field of the address supplied from the processor.
  • the signal generator is a single decoder 610 located outside the cache chip 10.
  • Fig. 1 is a block diagram showing in detail the internal structure of one cache chip 10 of a plurality.
  • An address array 20 for storing the address tag information and a data array 30 for storing instructions and/or data are placed inside the cache chip 10.
  • the address array memory 20 consists of four sets of 2-port RAMS 21, 22, 23, 24 although any number may be employed, each being of 1,024 words by 19 bits type.
  • the data array memory 30 consists of four sets of RAMs 31, 32, 33, 34 corresponding in number to the number of sets of the address array 20, each being of 4,096 words by 32 bits type.
  • Each cache chip 10 constitutes alone a 4-way set associative system cache memory having the number of columns of 1,024 and a block length of 16 bytes by use of these two arrays 20 and 30.
  • a similar system is shown in USP 4,493,026 whose disclosure is incorporated herein and is in more detail.
  • the store method used in this cache chip is a store-through method which always updates the content of the main memory at the time
  • the cache chip 10 is connected to the processor through signal pins 400-406 on the left side and is further connected to the main memory bus and optionally another processor or l/0 device through signal pins 410-417 on the right side.
  • the address space supported by the cache chip is 4 GB (gigabyte; 32-bit address).
  • the upper order 30 bits are inputted from the processor side to the address signal pins (A31-A2) 401 and a byte control signal in the decoded form of the lower two bits A1, A0 is inputted from the pins (BC0-BC3) 405.
  • the signal inputted from the byte control signal pin 405 contains the information on the data length in addition to the information of the lower two bits A1, A0 of the address.
  • the upper order 30 bits of the address signal outputted from the processor are inputted to the address signal pins (A31-A2) 401 of the cache chip 10 and the value is held in an address hold register 40. At the same time, it flows to an internal address bus 502 of a 30-bit width in the chip. Each bit of the address is allotted to the field such as shown in Fig. 2. The bits from the thirteenth bit to the fourth bit are allotted as a column field.
  • the portion on the internal address bus 502 corresponding to the column field is inputted as an address search input to the input of the address array 20 through the line 505 and a plurality (four in this embodiment) of address tags stored in the column corresponding to this search input is read out through the output lines 520, 522, 524, 526.
  • the line 520 is an address tag read line from the first set 21 of the address array 20; line 522 is an address tag read line from the second set 22; line 524 is an address tag read line from the third set 23; and line 526 is an address tag read line from the fourth set 24.
  • Each address tag read line is of 19-bit width. The content of these 19 bits consists of the 18 bit address tag A31-A14 and 1-bit validity bit.
  • the address tag information read out from each set of address tags corresponding to a column match is inputted to each corresponding comparator 71, 72, 73, 74 and is compared with the value on the tag field (Fig. 2) from the 31st bit to the l4th bit on the internal address bus 502 inputted to each comparator.
  • a corresponding hit signal 581, 582, 583 or 584 is asserted and reported to a cache control circuit 90.
  • the state where any one of these hit signals 581, 582, 583, 584 is asserted corresponds to the state of cache hit for the cache chip and represents that a desired (according to the processor sent address) block (16 bytes) is stored in the data array 30.
  • the content of the data array 30 is read out by the information on the signal line 509 in parallel with the address array 20.
  • the values of the column field and word field shown in Fig. 2 ( among the address bits) flow to the signal line 509.
  • Four blocks, each having a 16-byte length, (corresponding to four words) are respectively inside four sets 31, 32, 33, 34 for each column field and 4 bytes (that is, one word) among the 16 bytes are selected by the word field.
  • Four x 4-byte data are read out from each set 31, 32, 33, 34.
  • the cache hit state is known at this time or in other words, if any one of the hit signals 581, 582, 583, 584 is asserted, the 4-byte data read out from the set of the corresponding data array 30 are selected by the selector 120 from that information; its value flows to the internal data bus 501 and the data are delivered from the data pin (D31-DO) 400 to the processor.
  • the cache chip fetches the 16-byte long block by four times fetch including the 4-byte word containing the necessary data from the main memory 601 in accordance with the address information held by the address hold register 40 and the data are inputted from the memory data signal pin 410 and flow to the internal data bus 501.
  • the requested 4 bytes are passed from the data signal pin 400 on the processor side to the processor and at the same time, are written into one of the four ways 31, 32, 33, 34 of the data array 30 through the data bus 511 and the selectors 550, 551, 552, 553.
  • the information for selecting the ways is obtained from the information stored in a replacement memory 60.
  • This replacement memory 60 is a 2-port RAM of 1,024 columns by 6 bits, and the information of each 6 bits contains the information determining in which way of the data array 30 the new block is to be stored at the time of block transfer.
  • the content of this replacement memory 60 is searched by the value of the column field that flows from the bus 508 simultaneously with the searching of the address array 20 and is replaced by a well known LRU (Least Recently Used) algorithm through a replacement logic 100.
  • a "+l" incrementer 130 is added to the lower two bits A3-A2 of the address hold register 40 and operates as a 2-­bit counter.
  • the word address inside the block of the address held by the address hold register 40 is updated during block transfer.
  • the incrementer 130 counts up by +l after the data for one word that is taken in and then shifts to the data reception of the next one word. Therefore, after the complete block transfer of the 4-word unit, the incrementer has counted up by a total of +3.
  • the address for the main memory is sent to the main memory through the signal pins (MA31-MA2) 411 terminal of the output buffer 250.
  • the register 590 is a buffer which stores once the values of the instruction and/or data when the processor writes them into main memory. Since this cache chip 10 employs the store-through method, the data inside the register 590 is written into the data array 30 through the bus 510 and one of the selectors 550, 551, 552 or 553 when the address array 20 is searched and hit or otherwise in accordance with replacement logic 100. The data is written into the main memory from the signal pin 410 through the path 592 and the output buffer 220.
  • the registers 40 and 590 operate as a store buffers when the data is written into the main memory.
  • the processor writes the data into the main memory through the cache chip 10
  • the processor writes the write address into the register 40 and the write data into the register 590. If the main memory is busy, then the processor shifts to the next operation by assuming the write operation into the main memory is complete. Thereafter, since the cache chip 10 outputs consecutively a memory bus request signal MBREQ 416, the data held by the register 590 is written into the main memory only after a memory bus acknowledge signal MBACK 417 is asserted when the main memory is no longer busy.
  • interface signal pins are disposed between the processor and the cache chip 10 on the left side of Fig. 1 and interface pins are disposed between the cache chip 10 and the main memory bus on the right side of the drawing.
  • Reference numeral 400 represents a data bus signal pin with the processor and 401 an address pin for receiving the upper order 30 bits of the address from the processor.
  • Symbol CS402 represents a chip select pin of the cache chip 10 and when "l" is applied to this signal pin CS402, the inside of the cache chip 10 operates completely and when "0" is applied, part of the operation inside the chip is inhibited as described before.
  • This signal pin CS402 makes it possible to expand the apparatus to include other parallel cache chips 10.
  • Symbol AS403 represents an address strobe signal pin. Logic “l” is inputted to this pin AS403 when the valid address is inputted to 401 and "0" is inputted at other times.
  • BC3-BC0 designate the byte positions of the write and read data.
  • RDY406 represents a pin which lets the processor know that the read or write cycle is finished, and the signal is outputted through the output buffer 210.
  • (MD31-MD0) 410 are bi-directional data bus pins of a 32-bit width.
  • (MA31-MA2) 411 are bi-directional memory address bus pins through which the upper order 30 bits of the memory address pass.
  • MAS412 is an address strobe signal pin of the memory bus, and "l" is applied to this signal pin when the valid memory address is passed on 411. When “l" is inputted to this signal pin, it represents that the valid address exists on the memory address pin 411.
  • (MBC3-MBCO) 414 are signal pins to designate the byte positions of the data.
  • MRDY415 is a pin to which a signal reporting that the bus cycle of the main memory is complete is inputted.
  • Output buffers 260, 280, 290 are respectively for pins 412, 413, 414.
  • MBREQ416 is a signal requesting the use of the main memory bus and when the cache chip 10 needs to use the main memory bus, "l" is outputted from this pin and requests the use to an external bus arbiter.
  • an external bus master outputs a permission signal to the cache chip 10, which is inputted from the input pin MBACK417. In this manner, the cache chip 10 can now use the main memory bus.
  • the signal pins 410, 411, 412, 413, 414, 415 are commonly connected to the corresponding signal pins of the device which can be a bus master on the main memory bus. Therefore, when the cache chip does not use the main memory bus, the output buffers 220, 250, 260, 280, 290 are turned off and the corresponding signal pins 410, 411, 412, 413 become the input pins while the signal pin 414 is under the high impedance state. When the cache chip 10 does not use the main memory bus as described above, the cache chip 10 watches the bus cycle on the main memory.
  • This bus watching function is a mechanism such that when the content of the main memory is re-written by other bus masters (that is, other processors or I/O apparatus), the content of the cache in the cache chip 10 is searched and if there exists any block having the same address, it is invalidated.
  • Invalidation of the cache described above is effected in the following way.
  • "l" is inputted from MAS412 and "O" (write) is inputted from the MR/W413
  • the address from MA31-MA2 411 is latched by the register 50.
  • This value flows on the cache invalidation address bus 503 and the value of the column field of the address (Fig. 2) is used as the search input address through the path 506 in order to read out the desired tag of the address array 20.
  • the four tags 521, 523, 525, 527 thus read out are compared with the value (the value on the path 507) of the tag field (Fig.
  • This cache chip 10 not only operates by itself as a cache memory apparatus of a 1,024 columns by 4 sets associative system by fixing the CS402 input pin to "l" but its memory capacity can also be expanded easily with other like parallel cache chips by inputting the decoding result of part of the address information to the CS402 input pin.
  • Fig. 3 shows an example of the cache memory apparatus of a set associative system having 256 KB and 4,096 columns by 4 ways as a whole by connecting four cache chips 10.
  • the data bus 700 with the processor 600 is connected to the data pin 400 of each cache chip 10.
  • the address signal 701, address strobe signal 703, read/write request signal 704 and byte control signal 705 generated by the processor 600 are connected to the input pins 401, 403, 404 and 405 of each cache chip 10, respectively.
  • the output from RDY406 of each cache chip 10 is subjected to wired-OR and connected to the ready signal 706 of the processor 600.
  • the 15th and 14th bits of the address signal 701 generated from the processor 600 becomes the decode field (Fig. 2) and inputted to the 2-bit decoder 610 through a path 702, and its four decode outputs 707, 708, 709, 710 are inputted to the chip select pin CS402 of each cache chip.
  • the output of the output buffer 150 connected to the data pin 400 in Fig. 1 is ENABLE only for the cache chip 10 selected by the chip select signal CS402 and is under the high impedance state at other chips.
  • the output of the output buffer 210 connected to RDY406 is ENABLE only for the cache chip selected by the chip select pin CS402 and is under the high impedance state at other chips.
  • the data bus 725, address bus 724, address strobe signal 723, read/write signal 722, byte control signal 721 and ready signal 720 of the main memory bus are connected commonly to the corresponding pins 410, 411, 412, 413, 414 and 415 of each cache chip 10 respectively.
  • the bus request signal outputted from MBREQ416 of each cache chip 10 is sent separately to the bus arbiter of the main memory bus and a separate bus acknowledge signal is inputted to MBACK417 as the reply corresponding to it.
  • the signal 726 of the main memory bus is a group of a plurality of these signals.
  • FIG. 1 two state machines operating independently exist inside the cache control circuit 90.
  • FIG. 4 shows the two state machines inside the cache control circuit 90.
  • An access control circuit 900 controls cache access from the processor side and an invalidation control circuit 901 is for invalidating the entry of the cache, whenever necessary, by watching the address on the main memory bus.
  • the input signals to the access control circuit 900 are CS906 inputted from the chip select pin 402 of the cache chip 10, AS907 inputted from the address strobe pin 403, R/W908 inputted from the read/write pin 404 and the data acknowledge signal DTACK910 from the memory bus control circuit 110.
  • Another input signal is HIT903 obtained by the output of OR gate 902 of the hit signals 581, 582, 583, 584 of each way as the result of search of the address array 20 for the access from the processor.
  • Its output signals include various control signal groups 912 for controlling the cache, MREQ911 requesting the memory bus control circuit 110 to make access to the main memory, and RDY909 connected to the ready signal pin 406 through the output buffer 210.
  • Each input signal is inputted to the combination circuit 904 with the present state information to generate the output signal, and also generates the next state.
  • Reference numeral 905 represents a flip-flop group for holding the state.
  • This flip-flop group 905 holds the information corresponding to various states S0, S R , S Bl - S B4 , S Wl , S W2 of the later-appearing access control circuit 900 shown in Fig. 5.
  • One of the input signals of the invalidation control circuit 901 is an invalidation hit signal 914 "IHIT" for invalidation which is obtained by the output of OR gate sum 913 of the hit signals 585, 586, 587, 588 of each way as the result of search of the address array 20 by the address on the main memory bus.
  • Another input signal REF916 is the signal from the memory bus control circuit 110.
  • Another bus master executes the write-in of data to the main memory via the main memory bus, that is, when "l” is inputted from the address strobe signal pin MAS412 and "O" is inputted from the read/write signal pin MR/W413, "l” flows to this REF 916 and instructs the control circuit 901 (described later) to search the address array 20 for invalidation.
  • Reference numeral 918 represents a combination circuit and reference numeral 915 represents a flip-flop group for holding the state. This flip-flop group 915 holds the information corresponding to various states S O , S A , S1 of the later-­appearing invalidation control circuit 901 shown in Fig.
  • FIG. 6 shows the shift of the state of the access control circuit 900.
  • the memory control circuit 110 delivers "l” to DTACK910 and notifies it to the access control circuit 900. Accordingly, that data is stored in the data array 30 and at the same time, the data is also sent to the processor 600 and "l" is delivered to RDY909 to notify it.
  • the state shifts from S Bl to S B2 simultaneously with the reply of this DTACK910 and "l” is again delivered to MREQ911 in order to request the data of the four bytes of the second word in the block for the main memory to wait for the reply of DTACK910.
  • Fig. 6 shows the state shift diagram of the invalidation control circuit 901.
  • S O represents the initial state, where the address array 20 is searched by the address on the main memory bus and the result is reflected on the hit signal IHIT914 for invalidation.
  • the memory bus control circuit 110 delivers "l” to REF916 in response to these input signals and actuates the invalidation control circuit 901. Accordingly, the state shifts from S O to S A to judge IHIT914.
  • IHIT914 is "O" (in the case of miss-hit)
  • the access control circuit 900, the invalidation control circuit 901 and the memory bus control circuit 110 operate in the manner described above, and the access control circuit 900 remains in the initial state S O and the state shift is inhibited so long as the chip select signal CS402 is not asserted.
  • the other chips watch the address on the main memory bus and can make invalidation of the cache or can write the data of the store buffer in the chip into the main memory.
  • control signal generator selection circuit 1030 for generating a control signal (CS) for selecting any one of a plurality of cache chips 10 in response to the specified bits (A15, A14) of the address supplied from the processor is disposed inside each cache chip (10) (see Figs. 7 and 8).
  • Reference numeral 1020 (PLl-0) represents pins which is inputted by the position information of each cache chip 10 to be used when the signal pin 1010 instructs the structure consisting of a plurality of cache chips 10.
  • the values inputted from 1010 and 1020 are inputted to the selection circuit 1030 together with the values of the 15th and 14th bits of the address bits from the processor (A15, A14) on line 1040 and the chip selection signal 906 (CS) is generated on the basis of this information.
  • This signal CS906 is the one that determines whether the cache chip 10 is to be operated or not in accordance with the access request from the processor.
  • the value on CS906 is “l” and the state is the one where the cache chip 10 is always selected.
  • the PLO input of the pin 1020 and A14 (14th bit) of the address bits are compared and when they are coincident, the value on CS906 is “l” and the cache chip 10 is selected.
  • the input to the pin 1010 is "lO” (4-chip structure mode)
  • the PLl and the PLO inputs of the pin 1020 and the address bits A15, A14 are compared, and when they are coincident, the value of CS906 becomes “l” and the cache chip 10 is selected.
  • Fig. 9 shows the internal logic of the selection circuit 1030 accomplishing the functions described above.
  • Reference numeral 1100 represents an input signal from pin 1010 and reference numeral 1110 represents an input signal from pin 1020.
  • 1120, 1130 and 1140 represent 2-bit input decoders; 1170, 1180, 1200, 1210, 1230 are AND gates; and 1150, 1160, 1190, 1370, 1380, 1240 and 1250 are OR gates.
  • the output signal 1260 of the decoder 1120 becomes “l” in the case of the single structure mode, the output signal 1270 is “l” in the case of the 2-chip structure mode and 1280 is “l” in the case of the 4-chip structure mode.
  • Fig. 8 shows a wiring diagram for expanding the memory capacity by connecting in parallel four cache chips 10, where the control signal generation means (610) shown in Fig. 3 can be omitted because each chip will have the select circuit 1030 of Fig. 7.

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EP19890103323 1988-02-26 1989-02-24 Einchip-Cache-Speicher und Cache-Speichervorrichtung mit mehreren parallel geschalteten Einchip-Cache-Speichern Withdrawn EP0335113A3 (de)

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JP41990/88 1988-02-26
JP63041990A JPH01217530A (ja) 1988-02-26 1988-02-26 キヤツシユメモリ

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EP0335113A2 true EP0335113A2 (de) 1989-10-04
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EP19890103323 Withdrawn EP0335113A3 (de) 1988-02-26 1989-02-24 Einchip-Cache-Speicher und Cache-Speichervorrichtung mit mehreren parallel geschalteten Einchip-Cache-Speichern

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DE4132833A1 (de) * 1990-10-05 1992-04-09 Digital Equipment Corp Hierarchischer schaltungsintegrierter cache-speicher
EP0712083A1 (de) * 1994-11-09 1996-05-15 Sony Electronics Inc. Speichersystem mit parallelgeschalteten Speichervorrichtungen
WO1997011464A1 (en) * 1995-09-20 1997-03-27 Micron Electronics, Inc. Pipelined burst multi-way associative cache memory device

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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4132833A1 (de) * 1990-10-05 1992-04-09 Digital Equipment Corp Hierarchischer schaltungsintegrierter cache-speicher
EP0712083A1 (de) * 1994-11-09 1996-05-15 Sony Electronics Inc. Speichersystem mit parallelgeschalteten Speichervorrichtungen
US6000013A (en) * 1994-11-09 1999-12-07 Sony Corporation Method and apparatus for connecting memory chips to form a cache memory by assigning each chip a unique identification characteristic
EP1109102A2 (de) * 1994-11-09 2001-06-20 Sony Electronics Inc. Speichersystem mit mehreren Speichereinheiten und Speicherzugriffsverfahren
KR100391727B1 (ko) * 1994-11-09 2003-11-01 소니 일렉트로닉스 인코포레이티드 메모리시스템및메모리억세싱방법
EP1109102A3 (de) * 1994-11-09 2008-10-01 Sony Electronics Inc. Speichersystem mit mehreren Speichereinheiten und Speicherzugriffsverfahren
WO1997011464A1 (en) * 1995-09-20 1997-03-27 Micron Electronics, Inc. Pipelined burst multi-way associative cache memory device
US6006310A (en) * 1995-09-20 1999-12-21 Micron Electronics, Inc. Single memory device that functions as a multi-way set associative cache memory

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EP0335113A3 (de) 1991-09-04
JPH01217530A (ja) 1989-08-31
KR890013650A (ko) 1989-09-25

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