EP0296627A2 - Verfahren zur Herstellung einer Halbleiteranordnung - Google Patents

Verfahren zur Herstellung einer Halbleiteranordnung Download PDF

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Publication number
EP0296627A2
EP0296627A2 EP88110143A EP88110143A EP0296627A2 EP 0296627 A2 EP0296627 A2 EP 0296627A2 EP 88110143 A EP88110143 A EP 88110143A EP 88110143 A EP88110143 A EP 88110143A EP 0296627 A2 EP0296627 A2 EP 0296627A2
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EP
European Patent Office
Prior art keywords
poly
layer
emitter
forming
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP88110143A
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English (en)
French (fr)
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EP0296627A3 (de
Inventor
Takeo c/o Patent Division K. K. Toshiba Maeda
Koji c/o Patent Division K. K. Toshiba Makita
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Toshiba Corp
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Toshiba Corp
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Publication date
Priority claimed from JP62-156443A external-priority patent/JPH012347A/ja
Priority claimed from JP21666687A external-priority patent/JPS6459849A/ja
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of EP0296627A2 publication Critical patent/EP0296627A2/de
Publication of EP0296627A3 publication Critical patent/EP0296627A3/de
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology

Definitions

  • the present invention relates to a method for manu­facturing a semiconductor device having bipolar and MOS transistors on one semiconductor substrate.
  • an internal base region of the bipolar transistor is formed at the same step as a channel ion implantation step for the MOS transistor and, subsequent to forming the gate electrode of the MOS transistor, an external base region of the bipolar transistor is formed simultaneously with the formation of the source and drain regions of the P-­channel MOS transistor.
  • a gate oxide film As a thin one in the formation of microminiaturized MOS transistors.
  • an ion implantation cannot be carried out subsequent to forming the gate oxide film. Since, therefore, a dummy gate oxide film is formed prior to the channel ion implantation step and then that channel ion implantation is carried out, a gate oxide film needs to be formed after the removal of the dummy gate film.
  • the internal base width Upon implan­tation of ions into the internal base in the same way as the conventional step, the internal base width will be made broader due to the OED (oxidation enhanced diffu­sion), so that the characteristics of bipolar tran­sistors are largely deteriorated.
  • various processings can be per­formed, such as a ramp-up step done from room tem­perature, a purging step done with H2 and a step for introducing a H2 carrier gas, or a step for removing natural oxide at a place within the deposition device, at the time of forming a poly-Si deposition layer.
  • a method for manufacturing a semiconductor device comprises the steps of implanting impurity ions in a MOS transistor formation area of a semiconductor substrate; forming a gate electrode over the MOS transistor formation area, forming source and drain regions of the MOS transistor by implanting impurity ions into the surface portion of the semiconductor structure with the gate electrode used as a mask; forming an external base region by implanting impurity ions in a bipolar transistor formation area; forming an internal base region, connected to the exter­nal base region, by implanting impurity ions into the bipolar transistor formation area; depositing an insu­lating interlayer on the whole surface of the semicon­ductor structure; forming into the insulating interlayer an opening reaching the surface of the internal base region; subsequent to depositing a poly-Si layer on the whole surface of the resultant structure, leaving some poly-Si layer at least near the aforementioned opening; and forming an emitter region and emitter electrode of the bipolar transistor by implanting impur
  • the internal base region of the bipolar transistor is formed subsequent to forming the MOS transistor.
  • N type epitaxial layer 14 containing about 2 x 1016/cm3 of phosphorus (P) as an impurity is formed by an epitaxial growth method on the surface of the resultant structure at which time layer 14 of, for example, 1.2 ⁇ m in thickness is formed at, for example, 1130°C - Fig. 1B.
  • a P type epitaxial layer may be grown on the surface in place of N type epitaxial layer 14. In this case, the P type epitaxial layer containing about 2 x 1015/cm3 of B as an impurity is formed on that surface.
  • a mask, not shown, for ion implantation is formed with the use of a photoetching method and, with the use of the mask, P ions are implanted in aforementioned N type epitaxial layer 14 at an acceleration energy of 160 KeV and a dose of 5 x 1012/cm2 with the use of the mask to selectively form N well region 15. Then B ions are implanted at an acceleration energy of 100 KeV and dose of 6 x 1012/cm2 with the use of another mask for ion implantation of selectively form P well region 16 - Fig. 1C. In this case, P well region 16 may be formed, followed by the formation of N well region 15. At the aforementioned step, during the growth of the P type epitaxial layer, P ions for example are implanted to form an N well region over the collector region.
  • dummy gate oxide film 19 has wholly been removed by NH4F, about 150 ⁇ -thick gate oxide film 28 is formed in an O2 + 10% HCl atmosphere at 900°C.
  • Poly-Si layer 24 is so deposited by a CVD (chemical vapor deposition) method on the surface of the resultant structure as to have a thickness of 1500 ⁇ . Then a phosphorus impurity is diffused into poly-Si layer 24 to provide a low resistance area - see Fig. 1E.
  • Impurity ions are implanted into N type epitaxial layer 14 over buried collector layer 13 with the use of BF2 to form external base region 27 for a bipolar transistor. Then P+ ions are implanted into the surface of the resultant struc­ture at an acceleration energy of 60 KeV and dose of 4 x 1013/cm2 with field oxide film 17 and the gate electrode as a mask to provide N ⁇ type source and drain regions 28 and 29 in the surface of P-well region 16 - Fig. 1F.
  • 2000 ⁇ -thick CVD SiO2 film 35 is deposited as an insulating interlayer on the whole surface of the resultant semiconductor structure and contact holes 36 and 37 are formed in CVD SiO2 film 35 in a manner to reach the surfaces of internal base region 34 and N+ type drain region 32, respectively.
  • a 500 ⁇ -thick poly-Si layer is deposited on the surface of the resultant structure and a patterning step is carried out to leave poly-Si layers 38 and 39 alone to be formed for an emitter electrode and high resistance element.
  • poly-Si layer 39 is covered with mask 40, such as a photoresist mask.
  • mask 40 such as a photoresist mask.
  • As ions are implanted into poly-Si layers 38 and 39 at an accelera­tion energy of 50 KeV and dose of 5 x 1015/cm2 to form N type emitter region 41 in internal base region 33 and, at the same time, poly-Si layer 38 is made low-ohmic to provide an emitter electrode for a bipolar transistor and poly-Si layer 39 is partially removed for low resistance to provide a drain line for an N-channel MOS transistor and a high resistance element 42 - Fig. 1H.
  • a ramp-­up step for gradually raising a prevalent temperature at the load time within the apparatus chamber from as low a level as possible while introducing a reducing gas, such as hydrogen or chlorine, or introducing a reducing gas, such as hydrogen, as a carrier gas.
  • a reducing gas such as hydrogen, or a radical gas con­taining F atoms
  • a high temperature atmosphere of above 600°C to prevent the formation of natural oxide.
  • insulating interlayer 43 comprising the CVD-SiO2 film and BPSG film
  • contact holes 44 and 45 are formed in insulating interplay 43 with contact hole 44 reaching the surface of poly-Si layer 38 and contact hole 45 reaching the surface of poly-Si layer 39.
  • contact hole 46 is formed in insulating interlayer 43 and underlying CVD SiO2 film 35, reaching the surface of source region 25 of P-channel MOS tran­sistor.
  • aluminum for interconnection is deposited by, for example, a vacuum evaporation method on the whole surface of the semiconductor structure and a pat­terning step is carried out to form aluminum wirings 47, 48 and 49 - Fig. 1I.
  • the internal base region of the bipolar transistor is not yet formed at the step of Fig. 1E upon forming gate oxide film 23. Since internal base region 34 is formed at the time of forming source and drain regions of N- and P-channel MOS transistors, it is possible to reduce the heat treatment time following the formation of the internal base region, so that the aforementioned depth xj can be made adequately shallower than in the conventional method. In the conventional technique, for example, it is only possible to obtain a bipolar transistor with its current amplification factor h FE , its emitter resistor and its cut-off frequency f T as 100, 1 k ⁇ and about 4 GHz, respectively.
  • a bipolar tran­sistor was able to be obtained whose current amplifica­tion factor h FE , emitter resistance and cut-off frequency f T were 200, 30 ⁇ and 10 HGz, respectively.
  • the gate oxide film is formed prior to forming the internal base region of the bipolar transis­tor and, subsequent to forming the internal base region, the internal base region is not exposed to a high temperature oxygen atmosphere. In this way, it is possible to prevent an oxidation-enhanced diffusion at the internal base region.
  • Figs. 2A to 2E show another embodiment based on the aforementioned concept and the common steps 1A to 1I will be explained below with some omitted.
  • dummy gate oxide film 19 of 100 ⁇ in thickness is formed at 800°C in an O2 atmosphere and a channel ion implan­tation step is conducted at NMOS and PMOS regions. That is, boron ions are implanted at an acceleration voltage of 20 KeV and dose of 4 x 1012 cm ⁇ 2 into channel for­mation region 21 for an NMOS transistor and boron and phosphorus ions are implanted, respectively, at the acceleration voltages of 20 KeV and 240 KeV and doses of 3 x 1012 cm ⁇ 2 and 2 x 1012 cm ⁇ 2 into channel formation region 20 for a PMOS transistor.
  • gate oxide film 23 of 150 ⁇ in thickness is formed at 900°C in an O2 +10% HCl atmosphere as shown in Fig. 2B.
  • BF2 ions are implanted into the surface portion of the semiconductor structure at an accelera­tion voltage of 30 KeV and dose of 5 x 1013 cm ⁇ 2 to obtain internal base 34.
  • P+ ions are implanted at an acceleration voltage of 320 KeV and dose of 1 x 1016 cm ⁇ 2 into the surface portion of the semiconductor structure to form deep N+ region 22.
  • First gate poly-Si layer 24 of 1500 ⁇ in thickness is deposited on the surface of the semiconductor struc­ture as shown in Fig. 2C.
  • Hole 36 for an emitter formation area is formed in the surface portion of the semiconductor device as shown in Fig. 2D in which case the hole is formed by an RIE (reactive ion etching) for poly-Si layer 24 and by NH4F for oxide film 23.
  • second gate poly-Si 54 of 500 ⁇ in thickness is deposited on the surface of the resultant structure and As ions are implanted into the surface portion of the semiconductor structure at an acceleration voltage of 50 KeV and dose of 5 x 1015 cm ⁇ 2, followed by an anneal step conducted for 10 seconds at 1000°C in a N2 atmosphere.
  • Reference numeral 41 represents an emitter region.
  • a CVD SiO2 film of 2000 ⁇ in thickness is deposited on the structure surface to provide side wall 30 for LLD type transistor formation.
  • As ions are implanted into the N channel transistor at an acceleration voltage of 60 KeV and dose of 5 x 1015 cm ⁇ 2 to form N+ layer 32, followed by a post-oxidation step performed for 30 minutes at 900°C in an O2 atmosphere.
  • An insulating interlayer (CVD SiO2) and BPSG film 35 are deposited, contact holes are formed and Al wiring layer 48 is formed on the semiconductor structure.
  • transistors with a current amplification factor h FE of 100, cut-off frequency ft of 4GHz and emitter resistance of 1 k ⁇ can be formed simultaneously with the formation of CMOS transistors.
  • the emitter electrode of the bipolar transistor may be formed of aluminum in place of poly-Si layer 38.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
EP88110143A 1987-06-25 1988-06-24 Verfahren zur Herstellung einer Halbleiteranordnung Ceased EP0296627A3 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP156443/87 1987-06-25
JP62-156443A JPH012347A (ja) 1987-06-25 半導体装置の製造方法
JP216666/87 1987-08-31
JP21666687A JPS6459849A (en) 1987-08-31 1987-08-31 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
EP0296627A2 true EP0296627A2 (de) 1988-12-28
EP0296627A3 EP0296627A3 (de) 1989-10-18

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EP88110143A Ceased EP0296627A3 (de) 1987-06-25 1988-06-24 Verfahren zur Herstellung einer Halbleiteranordnung

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US (1) US4931407A (de)
EP (1) EP0296627A3 (de)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0381071A2 (de) * 1989-02-03 1990-08-08 Texas Instruments Incorporated Verfahren zur Emitter-Bildung in einem BI-CMOS-Verfahren
EP0411947A1 (de) * 1989-08-03 1991-02-06 Motorola, Inc. BiCMOS-integrierte Schaltung, umfassend einen bipolaren Transistor mit einem flachen Graben und vertikalen Basiskontakten

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5247200A (en) * 1989-02-16 1993-09-21 Kabushiki Kaisha Toshiba MOSFET input type BiMOS IC device
JPH0349234A (ja) * 1989-07-17 1991-03-04 Fujitsu Ltd 半導体装置の製造方法
US5171702A (en) * 1989-07-21 1992-12-15 Texas Instruments Incorporated Method for forming a thick base oxide in a BiCMOS process
US5212397A (en) * 1990-08-13 1993-05-18 Motorola, Inc. BiCMOS device having an SOI substrate and process for making the same
US5175123A (en) * 1990-11-13 1992-12-29 Motorola, Inc. High-pressure polysilicon encapsulated localized oxidation of silicon
JP3307489B2 (ja) 1993-12-09 2002-07-24 三菱電機株式会社 半導体装置およびその製造方法
US5646057A (en) * 1994-07-25 1997-07-08 Taiwan Semiconductor Manufacturing Company Method for a MOS device manufacturing
US5885880A (en) * 1994-09-19 1999-03-23 Sony Corporation Bipolar transistor device and method for manufacturing the same
TW304301B (de) * 1994-12-01 1997-05-01 At & T Corp
JP3583228B2 (ja) 1996-06-07 2004-11-04 株式会社ルネサステクノロジ 半導体装置およびその製造方法
FR2756103B1 (fr) * 1996-11-19 1999-05-14 Sgs Thomson Microelectronics Fabrication de circuits integres bipolaires/cmos et d'un condensateur
FR2756100B1 (fr) 1996-11-19 1999-02-12 Sgs Thomson Microelectronics Transistor bipolaire a emetteur inhomogene dans un circuit integre bicmos
US6051459A (en) * 1997-02-21 2000-04-18 Advanced Micro Devices, Inc. Method of making N-channel and P-channel IGFETs using selective doping and activation for the N-channel gate
KR100198663B1 (ko) * 1997-03-17 1999-06-15 구본준 통신용 아이씨(ic) 제조 방법
US5968042A (en) * 1997-06-17 1999-10-19 Ernster; Joel A. Monopolar suction coagulator
US6300201B1 (en) * 2000-03-13 2001-10-09 Chartered Semiconductor Manufacturing Ltd. Method to form a high K dielectric gate insulator layer, a metal gate structure, and self-aligned channel regions, post source/drain formation
US9478534B2 (en) 2013-10-08 2016-10-25 Globalfoundries Inc. Lateral BiCMOS replacement metal gate

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58225663A (ja) * 1982-06-23 1983-12-27 Toshiba Corp 半導体装置の製造方法
US4637125A (en) * 1983-09-22 1987-01-20 Kabushiki Kaisha Toshiba Method for making a semiconductor integrated device including bipolar transistor and CMOS transistor
ATE41836T1 (de) * 1985-06-03 1989-04-15 Siemens Ag Verfahren zum gleichzeitigen herstellen von bipolaren und komplementaeren mos-transistoren auf einem gemeinsamen siliziumsubstrat.
EP0224712A3 (de) * 1985-11-01 1988-02-10 Texas Instruments Incorporated Integrierte Schaltung mit bipolaren und komplementären Metalloxid-Halbleitertransistoren
IT1188309B (it) * 1986-01-24 1988-01-07 Sgs Microelettrica Spa Procedimento per la fabbricazione di dispositivi elettronici integrati,in particolare transistori mos a canale p ad alta tensione
US4727046A (en) * 1986-07-16 1988-02-23 Fairchild Semiconductor Corporation Method of fabricating high performance BiCMOS structures having poly emitters and silicided bases
US4764482A (en) * 1986-11-21 1988-08-16 General Electric Company Method of fabricating an integrated circuit containing bipolar and MOS transistors

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
ELECTRONICS AND COMMUNICATIONS IN JAPAN, PART II, ELECTRONICS, vol. 69, no. 7, 1986, pages 1-7, Scripta Technica, Inc., Silver Spring, Maryland, US; K. SATO et al.: "A novel Bi-CMOS technology with upward and downward diffusion technique" *
IBM TECHNICAL DISCLOSURE BULLETIN, vol. 24, no. 11A, April 1982, pages 5571-5573, New York, US; A.W. CHANG et al.: "Bifet process and technology" *
IBM TECHNICAL DISCLOSURE BULLETIN, vol. 28, no. 9, February 1986, pages 3813-3815, Armonk, New York, US; "Bipolar device incorporated into CMOS technology" *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0381071A2 (de) * 1989-02-03 1990-08-08 Texas Instruments Incorporated Verfahren zur Emitter-Bildung in einem BI-CMOS-Verfahren
EP0381071A3 (de) * 1989-02-03 1990-11-22 Texas Instruments Incorporated Verfahren zur Emitter-Bildung in einem BI-CMOS-Verfahren
EP0411947A1 (de) * 1989-08-03 1991-02-06 Motorola, Inc. BiCMOS-integrierte Schaltung, umfassend einen bipolaren Transistor mit einem flachen Graben und vertikalen Basiskontakten

Also Published As

Publication number Publication date
US4931407A (en) 1990-06-05
EP0296627A3 (de) 1989-10-18

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