EP0296015A1 - Prüfanordnung für die Leistungslinienimpedanz und deren Anwendung für Zündtester von pyrotechnischen Mitteln - Google Patents

Prüfanordnung für die Leistungslinienimpedanz und deren Anwendung für Zündtester von pyrotechnischen Mitteln Download PDF

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Publication number
EP0296015A1
EP0296015A1 EP88401366A EP88401366A EP0296015A1 EP 0296015 A1 EP0296015 A1 EP 0296015A1 EP 88401366 A EP88401366 A EP 88401366A EP 88401366 A EP88401366 A EP 88401366A EP 0296015 A1 EP0296015 A1 EP 0296015A1
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EP
European Patent Office
Prior art keywords
current
test
circuit
power line
power
Prior art date
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Granted
Application number
EP88401366A
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English (en)
French (fr)
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EP0296015B1 (de
Inventor
Jean-Jacques Maurice Derksema
Pierre Fernand Coutin
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R Alkan et Cie
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R Alkan et Cie
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Application filed by R Alkan et Cie filed Critical R Alkan et Cie
Publication of EP0296015A1 publication Critical patent/EP0296015A1/de
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    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F42—AMMUNITION; BLASTING
    • F42D—BLASTING
    • F42D1/00—Blasting methods or apparatus, e.g. loading or tamping
    • F42D1/04—Arrangements for ignition
    • F42D1/045—Arrangements for electric ignition
    • F42D1/05—Electric circuits for blasting
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F42—AMMUNITION; BLASTING
    • F42C—AMMUNITION FUZES; ARMING OR SAFETY MEANS THEREFOR
    • F42C21/00—Checking fuzes; Testing fuzes

Definitions

  • the invention relates to a device for testing the impedance of a power line and its application to testing primers of pyrotechnic means with electric ignition.
  • this defect can have serious consequences and it is advisable to ensure beforehand that the impedance of the power line does not exceed a predetermined value and, correlatively, that its electrical continuity is well ensured.
  • EP-A-0061 860 describes an apparatus and a method for testing a detonating module, the firing of which is ensured by supplying it with an alternating current of given intensity via a transformer.
  • the test current must also be alternating and of sufficient intensity to allow precise measurement of the impedance of the detonating module.
  • a test under an alternating current of given frequency and constant amplitude would require an electrical power source of excessive capacity and size for a device. reil supposed to be portable.
  • the apparatus therefore includes a capacitor which, when testing a detonating module, is preloaded to a predetermined voltage. The discharge of the capacitor generates between the terminals of the transformer primary a voltage peak which is representative of the impedance of the detonating module.
  • Such a primer comprises in known manner the assembly of an electrical charge, that is to say a heating resistor, and a small pyrotechnic pellet capable of detonating in the event of sufficient heating. It is noted that excessive heating, but less than the minimum heating causing the detonation, can gradually create a kind of chemical fatigue of the pellet, which then introduces dri ves of its detonation characteristics relative to those it initially had. Such deterioration is hereinafter called "phlegmatization”.
  • French patent application No. 87 02923 filed on March 4, 1987 by the Applicant describes a device and a method for the selective firing of cartridges for aircraft or other apparatus.
  • This device includes modular chargers each containing several cartridges and electronic circuits ensuring the management of cartridge loading and the selective distribution of firing orders to the primers of the different cartridges.
  • these circuits construct firing tables containing only the addresses of the cartridges whose firing line comprising a power stage and a primer is correct. Each firing line must therefore have been tested during the initialization of the device and / or prior to the firing order of the cartridge.
  • FIG. 1 shows a simplified electrical circuit comprising a start symbolized by a load resistance Rc, a power stage T2 consisting of two transistors mounted in Darlington circuit between a current supply source SC and the load Rc, and a switching tranistor T1 allowing the selection of the firing line from the electronic circuits of the aforementioned selective firing device.
  • the base of transistor T1 is attacked via a resistor Rb1, its emitter is connected to ground via a resistor Re and its collector is connected to the base of the Darlington circuit T2 via of a resistance Rb2.
  • the impedance of the firing line can be determined by measuring the voltage Vm at its terminals when a direct test current Im is injected into it by the current source SC.
  • Vm 2Vbe + Vce1 + Rb2Ib2 + ReIe (input circuit)
  • Im being the intensity at the source SC:
  • Im ( ⁇ T2 + 1)
  • Ib2
  • Ic Im - Ib2 (4)
  • Ie Ib1 _ Ib2 (e)
  • ⁇ T2 being the current gain of the Darlington circuit.
  • Vm (input) 2Vbe + Vcelsat + Rb2Ib2 + Re (Ib1 + Ib2)
  • Vm (output) Vce2sat + RccIc, hence: (7)
  • Rcc being the value of the load resistance which, for a given current Ic, brings the transistor T2 to saturation.
  • the minimum current which must pass through a primer of the aforementioned type to ensure its ignition is 3A. If the available electrical voltage is 24V, we see that a firing channel can only be declared operational if the value of the firing line impedance is at most equal to 8 ⁇ .
  • the invention aims to provide a device for testing a power line which overcomes this difficulty.
  • a device for testing the direct current of the impedance of at least one power line comprising an electrical load connected to a power stage capable of supplying it with a high nominal direct current, characterized in that it includes: constant current generating means able to circulate in said line a direct test current of low value compared to the nominal current, an electrical dipole connected in said power line and capable of generating a constant offset voltage bringing the power stage to saturation when the load is traversed by the direct test current, means for measuring the voltage drop across the power line, and means for exploiting the result of said voltage measurement.
  • FIG. 1 is an electrical diagram of a power stage according to the state of the art
  • FIG. 2 is a diagram similar to that of FIG. 1 showing a power stage modified in accordance with the invention:
  • - Figure 3 is a graph illustrating the original effect obtained by means of the modified circuit of Figure 2;
  • - Figure 4A is a block diagram of a device for testing a plurality of selectively addressable power lines:
  • - Figure 4B is a view similar to Figure 4A of a test device according to an alternative embodiment;
  • - Figure 5 is a more detailed block diagram of the test circuit proper of Figures 4A and 4B.
  • the power stage 10 in FIG. 2 is similar to that in FIG. 1. It includes a Darlington T2 circuit made up of two PNP transistors.
  • the emitter of T2 is connected to a current supply source SC and its base is connected to the collector of a switching transistor T1 via a resistor Rb2.
  • the emitter of transistor T1 is connected to ground via a resistor Re and its base is attacked by an addressing circuit (not shown) through a resistor Rb1.
  • the collector of T2 is connected to the electrical load Rc via a power diode D.
  • the saturation of the circuit T2 is reached for a lower value R′cc of the load Rc: the output voltage of the power stage then has the shape represented by the curve V ′ m in dashed lines.
  • the minimum value of the offset voltage VD was 0.1 V.
  • this value must be greater to ensure that the measurement under low direct current takes place in the linear variation zone of Vm as a function of Rc.
  • the offset voltage introduced by the dipole interposed in the collector circuit of T2 remains substantially unchanged when this line is crossed by the high nominal current (at least 3 amperes) intended to ensure the ignition of the primer Rc.
  • a power diode is particularly well suited, since it generates an offset voltage of the order of 0.6 to 0.8 V for currents ranging from a few tens of milliamps to several amps.
  • the invention is not limited to this type of component and any other electrical dipole capable of generating a substantially constant offset voltage of the desired order of magnitude would be perfectly suitable.
  • diode D could be connected, not between the circuit T2 and the load Rc, but between the load Rc and the ground.
  • This second configuration has the advantage of requiring only a single diode for testing a certain number of power lines in parallel, by means of a single test circuit 20 as shown in FIG. 4A.
  • diode Di associated with each load Rci if, for example, the overall configuration of the circuits does not make it possible to have a good common ground.
  • the diode Di can be connected between the power stage and the load as shown in FIG. 4B, or between the load and the ground.
  • this configuration can also be justified if the manufacturing technology used (hybrid circuits for example) allows the power stage 10i and the corresponding diode Di to be integrated into the same substrate.
  • FIGS. 4A and 4B differ only in the position and the number of diodes used, they will be the subject of a common description.
  • the test circuit 20 comprising the current source SC, is connected in parallel to all the stages of power 10 l ... 10i ... 10n which should be tested. It will be assumed below that the power stages 10i, the charges Rci and the diodes Di have the same intrinsic characteristics in each power line Ll .... Li .... Ln and that the same current is circulated there. continuous test Im.
  • the test circuit 20 has an input E for test control and an output S for reading the response to the test.
  • the blocks 21 and 22 shown for the record respectively represent a circuit for generating the nominal direct current for supplying the loads Rci and a circuit for addressing the power stages 10 l ... 10i ... 10n .
  • the addressing circuit 22 selects the address of the input Ai of the power stage 10i which should be tested or supplied under the nominal current.
  • the test circuit 20 comprises the current source SC and a circuit for measuring the voltage Vm.
  • the test is triggered by applying an appropriate command to the input E and by selecting the address of the power stage forming part of the power line Ll .... Li .... Ln whose l should be measured. 'impedance. This is provided by measuring the voltage Vm between point P and ground.
  • the measured voltage Vm is compared with a predetermined threshold value and the result of this comparison may or may not validate the power line tested.
  • the circuits generating a threshold and comparison value can be part of the test circuit 20 or be external to it.
  • the output S then delivers a signal capable of taking one or the other of two logical states depending on the result of the comparison.
  • ⁇ Vce2sat is the variation of the saturation voltage of circuit T2 for the variation of current ⁇ Im
  • ⁇ VD is the variation of the offset voltage of diode D for the variation of current ⁇ Im.
  • ⁇ Vce2 and ⁇ VD are a function of the components used and will be determined once and for all.
  • the variation of the saturation voltage of the power transistor (T2) Vce2sat is 15 ⁇ 5 mV for a variation ⁇ Im of 15 mA, in the temperature range between -55 and + 100 ° C.
  • the variation of the forward voltage of the ⁇ VD diode in the same conditions is 15 mV ⁇ 5 mV.
  • FIG. 5 shows a test circuit by differential measurement applicable in particular to the testing of cartridge primers in the context of the device which is the subject of the above-mentioned French patent application No. 87 02923.
  • the test circuit 20 comprises at the input an optoelectronic isolation circuit 201 to which the test trigger commands are applied to its input E.
  • the output of the isolation circuit 201 attacks the trigger input of a first monostable circuit 202 having a time constant of 40 ⁇ s, an input of an AND gate 203 and the trigger input of a second monostable circuit 204 having a time constant of 65 ⁇ s.
  • the inverted output Q of the first monostable 202 attacks the second input of the AND gate 203 and its non-inverted output Q drives a first current source 205 generating a first direct measurement current of 35 mA, as well as an authorization input d '' an analog memory 206.
  • the output of the prote ET 203 drives a second current source 207 generating a second direct measurement current of 50 mA, as well as the authorization input of a measurement circuit 208.
  • the current sources 205 and 207 are connected in parallel to the different power stages of the lines to be tested (only one of which has been shown for the sake of simplicity) by means of a diode 214. Similarly, the generator circuit 21 firing current is con connected to these same power stages via a diode 215.
  • the diodes 214 and 215 together play the role of an OR gate.
  • the outputs of the analog memory 206 and of the measurement circuit 208 are applied to a measurement comparator 209 whose output is connected to a logic memory 210.
  • the clock input of the logic memory 210 is attacked by the output of a read circuit 211 itself controlled by the monostable circuit 204.
  • the result of the measurement present at the output Q of the logic memory 210 is transmitted to the output S of the test circuit 20 via an optoelectronic isolation circuit 212 and an adapter output circuit 213.
  • a test of the power line Li is triggered by selecting the input Ai of the power stage 10i and by applying a test command signal to the input E.
  • Cellui transmitted by the circuit d isolation 201 (photocoupler), causes the generation of a 40 ⁇ s pulse by the monostable circuit 202. This pulse controls the current source 205 which circulates a direct current of 35 mA in the power line Li. Simultaneously, this 40 ⁇ s pulse applied to analog memory 206 authorizes the latter to memorize the voltage developed at point P.
  • the Q output of the monostable circuit 202 changes to "0" and its Q output changes to "1".
  • the output of the AND gate 203 also changes to "1" and the current source 207 circulates a direct current of 50 mA in the power line Li.
  • the level "1" at the output of the AND gate 203 also allows the circuit 208 to measure the voltage at point P.
  • Comparator 209 compares to a predetermined threshold value the difference ⁇ Vm between the voltages generated at point P by the currents of 50 and 35 mA respectively or, which is equivalent, compares the output of the measuring circuit 208 at the sum of the threshold value and the memorized value present at the output of the analog memory 206.
  • ⁇ Vm is greater than the threshold value, that is to say if the impedance of the load Rci is greater than the predetermined admitted value, the output of the comparator takes the logic value "0". Otherwise, it takes the logical value "1". Alternatively, one can naturally adapt a reverse logic.
  • the monostable circuit 204 causes the emission of a pulse by the read circuit 211.
  • the logic state of the comparator 209 applied to the input D of the logic memory 20 is transferred to its output Q. This logic state is transmitted to the output S via the optoelectronic output circuit 212 and the adapter output circuit 213.
  • the output S of the test circuit 20 is in state “1" if the power line Li associated with the primer Rci is operational and in state "0" if the latter is defective.
  • the invention allows, with good precision, a low resistance measurement across a power stage, this by overcoming the dispersion (intrinsic and related to temperature) of the characteristics of the constituent components. the measurement line.
  • the measurement performed corresponds to the total impedance, line (L), transistor plus load (Rc). It would be possible, knowing the impedance of the line (cable L) without load and an approximate value of the dynamic impedances of the power transistor, to obtain a measurement of the load resistance with good accuracy.
  • the device described also makes it possible to use only one test circuit for any number of lines to be tested, which ensures a significant gain in components compared to a solution using a circuit. test per line. This results in better reliability of the device and a reduced cost.
  • the purpose of the test carried out by means of the device described may be to ensure that the impedance of the line is not less, but more than a predetermined value. If the load is supplied by a voltage source instead of a current source, the power line impedance test will then protect it or the source against overcurrents.

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Testing Relating To Insulation (AREA)
EP19880401366 1987-06-15 1988-06-06 Prüfanordnung für die Leistungslinienimpedanz und deren Anwendung für Zündtester von pyrotechnischen Mitteln Expired - Lifetime EP0296015B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR8708266 1987-06-15
FR8708266A FR2616548B1 (fr) 1987-06-15 1987-06-15 Dispositif de test de l'impedance d'une ligne de puissance et son application au test d'amorces de moyens pyrochniques

Publications (2)

Publication Number Publication Date
EP0296015A1 true EP0296015A1 (de) 1988-12-21
EP0296015B1 EP0296015B1 (de) 1992-01-29

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EP19880401366 Expired - Lifetime EP0296015B1 (de) 1987-06-15 1988-06-06 Prüfanordnung für die Leistungslinienimpedanz und deren Anwendung für Zündtester von pyrotechnischen Mitteln

Country Status (4)

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EP (1) EP0296015B1 (de)
DE (1) DE3868150D1 (de)
ES (1) ES2029893T3 (de)
FR (1) FR2616548B1 (de)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0611944A1 (de) * 1993-02-18 1994-08-24 Csir Testschaltung
WO2005005921A1 (en) * 2003-07-15 2005-01-20 Detnet South Africa (Pty) Ltd Detonator fuse status detection
CN103017608A (zh) * 2012-12-20 2013-04-03 北京电子工程总体研究所 激活电路测试仪
WO2022084338A1 (de) * 2020-10-19 2022-04-28 Hoff Juergen Zündvorrichtung

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2976485A (en) * 1959-03-30 1961-03-21 Bendix Corp Continuity testing device for explosive igniting circuits
FR2117345A5 (de) * 1970-12-04 1972-07-21 Rheinmetall Gmbh
EP0061860A1 (de) * 1981-03-27 1982-10-06 Aeci Limited Vorrichtung und Verfahren zum Testen von Sprengsystemen
FR2568408A1 (fr) * 1984-07-26 1986-01-31 Porsche Ag Dispositif pour la verification des fusibles

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2976485A (en) * 1959-03-30 1961-03-21 Bendix Corp Continuity testing device for explosive igniting circuits
FR2117345A5 (de) * 1970-12-04 1972-07-21 Rheinmetall Gmbh
EP0061860A1 (de) * 1981-03-27 1982-10-06 Aeci Limited Vorrichtung und Verfahren zum Testen von Sprengsystemen
FR2568408A1 (fr) * 1984-07-26 1986-01-31 Porsche Ag Dispositif pour la verification des fusibles

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0611944A1 (de) * 1993-02-18 1994-08-24 Csir Testschaltung
WO2005005921A1 (en) * 2003-07-15 2005-01-20 Detnet South Africa (Pty) Ltd Detonator fuse status detection
CN103017608A (zh) * 2012-12-20 2013-04-03 北京电子工程总体研究所 激活电路测试仪
CN103017608B (zh) * 2012-12-20 2015-05-06 北京电子工程总体研究所 激活电路测试仪
WO2022084338A1 (de) * 2020-10-19 2022-04-28 Hoff Juergen Zündvorrichtung

Also Published As

Publication number Publication date
FR2616548B1 (fr) 1989-12-01
DE3868150D1 (de) 1992-03-12
FR2616548A1 (fr) 1988-12-16
EP0296015B1 (de) 1992-01-29
ES2029893T3 (es) 1992-10-01

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