EP0292502A1 - Method and apparatus for a constant frequency clock source in phase with a variable frequency system clock. - Google Patents
Method and apparatus for a constant frequency clock source in phase with a variable frequency system clock.Info
- Publication number
- EP0292502A1 EP0292502A1 EP87901789A EP87901789A EP0292502A1 EP 0292502 A1 EP0292502 A1 EP 0292502A1 EP 87901789 A EP87901789 A EP 87901789A EP 87901789 A EP87901789 A EP 87901789A EP 0292502 A1 EP0292502 A1 EP 0292502A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- signals
- frequency
- system clock
- constant frequency
- controllable
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
-
- G—PHYSICS
- G04—HOROLOGY
- G04G—ELECTRONIC TIME-PIECES
- G04G3/00—Producing timing pulses
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/14—Time supervision arrangements, e.g. real time clock
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
- G06F7/68—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using pulse rate multipliers or dividers pulse rate multipliers or dividers per se
Definitions
- This invention relates generally to the apparatus for producing the timing signals in a data processing system and, more particularly, to data processing systems that have a system clock with a variable frequency and require a constant frequency clock source to control the operation of interval timers and related apparatus.
- a data processing system generally has a plurality of components that must cooperate in the processing of digital signal groups.
- An example of such a data processing system is shown in Figure 1.
- at least one central processing unit 10 (or 11), at least one input/output unit 13 (or 14) and a memory unit 15 are coupled by means of a system bus 19.
- a console unit 12 can be coupled to the central processing unit(s).
- the central processing unit(s) manipulates groups of logic signals representing data information according to control signals in the Form of groups of logic signals representing instructions. These instructions are typically components of software or firmware programs.
- the memory unit provides the principal mechanism for storage of data signal groups and program signal groups to be manipulated by the central processing unit(s).
- the console unit can provide for the initialization of the data processing system and, during the operation of the data processing system, can function as a terminal.
- the console unit is frequently used for the control of diagnostic procedures for the data processing system.
- the input/output unit 13 provides the interface for exchange of signal groups between the data processing system and mass memory storage units, terminal devices, communication devices, and other peripheral devices requiring interaction with the central processing unit(s).
- the components of the data processing system must be coordinated in order to provide consistent performance. This coordination is typically performed by a timing or clocking mechanism.
- individual components of the data processing system can have associated clocking mechanisms.
- interface units are required to insure the integrity of the data signal groupsduring the exchange of signal groups between the individual components.
- the entire data processing system can have a single system clock by which means the flow of data signal groups throughout the entire data processing system can be coordinated.
- variable frequency signals can permit the rate of processing of the logic signal groups to be increased, as the frequency of the system clock is increased, or to be decreased, as the frequency of the system clock is decreased.
- This functionality can be particularly advantageous in the detection of system malfunctions because the system can be operated at a rate that can permit the detailed analysis of particular processing functions.
- This functionality can also be used to increase the power of the entire data processing system when a component or unit limiting the frequency of the system can be replaced with an improved component or unit that can operate at an increased frequency.
- interval timer In addition to the system clock, data processing systems typically include an interval timer.
- the function of the interval timer is to provide timing signals that are fixed in frequency and can therefore be used to provide real time measurements for purposes such as maintaining a calendar, measuring time for project execution, supplying billing information, etc.
- the interval timer must be driven by a constant frequency clock source even though the system clock can have a variable frequency.
- the timing signals used by the interval clock must be maintained in phase synchronization with the signals of the system clock.
- the output signals of the first oscillator can be processed in a predetermined manner to provide the constant frequency signal source, while the output signals from the second oscillator can be processed in a controllable manner to provide the variable frequency signals. This technique suffers from the difficulty in synchronizing the two sets of signals and in insuring that the two sets of signals are in phase.
- variable frequency signals are produced by dividing the output signal of the voltage controlled oscillator in a controllable divider circuit before applying the feedback signal to the phase comparator unit of the phase locked loop unit.
- the input signal to the controllable divider is the signal used as the basis for the the system clock signals.
- the input signal to the phase comparator unit will be at the same frequency as the signal from the reference oscillator.
- Comparison circuits compare the count in the controllable divider circuit with calculated fractions of a stored integer, the stored integer representing the system clock frequency. The output signals, resulting when any one of these calculated fractions of the system clock frequency in the comparison circuit are equal to the count from the controllable divider circuits, provide a constant frequency signal, the frequency being a multiple of the reference frequency.
- This constant frequency signal can be used to control an interval timer or related apparatus.
- the distribution network standardizing the delay in the distribution of the system clock signals, is placed in the feedback portion of the phase locked loop, thereby assuring that two sets of signals are in phase.
- FIG. 1 is a block diagram of a typical data processing system.
- FIG. 2 is a block diagram of a typical data processing system illustrating the use of a system clock to synchronize the operation of the system.
- FIG. 3 is a block diagram of a device for producing variable frequency system clock signals that can control the operation of a data processing unit or system and can provide constant frequency signals.
- FIG. 4 is a block diagram of the device for producing variable and constant frequency signals for use in a data processing system using a phase locked loop circuit.
- FIG. 5 is a block diagram of the clocking device that can provide controllable frequency signals for synchronizing the operation of the data processing unit, while providing constant frequency signals in phase with the controllable frequency system clock signals.
- the system clock can be physically located in any portion of the data processing unit although the usual location of the system clock is associated with one of the central processing units.
- the signals from the system clock are distributed to the various components of the data processing system.
- the variable length of the cables coupling the system clock can provide a delay that can result in signal processing errors.
- a signal distribution network 21 is placed in each signal path, including the path to the components of the unit in which the system clock is located, so that a constant delay is found to each unit. Because the distance that a signal travels from the system clock can be different for each unit of the data processing system, and because the interfacing circuits receiving the system clock signals can be different for each unit, each distribution network
- a reference oscillator provides a signal having a fixed frequency.
- the signal from the reference oscillator 31 is applied to controllable frequency unit 33.
- Controllable frequency unit 33 also receives control signals that are used to determine the frequency of the output signals of controllable frequency unit 33.
- the constant frequency clock source 32 applies the signals necessary to drive the interval timer circuit of the data processing system and related apparatus, while the signals to the distribution networks 21 provide the clocking signals coordinating the operation of the component units of the data processing system.
- the frequency control network includes a phase locked loop circuit.
- the output signal from the reference oscillator 31 is applied to a first input terminal of a phase comparator unit 41.
- the output signal of the phase comparator unit 41 has a voltage level determined by a difference in phase between the two input signals applied to the phase comparator unit.
- This output signal is applied to the input terminal of a voltage controlled oscillator 42, the amplitude of this input signal determining the frequency of the signal at the output terminal of the voltage controlled oscillator 42.
- the output signal of the voltage controlled oscillator is applied to a divider circuit 43 that divides the frequency of the output signal of the voltage controlled oscillator by a fixed amount.
- the output signal of the divider circuit 43 is applied to controllable divider circuit 44.
- the controllable divider circuit 44 receives control signals and these control signals determine the amount by which the frequency of the signal between the input and the output terminals of the controllable divider circuit is reduced.
- the controllable divider circuit can be implemented by a count down counter in which the number by which the input frequency is to be divided is determined by a number, (n-1) where n is the divisor, and is entered in the count down counter (controllable divider circuit 44).
- the output signal of the controllable divider circuit is applied to a second input terminal of the phase comparator unit 41.
- output signal of the voltage controlled oscillator will have a frequency that is the frequency of the reference oscillator multiplied by the divisor of the divider circuit 43, this quantity then multiplied by the divisor of controllable divider circuit 44.
- the output signal of divider circuit 43 is applied to the distribution network
- the frequency control network 33 is shown along with the components of the constant frequency clock source 32.
- the output signal of the divider network 43 is applied to the distribution network units 21 (xx) .
- An output signal from one of the distribution network units 21 (xx) is used as the input signal to the controllable divider circuit 44.
- Count signals, indicative of the count in the controllable divider circuit are applied to an input terminal of a divide-by-K unit 52, to an input terminal of a divide-by-K/(K-2) unit 53, to an input terminal of a divide-by-K/(K-1) unit 54 and to intervening divider units not explicitly shown in the Figure.
- the output terminal of the divider unit 51 is coupled to a first input terminal of comparator 56, the output terminal of divider unit 52 is coupled to a first input terminal of comparator 57, the output terminal of divider unit 53 is coupled to a first input terminal of comparator 58 and the output terminal of the divider unit 54 is coupled to a first terminal of comparator circuit 59.
- the second input terminals of comparator 56, comparator 57, comparator 58 and comparator 59 are coupled to terminals designating the current count in the controllable divider circuit 44.
- the output terminals of comparator 56, comparator 57, comparator 58, and comparator 59 are each coupled to an input terminal of logic "OR" gate 55.
- the reference oscillator provides a signal with a known and constant frequency.
- the reference oscillator can have a frequency of 250 kHz.
- the configuration of the controllable counter i.e. by controlling the count placed in the count down counter, the frequency of the system clock signals can be varied.
- n-1 When the integer (n-1) is entered in the controllable divider circuit, this value is also entered in the divider circuits 52 through 54.
- the value of n In each divider unit, the value of n is divided by an amount determined by the number K of divider units to result in K approximately equal intervals. (The approximately equal intervals result when the quantity n-1 is not exactly divisible by K.)
- comparator 57 When the count in the controllable divider circuit 44, reaches 20, then comparator 57 will provide an output signal to logic “OR” gate 55 and this signal will be applied to the output terminal of the logic “OR” gate. Similarly, comparator 58 will apply a signal to logic “OR” when the count in the controllable divider circuit reaches 40 and comparator circuit 59 will apply a signal to logic "OR” gate 55 when the count reaches 60. Of course, comparator circuit 56 will apply a signal when the count in the controllable divider circuit 44 reaches 0 (80). Thus, it can be seen that the output terminal of logic OR gate 55 will have signals applied thereto that are K times the frequency of the reference oscillator 31.
- the frequency of the constant frequency clock source will be 1 mHz.
- the individual intervals can vary slightly. However, at the end of the K th interval, the intervals will be synchronized, i.e. no accumulative error will have resulted with the recycling of the controllable divider circuit 44 because the comparator circuit 56 has the same value, i.e. 0, as does the controllable divider circuit.
- the positioning of the distribution network and the associated time delay is needed to maintain the synchronization of the phase between the constant frequency clock source and the system clock signals.
- phase-locked loop is not complete and that other elements such as a low pass filter can be incorporated in the loop.
- divider circuit 43 is not necessary for the operation of the invention, but can be incorporated for convenience in the implementation of the timing circuit.
- the foregoing description is included to illustrate the operation of the preferred embodiment and is not meant to limit the scope of the invention.
- the sco pe o f the inven ti on is to be limited only by the following claims. From the foregoing description, many variations will be apparent to those skilled in the art that would yet be encompassed by the spirit and scope of the invention.
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Computing Systems (AREA)
- Mathematical Optimization (AREA)
- Mathematical Physics (AREA)
- Pure & Applied Mathematics (AREA)
- Mathematical Analysis (AREA)
- Computational Mathematics (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
Un appareil à horloge produit des signaux d'horloge à système de fréquence variable pour la synchronisation du fonctionnement d'appareils de traitement des données et des signaux de synchronisation à fréquence constante, en phase avec les signaux d'horloge du système, permettant de commander le fonctionnement d'un rythmeur d'appareils associés. Les signaux d'horloge à système de fréquence variable sont produits en introduisant dans la boucle (33) verrouillée en phase un réseau (44) diviseur contrôlable. Les signaux d'entrée reçus par le réseau (44) diviseur contrôlable sont distribués comme signaux d'horloge du système. La fréquence constante est obtenue en distribuant des signaux de comptage provenant du réseau (44) diviseur contrôlable du circuit (33) à boucle verrouillée en phase à une pluralité de circuits de comparateurs (56, 59); les signaux de sortie du comparateur produisent une pluralité d'intervalles de synchronisation qui permettent d'obtenir des signaux à fréquence constante. Les intervalles de synchronisation sont déterminés par les signaux de contrôle (n-1) qui sont appliqués aux réseaux (44) diviseurs contrôlables et à une pluralité de circuits diviseurs (52, 54) associés au circuit comparateur (56, 59). Le signal de contrôle (n-1) est divisé par le circuit diviseur (52, 54) et la valeur obtenue est introduite dans le circuit comparateur (56, 59), ou la valeur est comparée à la valeur comptée fournie par le réseau diviseur contrôlable (44). Un réseau de distribution (21), utilisé pour produire une temporisation dans la distribution des signaux d'horloge du système, qui permet la synchronisation d'éléments du système de traitement des données, est placé dans la boucle à verrouillage en phase (33) afin de garantir que les signaux à fréquence constante et les signaux d'horloge du système sont en phase.A clock apparatus generates variable frequency system clock signals for synchronizing the operation of data processing apparatuses and constant frequency synchronizing signals, in phase with the system clock signals, for controlling the operation of a rhythm machine of associated devices. The variable frequency system clock signals are produced by feeding a controllable divider network (44) into the phase locked loop (33). Input signals received by the controllable divider network (44) are distributed as system clock signals. The constant frequency is obtained by distributing count signals from the controllable divider network (44) of the phase locked loop circuit (33) to a plurality of comparator circuits (56, 59); the comparator output signals produce a plurality of synchronization intervals which provide constant frequency signals. The synchronization intervals are determined by the control signals (n-1) which are applied to the controllable divider networks (44) and to a plurality of divider circuits (52, 54) associated with the comparator circuit (56, 59). The control signal (n-1) is divided by the divider circuit (52, 54) and the obtained value is fed into the comparator circuit (56, 59), or the value is compared with the counted value supplied by the divider network controllable (44). A distribution network (21), used to produce a timing in the distribution of the system clock signals, which allows the synchronization of elements of the data processing system, is placed in the phase locked loop (33). to ensure constant frequency signals and system clock signals are in phase.
Description
Claims
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US823729 | 1977-08-11 | ||
US06/823,729 US4748644A (en) | 1986-01-29 | 1986-01-29 | Method and apparatus for a constant frequency clock source in phase with a variable frequency system clock |
Publications (2)
Publication Number | Publication Date |
---|---|
EP0292502A1 true EP0292502A1 (en) | 1988-11-30 |
EP0292502B1 EP0292502B1 (en) | 1990-05-23 |
Family
ID=25239563
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP87901789A Expired - Lifetime EP0292502B1 (en) | 1986-01-29 | 1987-01-29 | Method and apparatus for a constant frequency clock source in phase with a variable frequency system clock |
Country Status (6)
Country | Link |
---|---|
US (1) | US4748644A (en) |
EP (1) | EP0292502B1 (en) |
JP (1) | JPS63503412A (en) |
AU (1) | AU7082287A (en) |
CA (1) | CA1286413C (en) |
WO (1) | WO1987004813A1 (en) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3719582C2 (en) * | 1987-06-12 | 1999-01-28 | Philips Broadcast Television S | Circuit arrangement for generating a phase reference signal |
US4849998A (en) * | 1988-06-03 | 1989-07-18 | Communications Satellite Corporation | Rate synchronized symbol timing recovery for variable rate data transmission systems |
GB2228598A (en) * | 1989-02-28 | 1990-08-29 | Ibm | Clock signal generator for a data processing system |
GB8906093D0 (en) * | 1989-03-16 | 1989-04-26 | British Telecomm | Optical transmission system |
US4972442A (en) * | 1989-04-27 | 1990-11-20 | Northern Telecom Limited | Phase-locked loop clock |
US4972160A (en) * | 1989-12-07 | 1990-11-20 | Northern Telecom Limited | Phase-lock loop circuit with improved output signal jitter performance |
JPH04371024A (en) * | 1991-06-19 | 1992-12-24 | Sony Corp | Pll frequency synthesizer |
FR2680058B1 (en) * | 1991-07-30 | 1994-01-28 | Sgs Thomson Microelectronics Sa | METHOD AND DEVICE FOR SYNCHRONIZING A SIGNAL. |
EP0686917A1 (en) * | 1994-06-07 | 1995-12-13 | International Business Machines Corporation | Apparatus for processing a series of timing signals |
JPH07336784A (en) * | 1994-06-08 | 1995-12-22 | Toshiba Corp | Clock synchronization device |
JP2817676B2 (en) * | 1995-07-31 | 1998-10-30 | 日本電気株式会社 | PLL frequency synthesizer |
KR100193806B1 (en) * | 1995-10-13 | 1999-06-15 | 윤종용 | Clock Generation Circuit and Method of Switching System |
US5784332A (en) * | 1996-12-12 | 1998-07-21 | Micron Technology Corporation | Clock frequency detector for a synchronous memory device |
US6172935B1 (en) | 1997-04-25 | 2001-01-09 | Micron Technology, Inc. | Synchronous dynamic random access memory device |
US7397314B2 (en) * | 2002-09-11 | 2008-07-08 | Hewlett-Packard Development Company, L.P. | Redundant clock source |
JP4624928B2 (en) * | 2006-01-12 | 2011-02-02 | ルネサスエレクトロニクス株式会社 | Semiconductor integrated circuit device |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3621451A (en) * | 1969-02-26 | 1971-11-16 | Hewlett Packard Co | Frequency multiplier |
JPS4999260A (en) * | 1973-01-26 | 1974-09-19 | ||
US4030045A (en) * | 1976-07-06 | 1977-06-14 | International Telephone And Telegraph Corporation | Digital double differential phase-locked loop |
AU577329B2 (en) * | 1983-11-07 | 1988-09-22 | Motorola, Inc. | Synthesized clock microcomputer with power saving |
-
1986
- 1986-01-29 US US06/823,729 patent/US4748644A/en not_active Expired - Lifetime
-
1987
- 1987-01-28 CA CA000528350A patent/CA1286413C/en not_active Expired - Fee Related
- 1987-01-29 JP JP62501438A patent/JPS63503412A/en active Granted
- 1987-01-29 WO PCT/US1987/000177 patent/WO1987004813A1/en active IP Right Grant
- 1987-01-29 AU AU70822/87A patent/AU7082287A/en not_active Abandoned
- 1987-01-29 EP EP87901789A patent/EP0292502B1/en not_active Expired - Lifetime
Non-Patent Citations (1)
Title |
---|
See references of WO8704813A1 * |
Also Published As
Publication number | Publication date |
---|---|
AU7082287A (en) | 1987-08-25 |
EP0292502B1 (en) | 1990-05-23 |
US4748644A (en) | 1988-05-31 |
WO1987004813A1 (en) | 1987-08-13 |
JPH0437446B2 (en) | 1992-06-19 |
JPS63503412A (en) | 1988-12-08 |
CA1286413C (en) | 1991-07-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP0292502A1 (en) | Method and apparatus for a constant frequency clock source in phase with a variable frequency system clock. | |
US6275553B1 (en) | Digital PLL circuit and clock generation method | |
US4068198A (en) | Phase-locked loop frequency shift key modulator | |
US4864253A (en) | Phase locked loop wherein phase comparing and filtering are performed by microprocessor | |
US3976946A (en) | Circuit arrangement for frequency division by non-integral divisors | |
CN106788420A (en) | A kind of signal frequency detection method, device and signal frequency controller | |
US3840822A (en) | Decadically adjustable frequency synthesizer | |
US4704723A (en) | Frequency divider | |
US3731219A (en) | Phase locked loop | |
US3435367A (en) | Digitally controlled frequency synthesizer | |
US3370252A (en) | Digital automatic frequency control system | |
US4540945A (en) | Variable-frequency oscillation circuit | |
US3320546A (en) | Variable frequency controlled frequency divider | |
JPS61501002A (en) | Phase and frequency adjustment network and method for phase-locked loops | |
JPH11237489A (en) | Reference frequency generator | |
US4489279A (en) | Variable-frequency oscillator having a crystal oscillator | |
US4001726A (en) | High accuracy sweep oscillator system | |
US5017801A (en) | Method and apparatus for converting a gap-infested read-in clock into a gap-free read-out clock | |
US4417352A (en) | Microphase stepper employing improved digital timing incrementer employing a rate multiplier | |
KR19990009340A (en) | Synchronous device and method | |
US3528027A (en) | Electric signal generator with accurately controllable phase-settings | |
US6445227B1 (en) | Rational frequency divider | |
JPS60186116A (en) | Pll circuit | |
US3546594A (en) | Analog distortion measurement apparatus for isochronous coded telegraph and data signals | |
JP2615984B2 (en) | Signal processing circuit |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
17P | Request for examination filed |
Effective date: 19880808 |
|
AK | Designated contracting states |
Kind code of ref document: A1 Designated state(s): CH DE FR GB IT LI NL |
|
17Q | First examination report despatched |
Effective date: 19890907 |
|
GRAA | (expected) grant |
Free format text: ORIGINAL CODE: 0009210 |
|
AK | Designated contracting states |
Kind code of ref document: B1 Designated state(s): CH DE FR GB IT LI NL |
|
REF | Corresponds to: |
Ref document number: 3762929 Country of ref document: DE Date of ref document: 19900628 |
|
ITF | It: translation for a ep patent filed |
Owner name: STUDIO TORTA SOCIETA' SEMPLICE |
|
ET | Fr: translation filed | ||
PLBE | No opposition filed within time limit |
Free format text: ORIGINAL CODE: 0009261 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT |
|
26N | No opposition filed | ||
ITTA | It: last paid annual fee | ||
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: FR Payment date: 19921210 Year of fee payment: 7 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: DE Payment date: 19921211 Year of fee payment: 7 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: CH Payment date: 19921214 Year of fee payment: 7 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: GB Payment date: 19921231 Year of fee payment: 7 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: NL Payment date: 19930131 Year of fee payment: 7 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: GB Effective date: 19940129 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: LI Effective date: 19940131 Ref country code: CH Effective date: 19940131 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: NL Effective date: 19940801 |
|
NLV4 | Nl: lapsed or anulled due to non-payment of the annual fee | ||
GBPC | Gb: european patent ceased through non-payment of renewal fee |
Effective date: 19940129 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: FR Effective date: 19940930 |
|
REG | Reference to a national code |
Ref country code: CH Ref legal event code: PL |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: DE Effective date: 19941001 |
|
REG | Reference to a national code |
Ref country code: FR Ref legal event code: ST |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: IT Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20050129 |