EP0284856A2 - Méthode de traitement du contenu d'une mémoire de rafraîchissement d'image et dispositif pour exécuter cette méthode - Google Patents

Méthode de traitement du contenu d'une mémoire de rafraîchissement d'image et dispositif pour exécuter cette méthode Download PDF

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Publication number
EP0284856A2
EP0284856A2 EP19880103819 EP88103819A EP0284856A2 EP 0284856 A2 EP0284856 A2 EP 0284856A2 EP 19880103819 EP19880103819 EP 19880103819 EP 88103819 A EP88103819 A EP 88103819A EP 0284856 A2 EP0284856 A2 EP 0284856A2
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EP
European Patent Office
Prior art keywords
memory
image
processing
word
words
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP19880103819
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German (de)
English (en)
Other versions
EP0284856A3 (fr
Inventor
Helmut Koch
Rudolf Diepold-Scharnitzky
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Wincor Nixdorf International GmbH
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Wincor Nixdorf International GmbH
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Publication of EP0284856A2 publication Critical patent/EP0284856A2/fr
Publication of EP0284856A3 publication Critical patent/EP0284856A3/fr
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/127—Updating a frame memory using a transfer of data from a source area to a destination area

Definitions

  • the invention relates to a method for processing the memory content of an image repetition memory, in which the memory words of at least one image line can be addressed with a common memory line address and in each case one memory column address.
  • the invention further relates to a circuit arrangement for carrying out the method.
  • Refresh memories are used in data display devices to keep the information to be displayed on a screen ready for cyclic reading, so that they are displayed with a refresh rate corresponding to the cycle time.
  • the refresh rate determines the picture quality, because if it is below about 70 Hz, the picture is restless, ie there is a flickering effect. This is particularly the case with positive image display, particularly graphic symbols, in which dark characters are reproduced on a light background.
  • a refresh rate of 70 Hz corresponds to a cycle time of 14.2 ms.
  • information changes can be carried out on the one hand by changing the image, on the other hand by changes within a current image.
  • the latter type of information change is relevant e.g. when editing texts and graphic information, and these information changes are made by direct access to the image repetition memory. This can involve changes to information with and without changing its position on the screen.
  • copying or moving image sections can be considered. If the data processing carried out with such an information change is slower than the cycle time of the image repetition, the information change on the screen is perceived as a step-like movement or as a progressive image change, which is undesirable in most cases, since image changes of this type mean when using a Data display device unnecessary expenditure of time.
  • the data processing carried out when the information is changed in connection with the image repetition memory is carried out in a so-called graphics coprocessor, which is in addition to the required computer in the data display device is provided.
  • graphics coprocessor which is in addition to the required computer in the data display device.
  • the type HD63484 from Hitachi requires a time of approximately one second to copy an image area with a size of 1000 x 1000 pixels.
  • Such long information processing is in no way suitable to avoid the above-mentioned adverse phenomena, in particular it can be readily recognized that control movements carried out manually are only reproduced on the screen with a considerable delay.
  • the invention solves this problem for a method of the type mentioned in that the processing at least Memory words of an image line to be changed are packaged, for which purpose a single memory line addressing and word-by-word memory column addressing is carried out for read and / or write access for this image line.
  • the invention accelerates the process flow in data processing for changing information in the image repetition memory, by means of which operations to be carried out for changing the information are completed within only a few image repetition times, so that there is a substantial reduction in the adverse effects of internal runtimes and access times. As will be shown, the invention even opens up the possibility of performing these operations within a single image refresh time, so that the undesirable effects of the image display are then completely avoided.
  • the packet-by-packet handling of the memory words to be changed for each image line saves time, since, as is known, image repetition memories are organized in such a way that the memory words of one or more successive image lines can be found under a memory destination address. If the memory words of an image line to be changed are now processed in packets, then only a single memory line addressing has to be carried out, the individual memory words then being reached by the memory column addressing. In this way, internal runtimes and access times are avoided, which are incurred in the previous procedure due to the memory line addressing of each individual memory word of an image line.
  • the invention can now be further developed in such a way that address calculations, sequence controls and lo required for execution in the processing of memory words logic logic circuits can be used.
  • This further development considerably accelerates the data processing when information is changed, so that the total time required for an information change can be in the order of an image repetition time of 14.2 ms.
  • circuit technology instead of microprograms, the operations in question can run so quickly that an essential part of the total expenditure of time is only the internal runtimes and access times of the image repetition memory.
  • the use of circuit technology would likewise bring about an acceleration in the previously known type of process sequence in graphic coprocessors, but the time range of a picture repetition time would not be reached. Only the use of circuit technology in connection with the basic idea of the invention leads to this considerable time advantage.
  • the method according to the invention is advantageously further developed such that the read memory words of an image line are buffered between processing steps. This saves a further amount of time.
  • the processing of memory words in packets according to the invention requires these memory words to be buffered. If the processing of the memory words is subdivided to a certain extent by the intermediate storage, it is possible to put individual processing steps in front of the intermediate memories in the access time that occurs when reading the image repetition memory. This also applies correspondingly to the write operation after the intermediate storage, since the processing steps required after the intermediate storage can then lie in the write memory access time.
  • processing using logic circuits could only utilize the memory access times for memory word processing with considerable circuitry complexity.
  • the read memory words are buffer-stored with a shift in their information content which corresponds to the amount of the image shift that deviates from the integer multiple of a memory word length.
  • the image shift is one of the processing steps that are carried out before the intermediate storage. This also makes a meaningful separation of the operation of the image shift from the operations of other image changes required after the intermediate storage.
  • the invention can advantageously be further developed such that the memory line address and the respective memory line address and the image position-oriented default values for the source position the memory column address and the number of memory words per image line and the number of image lines that are suitable for processing in packets are calculated.
  • This development ensures that the computer one Data display device, in which the invention is applied, is relieved and that time expenditure caused by this computer is avoided.
  • each image line contains a predetermined number of pixels, each of which is defined by an information element belonging to a memory word of the image repetition memory. The number of pixels per memory word thus determines the number of memory words per image line.
  • a word length is indicated in Fig. 1 in the image line 0.
  • Access to the frame buffer is word-organized, i.e. The memory words of one or more successive image lines can be reached with a memory line address.
  • each picture line 0 to n in the picture repetition memory is represented by a sequence of a predetermined number of memory words.
  • Each of these memory words is accessed under a memory row address and a memory column address, the memory words of an image line having a matching memory row address.
  • An image section A is shown in the screen area shown in FIG. 1, the upper left corner of which is formed by the pixel P.
  • This pixel P has the coordinates Xp and Yp.
  • the size of the image section A is defined in the X direction by a predetermined number of pixels and in the Y direction by a predetermined number of lines.
  • the image section A has a height of two image lines. Its length in the X direction does not have to be an integer multiple of the word length of the memory words. Likewise, its left and right boundary lines do not have to coincide with a memory word beginning or a memory word end. This is taken into account in the image section A shown in FIG.
  • image section A begins in the fifth memory word of lines 2 and 3 and ends in the ninth memory word of these lines.
  • FIG. 1 shows a further image section A ⁇ , the position of which on the image field is defined by a point P ⁇ and the size of which corresponds to that of the image section A.
  • the shift results in the coordinates Xp ⁇ and Yp ⁇ for the pixel P ⁇ and additional image sections D and E, shown in broken lines in FIG. 1, which in turn show that the image section A ⁇ also begins and ends within a memory word. In the example shown, these are the eighth and the twelfth memory word of two successive picture lines.
  • the additional image section D need not have the same size as the image section B.
  • the example of a duplication of an image section shown in FIG. 1 is only one possible way of processing memory words according to the method to be described below.
  • pure displacements of image sections are also possible, that is, not the duplication, but rather the displacement of an image section from one position of the image surface to the other.
  • Another type of image processing consists in the logical combination of the memory words of an image section with predetermined information, as a result of which an image section can be changed without shifting on the image surface.
  • the memory words forming this image section A are to be read from the image repetition memory, to be processed and to be rewritten into the image repetition memory at a position corresponding to the screen coordinates Xp ⁇ and Yp ⁇ .
  • the processing of the memory words therefore initially consists in the fact that their information is provided with new memory row and memory column addresses. In this way, there is an information content of the screen memory which corresponds to the image structure shown in FIG. two image sections A and A ⁇ are displayed on the screen, the information contents of which match.
  • Fig. 2 shows schematically and substantially enlarged compared to Fig. 1, the two memory words in which the pixels P and P ⁇ of the two image sections A and A ⁇ shown in Fig. 1 are.
  • the position of the pixels P and P ⁇ in these memory words results in parts A and A ⁇ which lie in the image sections A and A ⁇ and parts B and D which lie outside the image sections A and A ⁇ .
  • a pixel-by-pixel representation of the memory words is provided in FIG. 2, in which each memory word contains 16 pixels.
  • the pixel P is the tenth pixel in the first memory word of the image section A
  • the pixel P ⁇ is the fifth pixel in the first memory word of the image section A ⁇ . From this it can be seen that in a duplication process of the type shown in FIG.
  • FIG. 3 shows the basic structure of a data display device 1 which is equipped with a circuit arrangement 4 operating according to the invention.
  • a circuit arrangement is also referred to as a bit block operator.
  • the data display device 1 contains a system interface 2, via which it is connected to a data processing device, not shown in FIG. 3, whose functions or work results are to be displayed on a screen 7.
  • the information coming from the data processing device is fed in parallel via the system interface 2 to the bit block operator 4 and a graphics controller 3.
  • the graphics controller 3 can be a conventional processor with which the representation of geometric figures on the screen 7 is achieved.
  • the graphics controller 3 has access to an image repetition memory 5, which is constructed from dynamic memory modules, as is customary for image repetition memories.
  • the graphics controller 3 and the bit block operator 4 can change or edit the image information contained in the image repetition memory 5 and contain it in the image repetition memory 5
  • the memory words are read with a reading circuit which causes the information to be displayed on the screen 7.
  • the structure of the data display device 1 shown in FIG. 3 corresponds to conventional technology with the exception of the bit block operator 4.
  • the control circuits for the refresh memory 5 are not shown in FIG. 3, since they are not absolutely necessary for understanding the invention.
  • FIG. 3 A possible embodiment of the bit block operator is shown in block form in FIG.
  • this circuit arrangement is connected on the one hand to the system interface 2 and on the other hand to the image memory 5 and exchanges information with these units. This information exchange takes place via a bus interface 41 with the system interface 2 and via a memory interface 49 with the image repetition memory 5.
  • the circuit arrangement contains a sequence control, not shown in FIG. 4, with which the implementation of the individual steps of the method according to the invention is controlled. This sequence control is connected to all of the functional units shown in FIG. 4 and can be seen in more detail below in connection with the method sequence.
  • the circuit arrangement shown in FIG. 4 has a control section with functional units 42, 43 and 44 and a processing section with functional units 45, 46, 47, 48 and 50.
  • the control section is used to derive processing instructions from the system interface 2 (FIG. 3) Entered here to calculate addresses and processing criteria to be described later, and their functional units 42, 43 and 44 are constructed from logic circuits for this purpose, so that they have practically no time delay can perform the necessary calculations.
  • These are a control register group 42, an arithmetic logic unit 43 for calculating the processing criteria and an address generator 44.
  • the control register group 42 receives its information from the bus interface 41 and can output information to it.
  • the information supplied to it is coordinate and size values of image sections that are to be processed, for example, according to FIG. 1.
  • the control register group 42 also receives information about what type of processing of image sections is to be carried out.
  • the control register group 42 outputs information to the arithmetic logic unit 43. This calculates the physical addresses required for the processing to be carried out, with which the image repetition memory 5 (FIG. 3) can be controlled. It also calculates the processing criteria already mentioned, which are referred to in FIG. 4 as partial word length and displacement value.
  • the shift value corresponds, for example, to the number of pixels by which the pixels P and P ⁇ shown in FIG. 2 are shifted relative to one another in the X direction.
  • the partial word length corresponds to the number of pixels in FIG. 2 by which the pixel P ⁇ is shifted within its memory word relative to the beginning of the memory word.
  • the shift value is fed as a control variable to a shift circuit 48, which receives information from a register section 50 of the memory interface 49.
  • the shift circuit 48 shifts the information within memory words entered into it and read from the frame buffer 5 by the shift value supplied to it and then outputs these memory words to a buffer memory 47, the addressing of which takes place with addresses which the address generator 44 has calculated.
  • the storage volume of the buffer memory 47 corresponds at least to the length of one screen line, so that the memory words of a screen line can be kept in a packet-like manner in the buffer memory 47 for further processing in processing logic 46.
  • This processing logic 46 receives their information about which type of processing is to be carried out by the control register group 42.
  • the memory words processed in packages with the processing logic 46 are then output to a further processing logic 45 in which a processed image section again with regard to the position of its limits in the X direction within the respective limit memory word is processed.
  • a processed image section again with regard to the position of its limits in the X direction within the respective limit memory word is processed.
  • the position of those pixels of a processed limit memory word is therefore taken into account, the information content of which must remain unchanged, so that, for example, the position difference of the image section A ⁇ shown in FIG. 1 with respect to a memory word start or memory word end is detected.
  • the processed memory words are then fed back to the memory interface 49, via which they are written into the refresh memory 5 under addressing with memory row addresses and memory column addresses which were calculated by the address generator 44.
  • the register section 50 of the memory interface 49 also serves to supply the two processing logics 45 and 46 with the memory words which are contained in the image repetition memory 5 at those locations which are to be overwritten with new information. It is then possible to link old information with new information in the processing logic 46 and to record those old information in the limit word processing logic 45 which are to form the old partial word to be rewritten unchanged.
  • FIGS. 5a to 5d The sequence of the method according to the invention is described below with reference to FIGS. 5a to 5d with reference to the circuit arrangement shown in FIG. 4.
  • a processing of the type shown in FIG. 1 is to be explained first, in which an image section A in the form of a further image section A ⁇ is duplicated.
  • the image section A is referred to below as the source section, the image section A ⁇ as the destination section.
  • these two image sections contain source words and target words as memory words, which can be controlled in source memory 5 with source addresses and target addresses.
  • the memory words to be processed in one image line i.e. the memory words in the first image line of an image section to be processed
  • the memory line address of the first source word is output by the address generator 44 via the memory interface 49 in a first step.
  • the memory column address of the first source word is output by the address generator 44 via the memory interface 49. This provides access to the first source word in the frame buffer 5, so that it is then read into the register section 50 of the memory interface 49.
  • the first source word can then be adopted by the disk circuit 48, in which its information content is shifted by the shift value.
  • the first source word treated in this way is then loaded into the buffer memory 47.
  • the memory column address of the second source word can then already be output by the address generator 44 via the memory interface 49, so that the second source word can be written into the register section 50 in parallel with the loading of the first source word into the buffer memory 47. From the parallel Carrying out the previously described method steps shows a time-saving effect, because there is a temporally nested transfer and processing of information.
  • the next step is a branch, in which a query is made as to whether the last source word of the addressed memory line has been read or not. If the result is negative, the previously described method steps of information shifting and intermediate storage or the output of the next source word are repeated; if the result is positive, the source word last written into register section 50 is, as already described, subjected to information shifting in shift circuit 48 and loaded into buffer store 47. This completes the packet-wise transfer of the source words of an image section to be processed into the buffer memory 47.
  • FIG. 5 b shows that part of the method sequence in which the source words, which are transferred in packets to the buffer store 47, are processed in the processing logics 46 and 45 and are then written back into the image repetition store 5.
  • the memory row address of the first target word is output by the address generator 44 via the memory interface 49 in a first step, after which the memory column address of the first target word is output.
  • the first target word can then be accessed in the image repetition memory 5, so that it is written into the register section 50 of the memory interface 49.
  • the first source word in the intermediate memory 47 is then logically linked in the processing logic 46 in accordance with a specification that is supplied to it by the control register group 42. Then it will be the result of the linkage obtained in the limit word processing logic 45 is subjected to a limit word processing of the type described, for which the information of the first target word present in the register section 50 is used.
  • the memory word processed in this way can be fed to the image repetition memory 5, for which purpose the address generator 44 outputs the memory column address of the first target word via the memory interface 49. Since the memory line address of the target image line remains the same as part of the processing of the memory words in packets, it does not have to be output again.
  • the first processed memory word can then be written into the frame buffer 5 at the target position.
  • the logical combination of the second source word present in the intermediate memory 47 can already be carried out. This is followed by a branch with a query as to whether the logical linkage carried out in the previous method step was carried out with the penultimate source word contained in the intermediate memory 47. If the result is negative, the previous method steps are carried out again; if the result is positive, the memory column address of the penultimate target word is output by the address generator 44 via the memory interface 49. Then the penultimate processed source word is written into the frame buffer 5. The memory column address of the last target word is then output by the address generator 44 via the memory interface 49 and the last target word is transferred to the register section 50.
  • the limit word processing in the limit word processing logic 45 can then be carried out for the last one in the meantime memory 47 existing source word can be performed. Finally, the address column 44 outputs the memory column address of the last target word via the memory interface 49 and the last processed source word is written as the last target word in the frame buffer 5.
  • the image section in question becomes visible at a second position of the image area instead of the previous information available there. These are therefore overwritten in the image repetition memory so that they are no longer visible on the image surface.
  • a representation of the new image section can also be considered in such a way that the new image information is to be superimposed on the old image information, so that an image mixture occurs at the location of the new image section.
  • the memory words of the first image section for example of the image section A shown in FIG. 1, are to be linked with the memory words of the image section A ⁇ present at the target position. This linkage takes place in the circuit arrangement shown in FIG.
  • FIG. 5c Processing of memory words in the sense of image mixing is shown in FIG. 5c.
  • the memory line address of the first target word is output by the address generator 44 via the memory interface 49.
  • the corresponding column address is then output, so that the first target word from the frame buffer 5 can be written into the register section 50 of the memory interface 49.
  • the first source word in the intermediate memory 47 is then logically linked to the first target word in the processing logic 46 and then the previously described limit word processing in the limit word processing logic 45.
  • the first target word is also used for this.
  • the memory column address of the first target word is output by the address generator 44 via the memory interface 49.
  • the memory row address is the same.
  • the method variant shown in FIG. 5c works on the principle that the source words of an image line present in the intermediate memory 47 are successively linked to target memory words which are individually read out from the image repetition memory 5 and transferred to the register section 50. However, it is also possible to temporarily store these target memory words in packets, for which purpose the intermediate memory 47 must then have the volume of at least two image lines. The source words of an image line and the target words of an image line can then be stored next to one another in the intermediate memory 47 and fed to the processing logic 46 for linking to one another. It is possible to carry out a time-nested mode of operation similar to that shown in FIG.
  • FIGS. 5a, b and c each show on the left side of the process representation the access times which arise during the individual process steps and which are added up to a total processing time of the respective process section.
  • the numerical values of these access times result in each case for processing an image line with 32 memory words for the dynamic memory of the type MB81461-12 from the company Fujitsu, which is described in the data book 1986 of this company.
  • a total processing time of 8.28 microseconds for one image line results for the implementation of the overall method according to FIGS. 5a and 5b.
  • a time of 8.28 microseconds x 1360 is then required for the overall construction of such an image. This total time is 11.26 ms. It is therefore significantly less than the image repetition time of 14.2 ms for an image frequency of 70 Hz.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
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EP88103819A 1987-03-31 1988-03-10 Méthode de traitement du contenu d'une mémoire de rafraíchissement d'image et dispositif pour exécuter cette méthode Withdrawn EP0284856A3 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE3710696 1987-03-31
DE19873710696 DE3710696A1 (de) 1987-03-31 1987-03-31 Verfahren zum bearbeiten des speicherinhalts eines bildwiederholspeichers und schaltungsanordnung zur durchfuehrung des verfahrens

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EP0284856A2 true EP0284856A2 (fr) 1988-10-05
EP0284856A3 EP0284856A3 (fr) 1990-07-18

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EP88103819A Withdrawn EP0284856A3 (fr) 1987-03-31 1988-03-10 Méthode de traitement du contenu d'une mémoire de rafraíchissement d'image et dispositif pour exécuter cette méthode

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Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3924774A1 (de) * 1989-07-26 1991-02-07 Fraunhofer Ges Forschung Datenverarbeitungsanlage fuer fenster-orientierte rastergraphik-systeme

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4094000A (en) * 1976-12-16 1978-06-06 Atex, Incorporated Graphics display unit
GB2073995A (en) * 1980-04-11 1981-10-21 Ampex Computer graphic system
EP0097778A2 (fr) * 1982-06-30 1984-01-11 International Business Machines Corporation Mémoire digitale
EP0099989A2 (fr) * 1982-06-28 1984-02-08 Kabushiki Kaisha Toshiba Dispositif de commande d'affichage d'une image
US4625203A (en) * 1983-10-18 1986-11-25 Digital Equipment Corporation Arrangement for providing data signals for a data display system

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3015125A1 (de) * 1980-04-19 1981-10-22 Ibm Deutschland Gmbh, 7000 Stuttgart Einrichtung zur speicherung und darstellung graphischer information

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4094000A (en) * 1976-12-16 1978-06-06 Atex, Incorporated Graphics display unit
GB2073995A (en) * 1980-04-11 1981-10-21 Ampex Computer graphic system
EP0099989A2 (fr) * 1982-06-28 1984-02-08 Kabushiki Kaisha Toshiba Dispositif de commande d'affichage d'une image
EP0097778A2 (fr) * 1982-06-30 1984-01-11 International Business Machines Corporation Mémoire digitale
US4625203A (en) * 1983-10-18 1986-11-25 Digital Equipment Corporation Arrangement for providing data signals for a data display system

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EP0284856A3 (fr) 1990-07-18
DE3710696A1 (de) 1988-11-10

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