EP0263175A1 - Appareil et procede pour le codage et le decodage de donnees d'attributs dans les symboles de controle d'erreur de donnees principales - Google Patents

Appareil et procede pour le codage et le decodage de donnees d'attributs dans les symboles de controle d'erreur de donnees principales

Info

Publication number
EP0263175A1
EP0263175A1 EP87903098A EP87903098A EP0263175A1 EP 0263175 A1 EP0263175 A1 EP 0263175A1 EP 87903098 A EP87903098 A EP 87903098A EP 87903098 A EP87903098 A EP 87903098A EP 0263175 A1 EP0263175 A1 EP 0263175A1
Authority
EP
European Patent Office
Prior art keywords
error check
data
check symbols
attribute
attribute data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP87903098A
Other languages
German (de)
English (en)
Other versions
EP0263175A4 (en
Inventor
Sohei Takemoto
Leonard A. Pasdera
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ampex Systems Corp
Original Assignee
Ampex Corp
Ampex Systems Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ampex Corp, Ampex Systems Corp filed Critical Ampex Corp
Publication of EP0263175A1 publication Critical patent/EP0263175A1/fr
Publication of EP0263175A4 publication Critical patent/EP0263175A4/en
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/35—Unequal or adaptive error protection, e.g. by providing a different level of protection according to significance of source information or by adapting the coding according to the change of transmission channel characteristics
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's

Definitions

  • the invention relates to the field of transmission of digital data. More specifically, the invention relates to the encoding of attribute data into the parity or error check symbols for main data, i.e., the addition of additional data symbols to the data symbols of the digital data being transmitted which are the error check symbols encoded with the information of the attribute data to be conveyed, and later recovery of said attribute data from the transmitted main data combined with its attribute encoded error check symbols.
  • error check symbols or parity symbols which are generated from the data being transmitted and which are used on the receiver side of the link to improve the reliability of the transmission process.
  • error check symbols are usually digital bits when binary code is used, but may also be symbols having more than two values for codes other than binary.
  • the error check or parity symbols will hereafter be referred to as error check symbols.
  • error check symbols They are generated in many different known ways.
  • the generation of error check symbols involves the use of error correcting codes which translate the main data to be transmitted or recorded into one or more error check symbols.
  • linear error correcting codes this is done by dividing the polynomial represented by the main data by an error check polynomial and using the remainder as the error check symbols.
  • error correction codes are known to do this translation process some of which are linear and some of which are not linear. Those skilled in the art appreciate the difference between linear and nonlinear codes.
  • the main data and the error check symbols are combined and transmitted to the receiver.
  • the main data to be transmitted without any error check symbols appended thereto will be referred to as the main data while the main data with the error check symbols appended thereto will be referred to as the transmitted data.
  • the main data with the error check symbols appended thereto and encoded with the attribute data will be referred to hereafter as the attribute encoded transmitted data.
  • the transmitted data is decoded to generate what is called a syndrome. If there were no errors in the transmission process, the syndrome will indicate this condition, usually by being all zeros in the binary code case. If there were errors, the syndrome will so indicate. Furthermore, if the error was within the range of error correction of the error check symbols, the location of the error will be indicated by the syndrome.
  • the range of error correction is controlled by the number of error check symbols that are appended to the main data and is the number of errors which can occur and be corrected by use of the error check symbols although any number of errors can be detected but may not be correctable because they exceed the error correction range.
  • the error check symbols may be decoded with the main data to allow correction of errors of less than a certain number of symbols and detection of some errors having a greater number of symbols in error.
  • the use of a higher number of check symbols for a given number of main data symbols will increase the reliability of the error detection and error correction process.
  • attribute data In certain digital systems, a set of separate and dedicated data symbols is commonly used to identify certain attributes of the main data that is to be transmitted. Hereafter, this separate and dedicated data will be called “attribute data”.
  • attribute data can be the horizontal sync-to-color subcarrier burst phase for every TV scanning line. This phase relationship is not specified in the color television signal. It is a value that must be calculated based upon the detected relative times of occurrence of a certain time in the horizontal synchronization pulse and the beginning of the color subcarrier burst. In digital video applications, this phase relationship may be calculated on the transmitter side.
  • the difficulty with this approach is that in transmitting the attribute data in addition to the main data, a certain portion of the bandwidth of the transmission channel must be devoted to the transmission of the attribute data, and, in the case of storage, certain physical space on magnetic media or like memory is required for the attribute data.
  • Bandwidth in transmission channels and space in storage memories is usually at a premium, and it is advantageous to save bandwidth in transmission channels and space in storage memories in any possible manner.
  • the "transmitter side”, in a first embodiment, should be understood as referring to circuitry which generates unencoded error check symbols from the main data to be transmitted, hereafter referred to as the "first error check symbols", and which generates error check symbols for a selected member of an attribute data class, hereafter called the “attribute error check symbols" (note that the "error check symbols" for the attribute data are not actually used to detect and correct errors in the attribute data but are merely used to identify the member of the attribute data class and further references to attribute error check symbols should be understood to mean attribute data identification symbols) and combines the two sets of error check symbols into what will be hereafter referred to as "modified error check symbols" for actual transmission.
  • the transmitter side circuitry should be understood as referring to the circuitry which concatenates the selected member of the attribute data class at the most significant bit position of the main data to form an input string to an error check bit generator and generates error check symbols from this input string.
  • error check symbols will also be referred to as "modified error check symbols”.
  • the receiver side circuitry in a first embodiment, should be understood as referring to the circuitry which: operates on the main data in the condition in which it is received, hereafter referred to as the "received main data", to generate new error check symbols therefrom which will be hereafter referred to as the "second main data error check symbols”; combines the second main data error check symbols with the received version of the modified error check symbols, hereafter referred to as the “received modified error check symbols” to generate what may be hereafter referred to as a "partial syndrome”; generates for each member of the attribute data class a set of error check symbols, hereafter referred to as the "second attribute error check symbols”; and combines the partial syndrome with each set of second attribute error check symbols to generate a series of symbol groups or symbol patterns which will hereafter be referred to as "syndromes”; and performs a zero detect operation on each syndrome to determine which syndrome is all zeros so as to determine the identity of the selected member of the class of attribute data which was encoded on the transmitter side.
  • the receiver side circuitry should be understood as referring to that circuitry that does the following: concatenates each member of the attribute data group, one member at a time, with the received main data; generates error check symbols for each combination of one member of the attribute data class with the received main data, said error check symbols hereafter referred to as "third error check symbols”; combines each group of third error check symbols with the modified error check symbols as received, hereafter referred to as "received modified error check symbols" to generate a plurality of syndromes; and performs a zero detect process on each syndrome to determine which syndrome is all zeros and, thus, which member of the attribute data class was encoded on the transmitter side.
  • the act of transferring the data between the transmitter side and the receiver side will be referred to only as trans ission although recording of the data with later replay is also included within the term transmission.
  • a "word” will be understood as referring to a fixed number of symbols, and the main data field concatenated with its error check symbols may or may not be, but usually is, equal to one word in length depending upon the particular embodiment of the invention being considered.
  • the term "symbols” will be used to refer to the individual components of main data field or any of the error check fields and should be understood as meaning binary bits in the case of binary number system embodiments of the invention or other individual digits in alternative number systems in which the invention may be implemented such as Reed-Solomon code. The number systems that may be used to practice the invention are discussed more fully below.
  • Ax the selected member of the class of attribute data members which is to be encoded into the error check symbols for the main data, i.e., the "attribute data”.
  • D the main data which is to be transmitted, i.e., the "main data”.
  • Pd the error check symbols which would be generated by the transmitter side circuitry if the input field were D or D concatenated with sufficient leading zeros to make up one word at the input of the error check bit generation circuitry, i.e., the "first main data error check symbols".
  • Pax the error check symbols for A alone or A concatenated with sufficient trailing zeros to make up one word, i.e., the "attribute error check symbols" where this term is to be understood as meaning the symbols which uniquely identify the member of the attribute
  • attribute check symbols 10 data class to which they correspond and not as symbols to be used for error detection and correction of the attribute data.
  • attribute check symbols may be alternatively used and should be understood
  • the attribute check symbols may be the attribute data itself as long as the attribute data field is less than or equal to the length of the Pd field in certain embodiments which will be
  • D' the version of the main data which is received by the receiver side after transmission, i.e., the "received main data”. This version may have errors in it because of 5 errors introduced in the transmission process.
  • P' the version of the modified error check symbols received at the receiver side, i.e., the "received modified error check symbols" 10 (this version may have errors in it because of errors introduced in the transmission process).
  • Pd' the error check symbols which are generated by the receiver circuitry using D' or 15 D' with sufficient leading zeros to make up one word as the input field to the receiver side error check bit calculation circuitry, i.e., the "second main data error check symbols".
  • Pal . . . Pax . . .Pan the error check 30 symbols supplied to the decoder circuitry on the receiver side and corresponding to the members of the attribute data class Al . . . Ax . . . An to allow mathematical deduction of the identity of Ax, i.e., the "attribute check symbols" where this term is to be understood as meaning the symbols which uniquely identify the member of the attribute data class to which they correspond and not as symbols to be used 5 for error detection and correction of the attribute data.
  • the term "attribute error check symbols” may be used and should be understood as a unique code word identifying the particular member of the
  • the attribute check symbols may be the attribute data itself as long as the
  • attribute data field is less than or equal to the length of the Pd field in certain embodiments which will be hereafter defined and referred to as the decomposed embodiments.
  • attribute check symbols may be alternatively used and should be understood as a unique code word identifying the particular member of the attribute data class to which the code word corresponds regardless of whether an error 5 correction code or some other code was used to generate the attribute check symbols.
  • the attribute check symbols may be the attribute data itself as long as the attribute data field is less than or equal to 10 the length of the Pd field in certain embodiments which will be hereafter defined and referred to as the decomposed embodiments.
  • alpha the selected mathematical and/or 15 logical operation or sequence of operations which are used to encode the attribute error check symbols into the first error check symbols on the transmitter side and for selected operations on the receiver side.
  • the 20 preferred alpha operator is the logical exclusive-or operation since the preferred number system is binary.
  • alpha inverse the inverse operation or reverse 25 sequence from alpha which may hereafter be called alpha inverse or the inverse operator.
  • alpha inverse the inverse operation or reverse 25 sequence from alpha which may hereafter be called alpha inverse or the inverse operator.
  • alpha may not be defined or may not be unique).
  • the identity operator any mathematical or logical operation which can determine if two groups of symbols are identical.
  • the exclusive-or or X-OR operation is a simple way of performing the identity operation.
  • this operator may also represent a bit for bit or a symbol for symbol comparison in a comparator etc.
  • the identity operator may take any form regardless of the character of the alpha operator although the X-OR operation is preferred since it is a simple operation in the preferred binary code system.
  • the generic method of the invention involves generating error check symbols which are modified by the presence of the attribute data or the attribute data error check symbols in the input stream to the circuitry that generates the modified error check symbols.
  • the selected member of the attribute data class is "encoded” into the modified error check symbols which are transmitted using the alpha operator.
  • the identity of the selected member of the attribute data class which was encoded on the transmitter side is "decoded” on the receiver side.
  • the process performed on the receiver side involves generally performing the inverse alpha operator between P 1 and Pd' to arrive at Pax' if the inverse alpha operator is defined. From Pax' the identity of the attribute data can be derived.
  • the receiver side circuitry may combine Pd' with each of Pal...Pan to generate a plurality of P". Each P" is compared to P' by the identity operator to determine the identity of Pax'. Pax' will be the one member of the class Pal...Pan which results in a P" which is identical with P*. If the inverse alpha operator is not unique, there will be ambiguity where several of the group Pal...Pan
  • Pax will correspond to the member of the ambiguous subset within the set Pal...Pax which resulted in a P" which is identical to P 1 .
  • the receiver side circuitry generates syndromes for each member of the attribute data class by performing an exclusive-or logical operation or its equivalent between the received modified error check symbols and the presyndrome generated for each member of the attribute data class.
  • the first syndrome detected which is all zero identifies the member of the attribute data class which was selected on the transmitter side for encoding to generate the modified error check symbols.
  • any error correction code can be used to practice the invention.
  • the inverse alpha operator will be defined only for alpha operators in a restricted class where a linear error correction code is used and alpha is taken from the algebraic body on which the linear error correction code is defined. If a nonlinear error correction code is used or if a linear error correction code is used with alpha not restricted to the class of alpha operator for which the inverse alpha operator is defined, then the receiver side circuitry must perform trial and error matching procedures to eliminate the ambiguity and find the true Pax Any mention of a linear error correction code herein should be understood by those skilled in the art to mean that the invention can also be practiced with nonlinear error correction codes except that the receiver circuitry may have to do trial and error matching steps to decode the true Pax.
  • the invention can be practiced in at least two known embodiments referred to herein as the decomposed method and the direct method.
  • the following method defines a generic form of the preferred decomposed method in which the invention may be practiced.
  • Other decomposed methods discussed later herein and the apparatus to perform these methods are the preferred embodiment of the invention and are species of the broad genus to follow.
  • the generic method of practicing the preferred method of the invention involves the following steps: calculate the first error check symbols from the main data using any error correction code, which error correction will hereafter be referred to as ECC 1; select the member of the attribute data class to be used and calculate the attribute error check symbols from the selected attribute data using any error correction code, hereafter referred to as ECC 2, which may or may not be different from ECC 1; encode the attribute error check symbols into the first error check symbols using any sequence of mathematical and/or logical operations between the two sets of error check symbols or the result of a previous mathematical operation, i.e., combine Pd and Pa using the alpha operator, to generate the modified error check symbols which are to be transmitted; transmit the main data and the modified error check symbols (in binary code embodiments, alpha is most conveniently the exclusive-or logical operation and this is the preferred code and the preferred alpha); using ECC 1, calculate the second main data error check symbols Pd'; apply the inverse alpha operator between P' and Pd' to derive Pax where the inverse alpha operator is defined;
  • Pd' is generated using ECC 1 and is combined using the alpha operator with each Pal...Pan or with each Pa in the class of Pal...Pan which satisfies the condition represented by P' and Pd'. '
  • Each such combination yields a presyndrome P".
  • Each such presyndrome is compared to P' using the identity operator to determine the identity of Pax. Pax will correspond to the member of the class Pal...Pan which resulted in a P" which was equal to P'.
  • the number system chosen has all the mathematical operations needed in the above process defined for it, the number system will be satisfactory. If the number system can be mapped to a corresponding binary number of 0's and l's the foregoing requirement will always be met.
  • the invention will work for both main data and error check symbols which are expressed either in binary where there are only two symbols are defined (logic 1 and logic 0) or it will work where the data and error check symbols are expressed in Reed-Solomon code where there are 16 symbols defined, each of which can be mapped to a binary nibble of four binary bits.
  • the teachings of the invention include a method and apparatus for encoding attribute error check symbols generated from a selected member of a class of attribute data members into the first error check symbols for the main data.
  • the modified error check symbols may then be transmitted over any medium along with the main data symbols to which they apply. Neither the symbols representative of the selected member of the class of attribute data members nor the attribute error check symbols generated from the selected attribute data member are directly or separately transmitted.
  • the details of the preferred decomposed method using binary code and the excl sive-or logic operation as the alpha operator involve separate error check symbol calculations on various fields and the combination of the results using the exclusive-or logical operation.
  • the encoding operations on the transmitter side are done individually on the main data D and the attribute data A and the resulting error check symbols are combined by an exclusive-or logical operation to generate the modified error check symbols P. That is, on the transmitter side in the decomposed method, the error check symbols Pd are generated by using one encoder having as its input field D concatenated with sufficient leading zeros to make up one word.
  • the error check symbols Pa are generated by another encoder which has as its input A concatenated with sufficient trailing zeros to make up a word at the input of the encoder.
  • the invention works best with a limited class of attribute data members.
  • the error check symbols Pa may be supplied from a look-up table or some other non-calculating circuit which can rapidly translate between Ax and its corresponding error check symbols Pax rather than calculating Pax using an error correction code.
  • the error check symbols Pa and Pd are combined by performing an exclusive-or logical operation between the two fields. This is the process of encoding the error check symbols Pd with the error check symbols Pa of the selected member of the attribute data class.
  • the main data D and the modified error check symbols P are transmitted.
  • the data field comprised of D concatenated with P may be used as the input field for a separate error checking system which forms a part of the transmission link system. This separate error checking system generates separate error check symbols on the input field D concatenated with P in the trailing bit position. These separate error check symbols may be generated with any error correction code the selection of which is not critical to the invention.
  • the receiver side circuitry does the same function in all the decomposed method embodiments. That function is to decode the incoming data to determine the identity of the attribute data which was selected for encoding into the main data error check symbols. This is done, in the preferred embodiment with a foreshortened error detecting code, by concatenating sufficient leading zeros in the leading bit positions of D' to make up one input word to an encoder. The encoder then generates Pd' in the same manner as Pd was generated on the transmitter side. The value of Pd' is then supplied as one input to a partial syndrome generator which generates a partial syndrome by performing an exclusive-or logical operation between P' and Pd' .
  • a separate circuit then supplies each of the possible values for Pa, i.e., one Pa is supplied for each member of the attribute data class .to a syndrome generator.
  • the values for Pa are supplied from a look-up table. In other embodiments, they may be calculated with an encoder.
  • the syndrome generator then generates a syndrome by performing an exclusive-or logical operation between each of the possible values for Pa and the partial syndrome. Because of the properties of the exclusive-or logical operation and the methodology of generating the various input data quantities, the syndrome which consists of all zeros identifies the Pa which was encoded into Pd, and, thus, identifies the particular attribute data which was selected for transmission.
  • the main data D' and its associated attribute data A are then ready for use in display, signal processing or any other manner desired by the user.
  • the inverse alpha operator would be defined and unique as can be seen from the truth table of an exclusive-or function assuming that Pd and Pa and P are all one bit binary data fields.
  • the inverse alpha operator could be applied between P' and Pd' to derive Pax in one operation.
  • the transmitter side encoder has as its input field a code word comprised of D concatenated with A where A is in the leading bit position and occupies the most significant bit positions of the input code word D (foreshortened error detection code embodiments). In alternative embodiments, A may be placed elsewhere in the input word to the encoder such as in the least significant bit positions.
  • the encoder then generates the error check symbols P from the single input word of D concatenated with the selected A. In linear error correction codes, P will be equal to the error check symbols Pd mathematically combined with the error check symbols Pa.
  • the encoding process may use an alpha operator which can be any mathematical operation such as addition, subtraction, multiplication, division or any combination of the above may be used. Further, any logical operation may used such as AND, OR or exclusive-or or any combination of mathematical and logical operations ⁇ may be used.
  • alpha operator can be any mathematical operation such as addition, subtraction, multiplication, division or any combination of the above may be used.
  • any logical operation may be used such as AND, OR or exclusive-or or any combination of mathematical and logical operations ⁇ may be used.
  • direct method embodiments can use either linear error correcting codes or nonlinear error correcting codes. For direct methods using linear error correcting codes with the alpha operator restricted to
  • the receiver side circuitry can directly decode the identity of Pax using the inverse alpha operator.
  • the receiver side circuitry can directly decode the identity of Pax using the inverse alpha operator.
  • the trial and error method of decoding will be necessary to eliminate any ambiguity as to the identity of Pax.
  • the exclusive-or logical operation is used for the
  • each of the possible A values from the class of attribute data members is concatenated into the leading bit positions
  • This field of A and D will then be the input code word for another encoder.
  • This encoder calculates the error check symbols P" from the input word D' concatenated with each possible A. There will be an error check bit value P" for each of the possible A values.
  • the values of P" are supplied to the input of a syndrome generator which generates a syndrome for each P" by performing an identity comparison between all P" so generated and P'.
  • the identity test is the exclusive-or logical operation between each P" and P', the received version of the modified error check symbols.
  • the syndrome which comes out all zeros identifies the particular value of A which was selected for encoding on the transmitter side.
  • the apparatus of the invention to implement the decomposed method may be either serial or parallel in architecture or some combination of the two. That is, the transmitter and receiver sides may both be purely serial or purely parallel or somewhere between the two extremes. Further, the transmitter side may be serial and the receiver side may be parallel or vice versa.
  • Both the decomposed and the direct methods have pure serial and pure parallel which are described in detail in the detailed description below. That is embodiments of both types of methods which are serial on both the transmit and receive sides or parallel on both the transmit and receive sides are described below. For brevity, these embodiments will not be summarized here since those skilled in the art can appreciate many variations of the decomposed and direct methods described above.
  • the apparatus for the direct method may also be implemented in either a serial or parallel architecture or some combination of the two.
  • the transmitter side and the receiver side may each be serial or each be parallel, and each may have some degree of parallelism somewhere the two extremes. Further, the transmitter side may be serial and the receiver side may be parallel or vice versa.
  • Figure lA' is a conceptual flow diagram of the decomposed method of practicing the invention where the alpha operator is the exclusive-or logical function.
  • Figure IB is a conceptual flow diagram of the changes to the embodiment of Figure 1A on the receiver side where the alpha operator is selected such that the inverse alpha operator is defined and unique.
  • Figure 3A shows an embodiment of the decomposed method having serial data evaluation architecture on the receiver side.
  • Figure 3B is a conceptual flow diagram of the changes to the embodiment of Figure 3A on the receiver side where the alpha operator is selected such that the inverse alpha operator is not defined or not unique.
  • Figure 3C is a conceptual flow diagram of the changes to the embodiment of Figure 3A on the receiver side where the alpha operator is selected such that the inverse alpha operator is defined and unique.
  • Figure 4A is parallel data evaluation architecture machine for practicing the decomposed method of the invention where alpha is selected to be the exclusive-or logical function.
  • Figure 4B is a conceptual flow diagram of the changes to the embodiment of Figure 4A on the receiver side where the alpha operator is selected such that the inverse alpha operator is not defined or not unique.
  • Figure 5A is a direct method, serial data evaluation architecture machine for practicing the invention where alpha is selected to be any general alpha operator including the exclusive-or logical operation.
  • Figure 5B is a conceptual flow diagram of the changes to the embodiment of Figure 5A on the receiver side where the alpha operator is selected such that the inverse alpha operator is defined and unique.
  • Figure 6A is a parallel data evaluation architecture machine for practicing the direct method of the invention where alpha is selected to be any general alpha operator including the exclusive-or logical operation where the inverse alpha operator is not defined or not unique.
  • Figure 6B is a conceptual flow diagram of the changes to the embodiment of Figure 6A on the receiver side where the alpha operator is selected such that the inverse alpha operator is defined and unique.
  • Figure 7A is a flow diagram of a general method of practicing the decomposed method of the invention using any alpha operator including the exclusive-or logical operation where the inverse alpha operator is defined and unique.
  • Figure 7B is a flow diagram of the changes to the method of Figure 7A where alpha is selected such that the inverse alpha operator is either riot defined or not unique.
  • the first steps in the decomposed method of the invention are to compute the error check symbols Pd for the main data and to compute the "error" check symbols Pa, also referred to as the attribute check symbols, for a selected member of the class of attribute data members.
  • the Pa check symbols are not actually used to detect and correct errors in the attribute data. Indeed, they may be the attribute data itself in some embodiments or they may be some encoding of the attribute data into a code word Pa uniquely identifying the attribute data with which it is associated.
  • Pd is calculated by concatenating leading zeros into the unused bit positions of the main data D as shown at 20.
  • leading zeros are not necessary to define the magnitude of D, and therefore this step may be omitted.
  • the same general comment applies to all steps in all methods described herein for concatenating leading zeros and the circuitry described herein to implement such steps. Such steps and circuitry may be omitted. Any step defined herein which concatenates trailing zeros and any circuitry which implements such a step in any of the embodiments described herein may not be omitted however since trailing zeros are necessary to define the magnitude of a digital number.
  • a sufficient number of leading zeros are added to the main data to make the concatenation of the leading zeros plus the main data D plus the error check symbols Pd which will be generated from the main data equal the number of symbols in one word.
  • This concatenation is shown at 22.
  • Pd is calculated by inputting the main data D with its concatenated leading zeros to a conventional encoder 24.
  • This encoder implements any error correction code. There are certain advantages in speed of operation in using linear error correction codes and restricting the alpha operator to those operators for which the inverse alpha operator is defined..
  • the principal advantage is that for a defined inverse alpha operator, the identity of Pax can be immediately known on the receiver side from the states of Pd' and P' simply by applying the inverse alpha operator between these two quantities. If the inverse alpha operator is not defined or is not unique, then the receiver side circuitry must go through a trial and error process of elimination until the true Pax is found. This takes extra time.
  • the invention may be practiced with either linear error correction codes where the alpha operator is not restricted to alpha operators where inverse alpha is defined and unique or with nonlinear error correction codes where inverse alpha is not defined or not unique.
  • An example of an alpha operator which does not have a defined and unique inverse alpha operator is the AND logical operator. The truth table for an AND alpha operator operating on one bit Pd and Pa fields is given below.
  • the alpha operator is the AND logical operation converting the Pd and Pa one bit fields to the one bit P fields in the right column.
  • the inverse alpha operator would be the logic function between P and Pd which yields Pa in the right hand column which is shown below.
  • Inverse alpha operator not unique Pd P Pa 0 0 0 0 0 0 1 1 0 0
  • ambiguity problem becomes less significant when the size of the Pd, Pa and P fields becomes larger. Further, in general it is true that the number of members in the attribute data class is far fewer than the total number of combinations which can be made with the number of error check bits in the Pd field. The unused combinations can be used to differentiate between the members of the attribute data class which lie in an ambiguous subset. Thus ambiguity can be removed effectively for any alpha operator such that the invention can be used with any alpha operator, any number system and any error correction code.
  • the encoder 24 may be a conventional parity generator comprised of a plurality of exclusive-or gates connected in such a manner as to implement the division by a unique generator polynomial said division operation being characteristic of CRC check bit generation.
  • the error check symbols generated by the encoder 24 would then be the coefficients of the remainder polynomial resulting from this division.
  • the invention is not limited to number representation in the binary system. Any number system which can be linearly mapped to the binary form for which there is defined the logical operation and/or the mathematical operations of the alpha operator or the exclusive-or logical operation used in some other embodiments described herein will suffice.
  • the attribute data A and the main data D may be represented in any code for which the necessary mathematical and/or logical operations are defined.
  • the Reed-Solomon code is an example of one such acceptable code which happens to be a linear code. Whereas binary code has only two symbols which are defined, i.e., 0 and 1.
  • Reed-Solomon code can have any finite number of symbols equal to a prime number raised to any finite power.
  • One such code has sixteen defined symbols. Each of these symbols maps directly by a mathematical relationship to a nibble of four binary bits.
  • the binary number representation will be used for convenience and the term bits or symbols may be used interchangeably to mean the components in the code "alphabet" which can be concatenated into code words.
  • the error check bits for the selected member of the class of attribute data members may be supplied in the method of Figure 1 in any one of many different ways. For example, there may be one bus 27 which supplies each of the members of the attribute data class in a serial stream. The selected member. Ax. may then be picked from the stream by suitable apparatus and converted to the Pax bits.
  • bus 27 may represent a plurality of buses each of which carries one member of the class Al...Ax...An.
  • Suitable apparatus to select the bus carrying Ax such as a multiplexer may be used to supply Ax for encoding into Pax.
  • the apparatus that does the selection in either of these two architectures may be either a bit serial or bit parallel architecture or any combination of architecture between these two extremes. The design of such a functional unit for any such combination is well known to those skilled in the art.
  • any time multiple units of data such as the members of the attribute data class must be handled in any of the trial and error embodiments to be defined below
  • the multiple members of the attribute data class may be supplied in a serial data stream in time sequence or simultaneously in parallel on a plurality of data paths.
  • the apparatus that handles data at any point in any of the embodiments defined or pointed to herein may be bit serial, bit parallel, byte serial, byte parallel, word serial, word parallel, group serial or word parallel or any architecture between the serial and parallel extremes.
  • the step of supplying the proper error check 5 bits corresponding to the selected member Ax from the attribute data class is symbolized by block 28 in Figure 1.
  • the error check bits Pa may be calculated using an encoder such as the encoder 24 or using an 0 encoder which implements another error correction code other than the one implemented by the encoder 24. In such an embodiment, trailing zeros would be concatenated with the selected attribute data member starting at the least significant bit end.
  • the step 28 may represent any encoding of the attribute data 26 into- a code word Pa of a length equal to or less than the length of the length of the Pd field.
  • the step 28 may represent the process of supplying the attribute data itself for encoding with the Pd symbols to generate the P symbols although this method is not preferred.
  • the resultant input code word is shown at 26.
  • the output code string would be the attribute error check symbols or attribute check bits Pa.
  • the error check bits Pa could be supplied by a look-up table where the input address corresponded to the selected- member of the ' class of attribute data members.
  • each such member in the attribute data class there would be stored in the look-up table the corresponding error check bits which would result if each member of the attribute data class were encoded to its corresponding error check bits by an encoder such as that shown at 24 in Figure 1.
  • Another embodiment would use a multiplexer having one input port for each member of the class of attribute data members. Each input port would be hard wired with the bit pattern of the error check bits for its corresponding member of the attribute data class. A select signal would then control which of the inputs was connected to the output port to thereby control the multiplexer to supply the error check bits for the particular selected member of the attribute data class.
  • the process of modifying the error check bits for the main data with the error check bits from the selected member of the attribute data class is symbolized by the alpha operator shown at 30.
  • the binary number system is used.
  • the alpha operator is the exclusive-or logical operation, but in other embodiments, any alpha operator may be chosen.
  • Both the error check bits for the main data Pd and the error check bits for the selected member of the attribute data class Pa are data fields of the same predetermined number of bits. The number of bits is selected by the user, depending upon the reliability needs and other characteristics of the system in which the invention will be used.
  • the methodology of the invention depends upon whether inverse alpha is defined or is not defined or not unique.
  • the first step in all alternate embodiments of Figures 1A, IB and 1C is to concatenate a string of leading zeros into the most significant bit positions of the received data D' , as symbolized by the exclusive-or logical operation at 34.
  • leading zeros are not significant in defining the value of a digital number, and thus, this step may be omitted if desired without changing the result.
  • the output of the exclusive-or operation at 34 is the bit pattern shown at 36.
  • the bit pattern at 36 like the bit pattern at 22, is one word in length for embodiments utilizing foreshortened error correction codes.
  • the portion of the bit pattern 36 comprised of the received main data D 1 and the leading zeros are applied as the input string to an encoder 38.
  • This encoder 38 must implement the error correction code implemented by the encoder 24 on the transmitter side, and outputs the error check bits Pd'.
  • the exclusive-or logical operation is used for the alpha operator, and a trial and error method is used to determine the identity of Pax.
  • Pd' and each of the members of the class Pal...Pan are combined in the exclusive-or logic operation symbolized at 40 to yield a plurality of P" fields.
  • the members of the class Pal...Pan are input on the bus 44.
  • the members of the class Pal...Pan may be supplied for trial and error evaluation either in serial form on the bus 44 or the bus 44 may represent a plurality of parallel buses each of which carries one member of the class Pal...Pan.
  • the unit 40 may be designed in either a serial or parallel architecture or any architecture between the two extremes. For example, if the incoming data is a serial bit stream,. Pal may be assembled in a serial-in-parallel-out shift register and the parallel outputs may all be simultaneously combined in a plurality of exclusive-or gates each of which combines one bit of the Pa field with the corresponding bit of the Pd' field. Likewise, if the input stream is arriving serially, the unit 40 could be comprised of a serial-in-serial-out shift register.
  • this identity operator can be exclusive-or gates since the exclusive-or of two identical code words is always zero.
  • the syndromes are then examined to determine which is zero as symbolized by step 50.
  • the zero syndrome corresponding to Pax causes the circuitry symbolized by step 52 to output the correct attribute data Ax as symbolized by data path 51.
  • FIG IB there is shown an embodiment where the inverse alpha operator 39 is defined and unique. All the functions prior to the function 43 are the same as described above with reference to Figure 1A and will not be discussed here. in this embodiment, the identity of Pax can be directly determined by performing the inverse alpha operation between Pd' and P' to compute Pax as symbolized at 43.
  • Figure 1C shows an alternative embodiment where the inverse alpha operator is not defined or not unique, and a trial and error method must be performed.
  • the unit 40 combines each member of the class Pal...Pan with the field Pd' using the alpha operator instead of the exclusive-or logical operation to yield a plurality of partial syndromes P on the data path 47.
  • These P" data fields are each combined with the P' field by the identity operator 49. The results of this operation determine which P" corresponds to Pax.
  • the identity detect circuitry 50 is a zero detector which receives the output of the exclusive-or operation on data path 53 and outputs Pax on data path 51 to the output circuit 52 which outputs the correct attribute data.
  • the alpha operator is the exclusive-or logical operation and a trial and error decoding method is used.
  • the members of the class Pal...Pan may be supplied either concurrently or in serial fashion as will be shown in more detail below.
  • the general methodology which is utilized on the receiver side for the trial and error embodiments where the exclusive-or logic function or where inverse alpha is not defined or not unique is to supply the error check bits for each possible member of the class of attribute data members to a syndrome calculation apparatus.
  • a syndrome is calculated by performing an exclusive-or logical operation or the alpha operation between Pd' and the error check bits for the attribute data member.
  • the presyndromes are then compared one by one to the P' field by an identity operator which preferably is an X-OR gate to generate a plurality of syndromes.
  • FIG. 2A there is shown a conceptual flow diagram for the direct method of practicing the invention where the alpha operator is the exclusive-or logical operation.
  • the algorithm is described in terms of a direct method, the steps shown in Figure 2A also work for the decomposed method.
  • the direct method differs from the decomposed method in the sense that, on the receiver side, the decoding process requires an error check bit calculation for every member of the attribute data class when concatenated with the D' string, whereas in the decomposed method, the error check bits for attribute data may be looked up.
  • the direct method on the transmitter side starts with a concatenation of the selected member of the class of attribute data members into the unused, most significant bit positions left open by the main data in foreshortened linear error detection code embodiments (the attribute data bits may also be put in the least significant bit positions, as long as the same thing is done on the receiver side).
  • the resultant bit string is as shown in 54 in Figure 2A.
  • String 54 is used as the input string for encoder 56.
  • the encoder 56 can be any encoder which implements any error correction code.
  • the encoder 56 calculates the error check bits P directly from the input bit string 54. This operation is equivalent to an embodiment wherein a separate calculation of the error check bits Pd on the main data D and a separate calculation of the error check bits Pax on the selected member of the class of attribute data members is performed.
  • the error check bits Pax for the attribute data would then be encoded into the error check bits Pd for the main data by performing a bit-for-bit exclusive-or in the encoder 56 as symbolized by the alpha operator 76.
  • the alpha operator 76 may be either of the three types of alpha operators defined above in the discussion of the decomposed method, and the variations on the receiver side will be detailed below in connection with the discussion of Figures 2B and 2C.
  • the direct method then has similar alternate embodiments to those discussed above with reference to the decomposed method depending upon which type of alpha operator was chosen.
  • the arithmetic logic unit could then perform addition, subtractions, multiplication, or division, and/or any logical operation or any combination thereof between the Pd and pax bits. Each of these different types of mathematical or logical operations would result in a different bit pattern for the modified error check bits P.
  • modified error check bits P are generated, they are concatenated with the main data string on the least significant end thereof.
  • the main data D and the modified error check bits P are then transmitted as shown at 60 and 62 in Figure 2A.
  • Some embodiments to be discussed below may have separate error correction circuits to safeguard the integrity of this transfer. These so called super channels can be used in any of the embodiments, and will be discussed below.
  • the preferred embodiment shown in Figure 2A uses the exclusive-or logical operation for the alpha operator in a binary number system because the exclusive-or operation is simple to implement with one or more exclusive-or gates, and because it does not change the number of bits in P compared to the number of bits needed to represent Pd or Pax.
  • the bit string 64 may or may not have errors introduced therein during the transmission process. It will probably not have errors if a super channel is used especially if the number of transmission errors does not exceed the error detection and correction ranges of the error correction code used in the super channel. If there are errors in the string 64 resulting from transmission, the invention will not work properly.
  • the first step in calculating the plurality of P" presyndromes is the supplying of each member of the attribute data class Al...An for concatenation with the bit string 64.
  • An attribute data supply step 66 performs this function by supplying each member of the class of attribute data members on bus 68.
  • the attribute data class members may be supplied serially or in parallel format, and the concatenation apparatus symbolized by the operator 70 may handle the data in serial or parallel form or some compromise between the two extremes.
  • the attribute data on bus 68 is supplied for concatenation into the unused most significant bit positions left open by the received main data D' . This is done by performing an exclusive-or operation symbolized at 70, but this could be any other concatenation operation.
  • the function of the operator 70 is to concatenate the attribute data A the D' and P' bit strings.
  • the resultant output string is as shown at 72.
  • Each presyndrome is calculated as follows in the trial and error embodiments where alpha is the exclusive-or logic operation.
  • An encoder 74 which implements the same error correcting code and the same alpha operator as implemented in the encoder 56 and as symbolized by the operator 76, is used on the receiver side to calculate a plurality of error check bit patterns P" using as an input string for each such P" the concatenated string D' and one of the members of the class of attribute data Al...An. This encoding is symbolized at 78.
  • the encoder 56 is identical to the encoder 74.
  • the P" error check bit string is equal to the error correction string which would result if the D' string were passed through the encoder 74 alone, i.e.. with no attribute data concatenated therewith, and then the resulting error check bits Pd' were exclusive-ored with the error check bits Pa which would result from passing a member of the attribute data class through the encoder 74 alone.
  • the encoding process performed by the encoder 74 must be identical to the encoding process performed by the encoder 56.
  • D' will be equal to D.
  • Pd' will be equal to Pd on the transmitter side, and it follows that P" will be equal to P.
  • the syndrome calculation symbolized by unit 80 in Figure 2A is the exclusive-or logical operation between the received, modified error check bits P' and the P" error check bits generated by the encoder 74. If there were no errors in transmission, P' would be equal to P and P would be equal to P". It follows, therefore, that P' will equal P", and that the syndrome consisting of the result of an exclusive-or logical operation between P' and P" would be a string of all zeros. That is only true, however, when the attribute data which was encoded into the P" error check bits on the receiver side was the same attribute data Ax which was encoded by the encoder 56 into the error check bits P.
  • the correct operation of the attribute data recovery method of the invention relies upon the assumption that D' and P' were received correctly and are equal to D and P. If an error does occur in the transmission of either T> or P, then an all zero syndrome will not result even when the proper member of the attribute data class is selected for decoding on the receiver side. Thus the invention is most useful in systems wherein the occasional inability to recover the attribute data will not be fatal. Generally in systems such as color television digital transmission or digital signal processing systems, there is a great deal of redundancy in data from one scan line to the next. In such systems the scheme of the invention works quite well because of the redundancy, and no extra steps to improve reliability need be taken.
  • the input data for the encoder 86 would be the string comprised of the main data D and the modified error check bits P.
  • the encoder 86 implements any error correction code. This code may or may not be the same as implemented by the encoders 24 and 38 in Figure 1A.
  • the super channel error check bits p* will be transmitted and/or recorded with the main data D and the modified error check bits P.
  • the error check bits P* are received and take the form P*', as shown at 90.
  • a decoder 92 in the super channel circuitry takes as its input string the P* » error check bits, the received main data D' and the received, modified error check bits P'.
  • Figure 2A shows, in phantom, super channel circuitry which performs the same function in the same manner as the super channel circuitry described in Figure 1A.
  • the method employed in the super channel circuitry of Figure 2A also is identical to the method employed in Figure 1A.
  • FIG. 2B there is shown one trial and error type embodiment for a general alpha embodiment where inverse alpha is undefined or not unique. Only the data evaluation or decoding functions are shown in Figure 2B which are different from those shown in Figure 2A all other steps being the same.
  • the data evaluation process of Figure 2B involves a trial and error decoding operation which calculates the P" fields using Pd' and each of the members of the class Al...An.
  • the first step in this presyndrome P" calculation process is the supply of each member of the attribute data class Al...An or each member of the ambiguous subset of the attribute data class for the particular conditions of Pd' and P'.
  • the attribute data class members so supplied are concatenated by a functional unit not shown, i.e..
  • the encoder 74 to generate a plurality of presyndromes P".
  • the encoder 74 implements the same alpha operator as the encoder 56 on the transmitter side.
  • each presyndrome P" will be the result of one of the members of the class Pal operating on the Pd' field through the alpha operator.
  • the presyndrome between Pax and Pd' will be identical to P'.
  • the next step therefore is to test all the presyndromes for identity with the P' field.
  • This function is represented by the identity operator unit 75 which generates a plurality of syndromes each representing the results of the identity test between one of the presyndromes and the P 1 field as shown at 77.
  • the syndromes are tested to determine which indicates P' is equal to P" thereby identifying Pax and Ax.
  • the identity of Pax is output to a functional unit 84 which outputs the corresponding Ax field.
  • Embodiments of the invention can be arranged to implement data handling and data evaluation in either a serial or a parallel architecture or any combination architecture between these two extremes.
  • a degree of parallelism from one bit to a group of multiple bit words can be selected for the architecture, and the degree of parallelism can be different at different locations within the data transmission system. The most suitable degree of parallelism depends upon a number of factors, such as circuit complexity, data processing time, cost and the like.
  • Data handling and data evaluation of different or of the same architectures can be combined anywhere in any of the embodiments.
  • serial architecture trial and error embodiments the calculation for each attribute data member will be performed seriatim.
  • a syndrome is calculated for each member of the attribute data class concurrently in parallel paths where there is one path for each attribute data member.
  • only one path may be used where the single path is used to calculate the syndrome for the first member of the attribute data class, and then it is used again to calculate the syndrome for the second member of the attribute data class.
  • Figure 3A there is shown a serial data evaluation architecture for one embodiment of an apparatus to implement the decomposed method of Figure 1A where the alpha operator is the exclusive-or logical operation.
  • the transmitter side circuitry is shown on the top half of the figure.
  • the concatenator 94 can take many different forms. Since the number of main data bits will be known for every input string to the encoders of the system, the concatenator 94 may simply be circuitry which counts the main data bits arriving on the line 96 and begins filling the bit positions (or time slots) on the main data input line 98 with zeros after the most significant main data bit arrives at the concatenator 94 and is output on the line 98.
  • the concatenated bit string which will be input to the encoder 24 is shown at 100.
  • the structure of the encoder 24 is well known to those skilled in the art, and is totally dependent on the particular error correction code which is selected by the user for use in implementing the method of Figure 1A.
  • the encoder 24 accepts the main data on the line 98 in serial format, and translates the main data into the corresponding main data error check bits Pd, which are then output in serial format on line 102.
  • the error check bits Pax for the selected attribute data Ax are supplied by the error check bit supply circuit 28.
  • This error check bit supply circuit 28 can take many forms.
  • a look-up table 104 is used to store the error check bits Pa for each of the members of the class of attribute data. These bits Pa may be the result of a calculation using the same or a different error correction code from the error correction code which was used to calculate the Pd bits.
  • Each input would be coupled to a hard-wired bit pattern for the address of the error check bits for a particular one of the members of the attribute data class.
  • a select signal on a bus 110 from user-defined control logic 112 would control the selection by the multiplexer 110 of the particular one of its inputs which is coupled at any particular time to the output bus 106.
  • the error check bit supply circuit 28 would consist simply of a multiplexer like the multiplexer 110.
  • each input corresponding to a member of the attribute data class would be hard wired with the bit pattern for the particular error check bits Pa corresponding to that member of the attribute data class.
  • the select signal 110 would then cause the selected one of the attribute data class error check bit patterns to be coupled onto the bus 106.
  • the bus 106 would then be coupled to the alpha operator circuitry 114.
  • the alpha operator selected may be any alpha operator, and the receiver side circuitry will depend upon the alpha operator selected. In the preferred embodiment, the alpha operator is an exclusive-or circuit.
  • the error check bit supply circuit 28 would have an encoder such as the encoder 24 substituted for the look-up table 104.
  • the multiplexer 110 would have its input coupled to the actual bit patterns of the attribute data class members.
  • the select signal 110 would then select one attribute data member for application via the bus 106 to the input of the encoder.
  • the encoder would then calculate the corresponding error check bits Pax for the selected attribute data member, and apply these error check bits to the bus 108 as an input to the exclusive-or circuit 114.
  • start and stop bits or delimiter characters may also be present to signal the start and end of each main data string. Whether or not these delimiters are used depends on the user's application, and their use is not critical to the invention. Further, the use of the bit stripper 124 is not critical to the invention. The transmission of the leading zeros, along the with the main data D and the modified error check bits P over the link 32 will not cause any disruption of the operation of the system. However, stripping the leading zeros from the data to be transmitted is desirable, since transmission of these bits would consume valuable bandwidth unnecessarily.
  • the received main data D' and the received modified error check bits P' are input to a concatenator 128 on a bus 130.
  • the concatenator 128 also receives a string of zeros on a bus 132, and serves to reinject the leading zeros in the unused bit positions left open by the shortened main data D' .
  • this may be desirable for certain structures of encoders, it is not necessary in some embodiments as mentioned previously. Adding the leading zeros may be necessary in some embodiments with certain encoder structures since encoders such as the encoder 24 and the encoder 38 are designed in the prior art to accept input strings of a fixed length generally equal to word length of the system in which they are used.
  • bit stripper 124 If an input code word is shorter than the fixed length, then the unused bit positions should be tied to a logic zero to prevent unknown voltages at floating inputs. Such floating inputs could render the calculated error check bits unreliable. If the bit stripper 124 is not used on the transmitter side, then the concatenator may be eliminated.
  • the output bit string from the concatenator 128 is shown at 134.
  • This string is input to a bit stripper 140 which separates the 0-D' string from the P' string and outputs each string on a different bus.
  • the O-D' string is input to an encoder 38.
  • the encoder 38 implements the same error correction code as the encoder 24 on the transmitter side, and performs the same function in that it calculates Pd' from D' . If there are no errors during the transmission and/or recording of the main data D. or if a super channel was used for the transmission link 32, then D' will equal D and Pd' will equal Pd.
  • the operator 135 is an exclusive-or circuit which generates a partial syndrome P' X-OR Pd' on the bus 142.
  • the select signal on the bus 152 may be generated in any one of a number of different ways. The exact manner in which it is generated is not critical to the invention.
  • One way of generating a select signal which causes sequential coupling by the multiplexer 148 of each of its inputs to its output is through use of a counter 154 having its count input driven by a clock 156.
  • the counter 154 converts the stream of binary clock pulses from the clock 156 into sequential activations of each of a plurality of outputs where each outputs comprises one line in the bus 152.
  • the multiplexer selects a corresponding one of its inputs for coupling to its output bus 150.
  • the frequency of the clock 156 must be set such that the select signal on the bus 152 causes each address to be output on the output bus 150 for a sufficiently long time to allow the ROM 146 to access the corresponding error check bits and output them on the bus 147.
  • Another way of implementing the circuit 42 is to dispense with the ROM 146 and to substitute an encoder such as the encoders 24 and 38.
  • the inputs of the multiplexer 148 would then be hard wired to the bit patterns of the individual members of the attribute data class themselves.
  • a select signal 152 would then cause each individual member of the attribute data class to be input via the bus 150 to this encoder.
  • the encoder would calculate the corresponding error check bits for each attribute data class member arriving at its input and output a stream of error check bit strings Pal through Pan on the bus 147.
  • the exclusive-or or other decoding circuit 144 always functions in the same way.
  • the purpose of the exclusive-or circuit 144 is to generate the final syndromes SI through Sn which are used to determine which member of the attribute data class was encoded in the modified error check bits P on the transmitter side.
  • the exclusive-or circuit 144 outputs the stream of syndromes on a bus 149.
  • Each of the syndromes SI through Sn is calculated by performing a bit-for-bit exclusive-or operation between one of the error check bit strings Pal-Pan and the partial syndrome on bus 142.
  • the number of bits in the partial syndrome on the bus 142 is equal to the number of bits in the bit strings Pd' and P', since a bit-for-bit exclusive-or operation was used to generate the partial syndrome, and since there are no carries in the exclusive-or logical operation. Further, the number of bits in each of the error check bit strings Pal through Pan is also equal to the number of error check bits in the partial syndrome in bus 142. Each syndrome should then consist of the number of bits corresponding to the number of bits in the partial syndrome. The only syndrome in the steam of syndromes on the bus 149, which is all zeros, will be the syndrome corresponding to the error check bits Pax.
  • the zero-detect circuit 50 can be a simple NOR (or NAND) gate connected to the outputs of a serial-in parallel-out shift register. This shift register would shift in the serial format bits of each syndrome until all bits had arrived and then output all bits of the syndrome simultaneously in parallel format to the inputs of a NOR gate. If the inputs to the NOR gate wore all zeros, the NOR gate output would change states.
  • the output circuit 155 could be a look-up table similar in design to the error check bit supply circuit 42, except that the ROM in the output circuit would contain the attribute data member bit patterns themselves rather than the error check bits corresponding thereto.
  • the output on the bus 151 on the zero-detect circuit could be used to gate the select signal on the bus 152 into the output circuit 155 such that only the select signal corresponding to the syndrome which was all zeros would actually cause the output circuit 155 to retrieve an attribute data member from its ROM. Similar variations in the design of the output circuit 155 may be made, as were described earlier herein with respect to the error check bit supply circuit 42.
  • the alpha operator is any general alpha operator and is not defined or not unique where the decomposed method with serial data evaluation is used.
  • the Pd' string on bus 136 is applied to an alpha operator circuit 137 which receives as another input the stream of error check bits Pa in the class Pal...Pan on the bus 147.
  • the alpha operator outputs a series of P" fields on a bus 139 which is coupled to an identity operator 141.
  • the identity operator also receives as an input the P' bit string via the bus 138 and does a comparison between P' and each P" to determine if the two bit strings are identical.
  • data regarding the decoded identity of Pax is sent via bus 143 to the output circuit 154 to cause the corresponding attribute data Ax to be output.
  • the circuitry on the transmitter side may be identical, as in the embodiment shown in Figure 3A. Alternatively, it may perform the same functions as the apparatus of Figure 3A. but perform them in parallel fashion. Any number system and any error correction code can be used and any alpha operator may be selected.
  • the circuitry on the receiver side of this embodiment will, as in the case of the embodiment of Figure 3A, have to be selected in accordance with whether the inverse alpha operator is or is not defined and unique.
  • the circuitry preceding and following the identity test circuitry may be identical, as in the embodiment shown in Figure 3A, or it may be arranged to perform the same functions as the embodiment of Figure 3A. but in a parallel fashion.
  • the encoder in the circuitry 163 will generate Pd' using the same error correction code used to generate Pd on the transmitter side and will process Pd' with P' to arrive at Pax. Pax is then output on bus 164 to output circuit 166 which converts Pax to its corresponding attribute data in any known fashion.
  • the decoder circuitry 163 For trial and error embodiments using the exclusive-or logic operation for the alpha operator, the decoder circuitry 163 generates a partial syndrome comprised of P* S-OR Pd' on the bus 164.
  • the partial syndrome generated on bus 164 will be combined simultaneously in a plurality of X-OR circuits 168. 169. 170. 171 ... etc. with one member of the class Pal...Pan each member of said class being coupled to an input of the corresponding exclusive-or (X-OR) operator circuit.
  • the output of the X-OR circuits 168-171 are the syndromes which collectively identify the attribute data encoded on the transmitter side by the particular syndrome which is all zeros.
  • a single partial syndrome will be output on the bus 164 of Figure 4A, and will be coupled to the inputs of a plurality of exclusive-or circuits 168-171.
  • the error check bits corresponding to the individual members of the attribute data class will be supplied on individual buses 173. 175. 177 and 179. with each bus coupled to an input of one of the exclusive-or circuits 168-171.
  • each exclusive-or circuit 168-171 receives the partial syndrome.
  • Each exclusive-or circuit 168-171 computes a single syndrome and each syndrome corresponds to one member of the attribute data class. Only the syndrome Sx corresponding to the selected member Ax of the attribute data class which was encoded by the transmitter side will be all zeroes.
  • Each syndrome in parallel format is supplied to the input of a zero-detect circuit such as the zero-detect circuits 159-162.
  • Each zero-detect circuit has an output line, shown as lines 168-171 respectively. which carries a signal which changes state when the syndrome at the input is comprised of all zero bits.
  • These output lines 168-171 are collected in a multiline select bus 175, and are coupled to the select port of a multiplexer 178. This multiplexer serves the purpose of the output circuit 154 in Figure 3A.
  • the multiplexer 178 has a plurality of inputs with each input being assigned to one particular member of the attribute data class. Each input is hard wired to a bit pattern which represents the corresponding member of the attribute data class.
  • the select signals on the bus 175 are such that only the input corresponding to the syndrome which was all zeros will be selected for output on the output bus 180.
  • Figure 4B shows the changes in the receiver side circuitry from that shown in Figure 4A for an embodiment of the decomposed method where inverse alpha is not defined or not unique.
  • the receiver side partial syndrome generation circuitry 163 generates Pd' using the same error correction code used to generate Pd on the transmitter side. Pd 1 and P' are then output on buses 180 and 182 respectively.
  • Pd' is combined simultaneously in a plurality of alpha operator circuits 184, 186... with each member of the class Pal...Pan.
  • the results are then simultaneously compared in a plurality of identity circuits 188, 190... etc. to P'.
  • the outputs of the identity circuits collectively identify which of the class Pal...Pan is Pax.
  • This data is sent on a bus 192 to an output circuit 194 which outputs the attribute data Ax corresponding to Pax.
  • Figure 4C there is shown the changes to the receiver side circuitry shown in Figure 4A for an embodiment of the decomposed method where the inverse alpha operator is defined and unique. In this embodiment.
  • the receiver side partial syndrome generation circuits 163 generate Pd' from the received main data D' using the same error correction code used on the transmitter side.
  • the Pd' field and the P' field on the buses 180 and 182, respectively, are applied to an inverse alpha operator 193 which calculates Pax and outputs same on a bus 195.
  • An output circuit 166 receives Pax and outputs the corresponding Ax field.
  • a serial data evaluation architecture for an apparatus to implement the direct method of the invention with alpha not defined or not unique including the case where alpha is the exclusive-or logic operation.
  • a concatenator 200 receives the main data D ' in a serial bit stream on bus 202 and concatenates D with the selected attribute data Ax arriving in a bit stream on a bus 204.
  • the selected attribute data bit stream may be supplied in any one of a number of different ways as discussed previously with regard to Figure 3, and the manner in which it is supplied is not critical to the invention.
  • the multiplexer method was selected wherein each input of the multiplexer has an input which is hard wired to the bit pattern of one of the members of the attribute data class.
  • User defined control logic 206 causes the selection of the desired member of the attribute data class such that it defines some attribute of the main data D then arriving.
  • the output of the concatenator 200 is a string 208 with the selected attribute data concatenated into the unused bit positions left open by the main data D.
  • the encoder 56 receives the serial bit stream 208 and translates it into the modified error check bits P in accordance with an error correction code of the user's choice.
  • the logical operation exclusive-or is used for the alpha operator, any other alpha operator could also be used.
  • Figure 5 symbolizes the alpha operation used for the encoding by the Greek letter alpha.
  • encoder 56 in the preferred embodiment, simply operates on its input string 208 to translate the string 208 to its corresponding modified error check bits P. That is, the encoder 56 does not separately calculate the error check bits for the attribute data Ax and the main data D and then combine them using an exclusive-or logical operation. However, in alternative embodiments such a method of generation of the modified error check bits could be used.
  • the encoder 56 could take the form of two prior art encoders to generate the separate check bits Px and Pd for the selected attribute data member and the main data, respectively followed by the circuitry to combine the two strings using the alpha operator. That is, the two error check bit output strings from the separate encoders could be applied to the data inputs of an arithmetic logic unit which could be controlled to add the two strings, subtract the two strings, multiply them, divide them, or perform a logical AND or a logical OR operation between them.
  • the output from the encoder 56 or arithmetic logic unit is the string of modified error check bits P.
  • the bits P are then applied to one input of a concatenator 210.
  • Another input of the concatenator is coupled to the input of the encoder 56 to receive the bit string 208.
  • the circuit 208 concatenates the modified error check bits P to the string 208 and outputs the string 212 on a bus 214.
  • the bus 214 is connected to the input of a bit stripper 216.
  • This bit stripper 216 performs the same functions as the bit stripper 124 in Figure 3, except that it is not optional. That is, only the main data D and the modified error check bits P are to be transmitted.
  • bit stripper 216 can have any of the designs described above for the bit stripper 24, and its exact design is not critical to the invention. Those skilled in the art will appreciate that there are many different ways of fabricating such a bit stripper.
  • the output of the bit stripper 216 on a bus 218 is applied to the input of the transmission link 32 and supplies the bit string 220 to said input.
  • the transmission link 32 may include its own error-checking capabilities.
  • the input code word would be the bit string 220, and the output would be the corrected bit string 222 shown on the receiver side in Figure 5. The apparatus to do this error detection and correction in the transmission link 32 will be apparent to those skilled in the art.
  • bit strings arrive sequentially on a bus 228 at an input to the concatenator 226.
  • the shift register 224 shifts out the string 222 in a proper timed relationship to the arrival of the bit string of the attribute data class so as to form one of the bit strings 230, 231, etc. on the bus 232.
  • the shift register 224 must be recirculating.
  • a copy of the bit string 222 is shifted out to the concatenator 226 on the bus 234
  • a copy of the bit string 222 is also shifted back into the input of the shift register 224 via a bus 236.
  • a gate 238 on the bus 236 allows the bits shifted out of the shift register 224 to be shifted back into the shift register during all times when the P" error check bits for the string 222 corresponding to a single string of input data D' are being calculated.
  • the state of this gate 238 is controlled by a control signal which is designated herein as the signal "new D'" which is an active low signal which becomes a logic zero when a new bit string 222 is arriving on the transmission link 32.
  • the attribute data supply circuit 66 in Figure 2 can be implemented in many different ways, and only one of these possible ways is shown in Figure 5A. The exact manner in which the attribute data supply circuit 66 is implemented is not critical to the invention, so long as the implementation selected is capable of supplying the bit string defining each of the members of the attribute data class in a stream on the bus 228 to the concatenator 226.
  • the particular implementation selected for the embodiment of Figure 5A involves a multiplexer 240, which has a plurality of inputs with each input corresponding to one member of the attribute data class. That is, each input is hard wired to the bit pattern of its corresponding member of the attribute data class.
  • a select signal on a bus 248 controls which of the inputs of the multiplexer 240 is coupled to the output bus 228. If the bus 228 is a serial format bus, then the multiplexer 240 must contain a parallel-in, serial-out shift register as its output stage.
  • the select signal on line 248 is supplied as one active signal in a group of output signal lines from a counter 242.
  • the count input of this counter 242 is connected to.
  • the concatenated strings 230, 231 etc. are applied to the input of a bit stripper 252.
  • the purpose of this bit stripper 252 is to separate out the received error check bits P'. and to output them on a bus 254.
  • the bit stripper 252 also separates out the concatenated strings comprised of the received main data D' concatenated with each member of the attribute data class and outputs these bit strings in a stream on a bus 256.
  • the bit strings so separated are shown at 258, 259 etc.
  • Each of the bit strings 258. 259 etc. are applied to the input of an encoder 74.
  • the purpose of the encoder 74 is to generate the P" error check bits for each of the bit strings 258, 259 etc.
  • the encoder 74 implements the same error correction code implemented by the transmitter side encoder 56, and may be of the same design.
  • the encoder 74 is identical to the encoder 56, and implements the same alpha operator between the error check bits Pd' for the received data D' and the error check bits. Pal, Pa2, etc., for the corresponding members of the attribute data class. This alpha operator or sequence of mathematical and/or logical operations is symbolized by using the Greek letter alpha.
  • Figure 5A is intended to to illustrate the circuitry of both the cases where alpha is any general alpha or where alpha is the exclusive-or logical operation.
  • the alpha operator represents the mathematical and/or logical operation or sequence of operations by which the error check bits Pd' for the received data D' are encoded with the error check bits Pal, Pa2, etc. for the individual members of the attribute data class.
  • the output of the encoder 74 is a stream of bit strings PI", P2" . . .
  • Each bit string in the stream represents one P" error check bit string corresponding to the encoding of the error check bits Pa for one member of the attribute data class into the error check bits Pd' for the received data D'.
  • the bus 260 is coupled to one input of an syndrome generation circuit 262.
  • the other input of the syndrome generation 262 is coupled to the bus 254 and receives the bit strings of the received modified error check bits P*.
  • the syndrome generation circuit 262 functions to determine if P" and P' are identical.
  • the identity checking circuit 262 is an exclusive-or circuit, but in alternative embodiments, any structure that can determine equality between P" and P' will suffice for practicing the invention.
  • This syndrome will correspond to the P" in which is encoded the error check bits Pax corresponding to the selected member Ax of the attribute data class which was encoded on the transmitter side.
  • the syndrome bit stream on bus 264 will be coupled to the input of a zero-detect circuit 266, which has the same design as " the zero-detect circuit 50 in Figure 3A.
  • Its output signal ZERO on a line 268 will be coupled to the output circuit 84.
  • This output circuit 84 serves to output the particular member of the attribute data class which corresponds to the syndrome on the bus 264 which was all zeros.
  • the ZERO signal on the line 268 will remain in a logic zero state for non-zero syndromes, thereby blocking the select signals on the bus 248 from reaching the select input of the multiplexer 272 as each syndrome on the line 264 arrives.
  • the logic state of the ZERO signal on line 268 changes to a logic one. This causes the AND gate 276 to gate the select signal then on the bus 248 through to the select input of the multiplexer 272.
  • the delay circuit 270 serves to delay the select signal for a sufficient time to account for the delays in having the bit strings 230, 232 etc. pass through the encoder 74 and converted to the P" error check bit strings.
  • the delay circuit 270 should impose a sufficient delay such that the gated select signal on the line 274 selects the proper selected member Ax of the attribute data class for output on the output bus 280 at the same time that the syndrome corresponding to Ax arrives at the zero-detect circuit 266 and causes the change of state of the ZERO signal on line 268.
  • the output circuit 84 may be implemented in any one of a number of different ways, and the particular implementation shown in Figure 5A is not critical to the invention. It is only necessary that the implementation selected be able to output the proper selected member of the attribute data class corresponding to an all-zero syndrome being generated by the exclusive-or circuit 262.
  • Figure 5B there is shown an embodiment of the invention where the alpha operator implemented by the encoder 56 has a defined and unique inverse alpha operator.
  • Figure 5B shows only the differences in the receiver side circuitry from that shown in Figure 5A. As is readily seen, in all embodiments where inverse alpha is defined and unique, the receiver side circuitry is much simpler.
  • the incoming bit string 222 from the transmission link is applied to a bit stripper 281 via a bus 282.
  • the bit stripper 281 functions to strip the P' and D' bits and output them separately on the buses 283 and 284 respectively.
  • An encoder 285 receives the D' bit string on the bus 284 and generates the error check bits Pd' on a bus 286.
  • the encoder 285 implements the same error correction code as was implemented by the encoder 56 on the transmitter side (not shown).
  • the error check bit strings Pd' and P' are then applied to an inverse alpha operator circuit 287 which reverses the alpha operator encoding operation performed by the encoder 56 (not shown) to generate the Pax error check bit string on a bus 288.
  • FIG. 6A there is shown the parallel data evaluation architecture to implement the direct method of the invention using an alpha operator where inverse alpha is not defined or not unique.
  • the embodiment of Figure 6A represents the situation where alpha is any general or unrestricted alpha operator or the exclusive-or logical alpha operator. In both cases inverse alpha is not defined or not unique.
  • On the transmitter side there is very little change from the embodiment of the serial architecture shown in Figure 5A unless parallel format data handling for the encoding of Ax or Pax into the P check bits is desired to speed up operations.
  • the main data D would be processed in parallel format and the selected member Ax of the attribute data class would be input in parallel format for concatenation simply by connecting the lines carrying the selected member Ax of the attribute data class to the unused bit positions at the input of the encoder 56 left open by the foreshortened main data D.
  • the encoder 56 would accept its input string in parallel format and output its modified error check bits P in parallel format using any error correction code and any alpha operator.
  • the bit stripper 216 (not shown) would be a simple design apparent to those skilled in the ' art. Since these changes are so trivial on the transmitter side, they have not been detailed in Figure 6A, as they will be apparent to those skilled in the art
  • the transmitter side supplies a parallel format string 290 to the transmit link 32 for transmission.
  • each latch has their inputs coupled to a one of a plurality of hard-wired bit patterns each of which represents one of the members of the attribute data class Al...An. These hard-wired bit patterns coupled to each latch are on a plurality of buses symbolized by the line 294.
  • the preferred data handling architecture is parallel load latches and parallel format buses 289 and 294.
  • latch 292 After loading, latch 292 stores a concatenation of the D' and P' bits with the Al attribute data member, while latch 293 stores a concatenation of the D' and P' bits with the A2 member of the attribute data class.
  • the output of each latch 292, 293 etc. is bifurcated.
  • the D' and attribute data bits A are supplied to the input of an encoder such as the encoder 295 or the encoder 296 etc. which is dedicated to that particular latch.
  • the latch 292 has the Al bits and the D' bits connected to the input of the encoder 295. This encoder calculates the PI" error check bits using the same error correction code and the same alpha operator as were used on the transmitter side to generate the modified error check bits P.
  • Each encoder has its output coupled via a bus to an identity detection circuit such as the identity operator circuits 300, 302 etc.. Each said identity circuit functions to receive the P' and P" bit strings and to determine if they are equal.
  • the identity detect circuit is an exclusive-or circuit which calculates the syndrome of that particular member of the attribute data class by performing the operation P" X-OR P'.
  • the identity detect circuit may be any circuitry which detect when P" equals P.
  • the latch 293 has its A2 bit outputs and its D' outputs coupled to the input of an encoder 296.
  • the encoder 296 calculates the P2" error check bits.
  • the output of the encoder 296 is coupled to an identity detect exclusive-or circuit 302 which has its other input coupled to the P 1 bits either from the latch 292 or the latch 293. It does not matter from which source the P' bits come, since all latches from the receiver side store an identical copy of these P' bits.
  • the exclusive-or circuit generates syndrome S2 on its output bus 304.
  • Each exclusive-or circuit 300, 302 etc. generates the syndrome bits either in parallel or serial format and outputs them on one of the buses 303. 304 etc.
  • Each of these syndrome carrying output buses such as buses 303 and 304 is connected to the inputs of a zero detect circuit.
  • These zero detect circuits are implemented with NOR gates in the embodiment of Figure 6A.
  • the output bus 304 syndrome bits are connected to the inputs of a NOR gate 306, which serves the purpose of determining whether each bit of the syndrome S2 is a logic zero.
  • Another NOR gate 308 serves the same purpose for zero detection of the SI syndrome.
  • latches 292 and 293 there will be one latch such as the latches 292 and 293 for each member of the attribute data class.
  • encoders such as the encoders 295 and 296 and for the identity detect circuits such as the circuits 300 arid 302.
  • NOR gate for each member of the attribute data class. The output from the NOR gates such as the gates
  • select signal bus 310 which is coupled to the select input of a multiplexer 312 serving as the output circuit.
  • This multiplexer will output the member of the attribute data class which corresponds to the syndrome which was all zero bits.
  • Each input of the multiplexer 312 is hard-wired to the particular bit pattern of a selected one of the attribute data class members. The bit pattern on the select bus 310 determines which of these input ports is connected to the output bus 314.
  • FIG. 6B there is shown an embodiment of the direct method where the inverse alpha operator is defined.
  • the input bit string D' and P' on bus 289 from the super channel are applied to a bit stripper 291 which outputs D' on a bus 293 and P' on a bus 295.
  • An encoder 297 receives the D" bits and generates the error check bits Pd' using the same error correction code used on the transmitter side.
  • the Pd' and P 1 bits are then applied to an inverse alpha operator circuit 299 which generates the Pax bits.
  • the Pax bits are applied to an output circuit 301 which outputs the attribute data corresponding to the Pax bits.
  • Figure 7A there is shown a flow chart of a general method for practicing the invention using an alpha operator where the inverse alpha operator is defined and unique.
  • Figure 8A shows a general apparatus for carrying out the method of Figure 7A.
  • the first step is to calculate Pd using any error correction code, which will hereafter be referred to as ECC #1 as symbolized by step 320.
  • ECC #1 error correction code
  • Step 324 is to generate Pax, the error check bits for the selected attribute data Ax.
  • the error correction code implemented by the translator 328 may be a different error correction code, i.e., ECC #2, than was implemented by encoder 322.
  • 328 is a look-up table or multiplexer for a small class of attribute data.
  • Step 330 is the encoding step wherein Pax is encoded into Pd using any alpha operator.
  • This operation is performed by ALU 332 or some other logic programmed or controlled to carry out the desired sequence of athmatical and/or- logical operations.
  • the particular sequence is not critical nor are the number of mathematical and/or logical operations critical as long as the sequence may be reversed using only P' and pd' on the receiver side to calculate Pax.
  • the alpha operator can be any alpha operator, but if the inverse alpha operator is not defined or not unique, trial and error methods will be necessary on the receiver side to derive the identity of the encoded attribute data. Such a general method is depicted in
  • Step 336 is the calculation of Pd' from the received main data D' using ECC #1. This is accomplished in conventional manner by circuits 338 and 340 in Figure 8A. The encoder 340 must implement the same error correction code ECC #1 used on the transmitter side. Finally, the alpha sequence of math atical and/or logical operations done in step 330 is reversed in step 342, i.e., the inverse alpha operator is performed between Pd and P 1 to derive Pax. This is done using the calculated Pd' and received error check bits P'. The ALU 344 or some other logic performs this inverse alpha sequence of operations to deduce the Pax bit string.
  • the last step in embodiments where inverse alpha is defined and unique is 346 to output the Ax corresponding the Pax mathematically deduced in step 342
  • This translator uses ECC #2, and typically is a look-up table or MUX.
  • Figure 7B shows the changes in the general method of Figure 7A where the inverse alpha operator is not defined or not unique.
  • Figure 8B shows a general hardware implementation of the method of Figure 7B.
  • Pal...Pax...Pan for the members of the attribute data class. This is done using the same alpha operator as was used in the transmitter side to encode Pax into Pd to derive P. In Figure 8B. this is performed by the ALU 350 which has the Pd• field as one input and the Pal...Pan fields sequentially arriving at the other input from an attribute data check bit supply circuit 352 such as a look up table or an encoder using ECC #2. As each member of the class Pal...Pan arrives at the ALU input, the ALU 350 is controlled to perform the alpha operator sequence of .mathmatical and/or logical operations between the two input data fields so as to output a presyndrome PI", P2"...Pn".
  • Step 337 of Figure 7B therefore results in a plurality of presyndromes PI" ...Px” ...Pn" where Px" corresponds to the Pax error check bits for the selected member of the attribute data class.
  • step 339 is performed to test each of the PI"...Px” ...Pn" presyndromes against P' for identity. In Figure 8B this is performed by the identity test circuit 354. Only Px" will result in an identity determination, and this data is passed to step 341 which outputs the member of the attribute data class corresponding to the partial syndrome Px" .
  • step 341 is implemented by the reverse translator 356 which is either a look up table or some decoder which embodies ECC #2 to convert Pax to the corresponding Ax.

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Abstract

Appareils et procédés pour coder des informations d'une catégorie donnée dans la parité pour les données principales d'une autre catégorie. Les procédés et les appareils prennent, essentiellement, un élément donné d'une première catégorie de données limitées et l'enchaînent avec les données principales (20). On calcule ensuite la parité sur le mot enchaîné (24). Après transmission ou enregistrement des données principales et de la parité, on peut récupérer l'élément choisi de la première catégorie de données en comparant (48, 50) les données principales et leur parité à celles produites côté récepteur en utilisant les données principales et chaque élément de la première catégorie de données afin de créer une pluralité de syndromes. Le premier syndrome entièrement zéro identifie l'élément de la première catégorie qui a été codé dans la parité des données principales.
EP19870903098 1986-04-11 1987-04-09 Apparatus and method for encoding and decoding attribute data into error checking symbols of main data Withdrawn EP0263175A4 (en)

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US85102586A 1986-04-11 1986-04-11
US851025 1986-04-11

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US5463641A (en) * 1993-07-16 1995-10-31 At&T Ipm Corp. Tailored error protection
DE4408163A1 (de) * 1994-03-11 1995-09-14 Bosch Gmbh Robert Verfahren zum Übertragen von Daten
NL9400965A (nl) * 1994-06-14 1996-01-02 Nederland Ptt Systeem omvattende een encoder voor het op cyclische wijze coderen van woorden en omvattende een decoder voor het decoderen van op cyclische wijze gecodeerde woorden, alsmede encoder, alsmede decoder, alsmede werkwijze voor het aan een zendzijde toekennen van een op cyclische wijze gecodeerd woord aan een object en voor het aan een ontvangzijde detecteren van het aan het object toegekende, op een cyclische wijze gecodeerd woord, alsmede object voorzien van een op cyclische wijze gecodeerd woord.
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FR2735889B1 (fr) * 1995-06-22 1997-09-05 Sgs Thomson Microelectronics Circuit de calcul de syndrome
DE19626455A1 (de) * 1995-07-24 1997-01-30 Ascom Tech Ag Verfahren zur Integration von Zusatzdaten in digitalen Datenpaketen
EP1318642A1 (fr) 2001-12-07 2003-06-11 BRITISH TELECOMMUNICATIONS public limited company Annulation d'infterférences dans des récepteurs multiporteuses
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IL82176A (en) 1993-06-10
WO1987006368A1 (fr) 1987-10-22
JPS63503016A (ja) 1988-11-02
EP0263175A4 (en) 1991-11-21

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