EP0228745A2 - Rasterabtastvideosteuergerät mit einem "Cache"-Speicher, Aktualisierungs-"Cache"-Speicher für ein solches Videosteuergerät und KSR-Anzeigeterminal mit einem solchen Videosteuergerät - Google Patents

Rasterabtastvideosteuergerät mit einem "Cache"-Speicher, Aktualisierungs-"Cache"-Speicher für ein solches Videosteuergerät und KSR-Anzeigeterminal mit einem solchen Videosteuergerät Download PDF

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Publication number
EP0228745A2
EP0228745A2 EP86202315A EP86202315A EP0228745A2 EP 0228745 A2 EP0228745 A2 EP 0228745A2 EP 86202315 A EP86202315 A EP 86202315A EP 86202315 A EP86202315 A EP 86202315A EP 0228745 A2 EP0228745 A2 EP 0228745A2
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EP
European Patent Office
Prior art keywords
data
memory
controller
transceivers
registered
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP86202315A
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English (en)
French (fr)
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EP0228745A3 (de
Inventor
Craig Alden Mackenna
Jan-Kwei Jack Li
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Gloeilampenfabrieken NV
Koninklijke Philips Electronics NV
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Publication date
Application filed by Philips Gloeilampenfabrieken NV, Koninklijke Philips Electronics NV filed Critical Philips Gloeilampenfabrieken NV
Publication of EP0228745A2 publication Critical patent/EP0228745A2/de
Publication of EP0228745A3 publication Critical patent/EP0228745A3/de
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory

Definitions

  • the invention relates to a raster scan video controller.
  • video controllers are used in bit-mapped alphanumeric and or graphic image processing.
  • the invention is directed to the control logic and to circuits necessary to overcome a mismatch between the number of data lines in display memory and the number of data lines on a raster scan video controller.
  • the invention is useful for high performance CRT systems, black/white or color, especially those capable of accessing display memory to create and update an image on a video display.
  • An update data cache is a mechanism by which a CRT controller with a smaller number of data lines can update a display memory with a larger number of data lines.
  • the multiple bits accessed in a display memory cycle can be quite large both because the pixel rate is much faster than the memory time and because each pixel may be represented by a multiplicity of bits. This multiplicity is determined both by the number of bits of an actually displayed pixel, and by the number of pixels that can be displayed on a particular screen position. The latter number may relate to multiple windowing features, hidden objects in a graphics system, and others.
  • Most presently available video display systems typically include a processor, a video controller, a display memory containing a single current screen image, other system memory, and a raster scan video display.
  • the video controller In normal (steady-state) operation, the video controller continually reads out the contents of the display memory and transforms the information read out to the signalling necessary to control the raster scan beam while it is in its active display time.
  • the video controller also provides the horizontal and vertical retrace signalling at appropriate intervals, and blanking of the raster scan beam during retrace.
  • the processor also has access to the display memory, so that it can change the current screen image. This access may be "through” the video controller or "around” it.
  • the invention applies to the former type of system. In either case, use of the display memory is typically carefully controlled between updating and display accesses, to prevent breakup of the video image while it is being changed.
  • the display memory may be available for updating a) only during vertical retrace periods, or b) during both horizontal and vertical retrace periods, or c) during retrace periods plus alternating memory cycles during the active display time of scan lines. In any of these cases, however, updating of display memory typically proceeds at a rate slower than could be achieved without interference from the video controller's display accesses because of the time division among both access types.
  • Another object of the present invention is to improve performance because the update and video operations can occur simultaneously in many cases.
  • the improved video controller according to the invention is recited in Claim 1.
  • the invention also relates to an update cache for use in such improved video controller.
  • Various advantageous aspects are recited in the dependent Claims.
  • the improved video controller incorporating the present invention has two types of chips, to wit, an address module and at least one data module.
  • the chip set known as BMAP, is designed to work with an external processor which generates the instructions for the set.
  • the major function of the address module is to generate both video addrresses and update addresses, while the data modules are used to collect and integrate video data that had been read out from the display memory.
  • the video data output from the data module passes through high speed shift registers and a look-up table to the CRT display.
  • the major parts of the address module are a synchronous signal generator, a window controller, an update controller and an interface controller.
  • the address module also has the ability to update the contents of the display memory according to instructions passed from the host system. Thus, the host system does not have to access display memory when it wants to insert some characters or graphic elements into display memory. It only passes the appropriate instructions and/or data to the BMAP.
  • the structure of the display memory is related to the operating frequency of the CRT controller and the complexity of the system. This can result in a mismatch in data width between the video controller, display memory and the host system.
  • the invention provides an update cache for selective updating of a memory in a computer system wherein the data width of the memory is greater than the data width of the devices performing or controlling the updating.
  • a system usually includes one or more updating devices each having a number of signal connections on which they read and write data. For high-performance memories, this number can be less than the number of signals provided by the memory.
  • the invention provides a set of transceivers provided with register storage for each updating device, such transceivers hereinafter being called registered transceivers.
  • Each transceiver has a number of paired data signal connections, and each has control inputs which control the driving, receiving and latching of the states of these data signals. The total number of pairs in the set is greater than or equal to the number of data signals provided by the memory.
  • a set of data lines connect each data signal of the memory to one and only one data signal connection in each set of registered transceivers, such that each registered transceiver treats all of its memory data signals identically in response to its control inputs.
  • Another set of data lines connects each data signal of each updating device to a data signal of one or more registered transceivers in its set. Each pair which has one data signal connected to a memory signal has the other data signal of the pair connected to one and only one data signal of its updating device.
  • the control logic provides the appropriate control signals to select any of a numer of subsets of the set of registered transceivers associated with an updating device, each subset having a number of data signal pairs that is less than or equal to the number of data signals provided by the updating device.
  • the address module For each update access, the address module provides an address for the memory and the control signals to transfer data from memory to the set of registered transceivers or from the set of the registered transceivers to the memory. Control signals are also provided to control the transfer of data from an updating device to a selected subset of its registered transceivers or from the selected subset to the updating device. The control signals further provide the ability to latch data from an updating device in a selected subset of its registered transceivers. The control logic further provides for the simultaneous execution of a video access and a transfer between the updating device and the selected subset, where necessary and convenient.
  • the invention uses of a set of bidirectional registered transceivers plus the logic and signals to control them.
  • the interface controller of the adddress module contains the logic and directs the distribution of control signals.
  • the registered transceivers are placed between the data lines of the display memory and the data lines used for update accesses by the CRT controller or the host processor.
  • the video controller BMAP
  • the video controller can read the display memory, in a fashion similar to a normal video access and latch a whole block of data into the registered transceivers. It can then modify the data word by word. After all the modifications are completed, it can use a write cycle to write the (wholly or partially) updated data from the registered transceivers back to the display memory. Random accesses related to the updating process can be done without changing the latched data.
  • the transceivers/registers function as a data cache, with write operation being handled in a write-back fashion.
  • the registered transceivers are logically grouped according to their width vs. the width of the data accesses.
  • the total number of devices uised is determined by the display memory access width.
  • update accesses are 16 bits, so octal devices are paired, one pair being selected on any given update access.
  • the video controller has sufficient output signalling to allow update operations involving latched data to be carried out simultaneously with video accesses to memory.
  • the bit-mapped raster scan video (CRT) controller chip set illustrated in Figure 1 has an address module 10 and a multiple data module 12.
  • the address module 10 has as principal subsystem a synchronous signal generator 30, an update controller 32, a window controller 40 and an interface controller 34.
  • VCC, Gnd clock
  • CLK clock
  • Reset the following synchronization connections are provided: Vertical Sync 100 (VSsync/CSync), H(orizontal) Synch 102, CBLANK/HBLANK(ing) signal 104, alternating line/vertical blank (ACLL/VBLANK) signal 106.
  • Interface controller 34 has an attachment 108 for a system bus, and two memory interface connections 110, 112.
  • the window controller faces the data module side, and the interface controller side, the update controller only faces the interface controller side.
  • the multiplying of the data module 12 may be chosen according to needs and facilities.
  • the chip set shown provides hardware support for windows in a bit-mapped alphanumeric and graphic raster scan video (CRT) display system used in a computer system having one or more main processors and is particularly advantageous for use with multi-tasking operating systems.
  • the hardware support includes logic circuits whereby a description of a plurality of overlapping windows can be programmed into the chip set. This feature allows the CPU to maintain a multi-window bit-mapped display almost as easily as it maintains a conventional alphanumeric display.
  • video access is used to indicate an access that reads out the display memory contents to be displayed on the screen.
  • update access indicates a memory access that is used to update the contents of the display memory.
  • update operation refers to the transfer of information between the updating device and the registered transceivers.
  • each video access and update access consist of 16 to 256 bits, while an update operation always consits of a 16-bit word.
  • more extended systems could have a minimum access width of 32 bits and an update operation also relating to 32 bits.
  • the video access operates straightforwardly as follows. Upon presentation of the display address, the display memory (item 13 in Figure 2) will output the whole block of information stored at the display memory address. Then, either the data read out will go to data accumulator modules not shown or to shift registers 15 directly.
  • the BMAP address module outputs a "local address" together with the display address to select a 16-bit word from the display memory.
  • the local address is used to select the desired word from the corresponding video access. All 4 bits in the local address are needed when the BMAP is used in a system that has 8 bits per pixel and 32 pixels per video access. The 18 most significant bits in the pixel address represent the 18 bit video address.
  • a 16-bit word may consist of 16 one-bit pixels for a monochrome display system, and consist of 2 pixels for a system that has 8 bits per pixel
  • the pixel address offset can have a length that varies from 1 to 4 bits.
  • Figure 2 is a block diagram of a sophisticated system that includes an address module 10 and several data modules 12.
  • the address module generates both video addresses and update addresses, while the data modules are used to collect and integrate the display patterns that have been read out from the display memory 13.
  • the data output by the data module(s) then goes through the high speed shift register(s) 15 and color look-up table 17 to the video display 19.
  • the address module 10 also has the ability to update the contents of the display memory 13 according to the instructions passed from the host system that has one or more host processors 11 and system memory 114 (I/O has not been shown for brevity). Therefore, host processor 11 does not have to access the display memory 13 when it wants to insert some characters or graphic elements into the display memory. Instead, it only needs to pass appropriate instructions to the address module 10. To this effect, the system is provided with a data transceiver 116 for interfacing the address module to the system bus and an address transceiver 118 for interfacing address module and display memory to the system bus.
  • the address module 10 After receiving the instructions passed from the host system, the address module 10 executes them one by one just like a special purpose microprocessor. Since the whole procedure is controlled by the internal hardware, instructions can be done within a very short time. Typically the insertion speed is 5 to 50 times faster than a software procedure on the host processor.
  • the host processor can also use the address module 10 in the DMA/BitBlt mode.
  • the DMA/BitBlt procedure is similar to the character insertion procedure.
  • the data module 12 has 32 data inputs on the side of display memory 13 and 8 data outputs on the side of shift registers 15. By setting the appropriate control inputs, one ore more data modules can be used in variouus kinds of applications. All system that apply sequential memory access to increase the data read out speed, have to include the data module (or equivalent hardware) in the back-end.
  • Figure 3 shows a typical memory structure that can be used with the BMAP chip set.
  • the address module 10 can read the display memory similarly to a video access and latch the whole block of data into a set of bidirectional transceivers/registers 14. These transceivers/registers 14 (e.g. 74F646) are placed in the data path used to update the display memory, and function as an update cache for the video controller. The address module can then modify the data word by word. As the last word is modified, the address module 10 writes the updated data from the transceivers/registers 14 back to the displaymemoy 13. "Random" update accesses can also be done without latching the data. This operation is useful when a single word (e.g., "Source" data) is needed during updating.
  • a single word e.g., "Source" data
  • the number of transceivers/register devices used is determined by the display memory access width. In the embodiment described herein (BMAP) this can be from 16 to 256 bits, and four to 32 octal devices (e.g., 74F646) are used correspondingly.
  • the registered transceivers are logically grouped according to their width vs. the width of update operations. With BMAP, update operations are 16 bits, so the octal devices are paired, one pair being selected on any given update operation.
  • control logic must of course provide the control signals needed by the particular registered transceivers chosen. These may vary in detail, but basically serve to control any of the following operations:
  • the video display controller has sufficient output signalling to allow update operations of type b) and c) to be carried out simultaneously with display accesses to memory.
  • updating speed is improved if the occurrence of type b) and c) accesses are maximized.
  • update operations by the video display controller should be ordered/grouped so that several consecutive update operations fall within the same display memory access.
  • bit-mapped video display controllers access information at "source” and "destination" areas of display memory, the latter representing the actual updating of the image, the former being access to information that directs the updating.
  • BMAP adds "instruction" accesses, which also direct updating.
  • these interspersed accesses to other areas are handled by type e) and f) operations, in which the latched data in the registered transceivers 14 is not affected.
  • control information is output by four local address lines and three status lines 52 from the interface controllers 34 which are shown in Figures 1, 4 and 5.
  • the local address lines serve to select one pair of registered transceivers among the 2 to 16 pairs.
  • the status lines indicate the type of access being done, video access or update operation.
  • PLC programmed logic array
  • the information output by the control logic must include, for each update operation
  • the control logic must include a provision to write data back to display memory at appropriate times (point 5 above).
  • this is known explicitly, when the appropriate number of low order bits (1-4) of the destination local address 50 are all ones, or when the access is the last one of a block at the destination (see left OR gate 56 in Figure 5). That a new access to display memory 13 is needed for the destinaton (points 3, 4 above) is also known explicitly. It is indicated when the appropriate number of low-order bits (1-4) of the destination local address 50 are all zero, or when the access is the first one of a block of data at the destination (OR gate 58 in Figure 5). A single write operation is handled by signalling both first and last, so that the block of bits of display memory width is first read. The block is then rewritten with a number of bits equal to the update operation width, bits being changed by the video display controller or host processor.
  • the mask register 60 in Figure 5 is programmed during system initialization, to correspond to the width of display memory 13 accesses and the number of registered transceiver pairs 14. It controls how many low order local address bits must be 1 to force a write-back, and how many low order bits must be 0 to cause a new read from display memory 13.
  • a generalized variation would be to include a set of latches for the display memory address (i.e. for the high order part of the update address), plus a comparator between the contents of this latch and each new address, and a single-bit flag to record whether or not the data in the registered transceivers has been updated.
  • An algorithm of the following form can then be used to control the cache, where n is the ratio of the number of bits in the display access, divided by the number of bits in the update access.
  • the update operation is controlled by an 18-bit address, supplied by the window controller of the address module, the local address and the "TYPE2" outputs.
  • the need for the 18-bit address depends on whether the update operation requires an update access.
  • the update controller 32 generates three kinds of operations. Two of them have to access either the display memory or the system memory.
  • the hardware that is used to generate the local address and the "TYPE2" outputs is shown in Figure 5.
  • the 4-bit address port is used to output one of the local addresses stored in the PC (program counter), DC (destination counter) and SC (source counter).
  • the 4-bit mask register 60 is used to define the address boundary for the external transceivers/­registers 14. If the operation refers to the "first" word of an update access, the BMAP has to read the destination pattern from the display memory, latch the data in the transceivers/registers 14 and read the required 16 bits of the latched data.
  • the BMAP has to combine the write operation with the access that writes the whole data block from the transceivers/registers 13.
  • the BMAP performs a read-modify-­write operation to the display memory 13 direclty.
  • Table 2 shows 8 kinds of access that relate to the output controllers.
  • the three TYPE2 outputs are also connected with the external PLA 54, such that the corresponding DRAM 13 (display memory) and transceiver/register 14 control signals can be generated to do the update access.
  • Both the "TYPE2" and "local address” outputs are qualified by the LAS* (local address strobe) signal and negate by the LDTACK* (local address acknowledge) signal, as in the display memory access cycle.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Digital Computer Display Output (AREA)
EP86202315A 1985-12-30 1986-12-18 Rasterabtastvideosteuergerät mit einem "Cache"-Speicher, Aktualisierungs-"Cache"-Speicher für ein solches Videosteuergerät und KSR-Anzeigeterminal mit einem solchen Videosteuergerät Withdrawn EP0228745A3 (de)

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US81536185A 1985-12-30 1985-12-30
US815361 1985-12-30

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EP0228745A2 true EP0228745A2 (de) 1987-07-15
EP0228745A3 EP0228745A3 (de) 1990-03-28

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JP (1) JPS62183487A (de)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0447229A2 (de) * 1990-03-16 1991-09-18 Hewlett-Packard Company Logische und arithmetische Verarbeitungseinheit zur graphischen Rechnereinheit
EP0696023A3 (de) * 1994-07-18 1998-02-04 Sun Microsystems, Inc. Schnittstellensteuerung für Rasterpuffer mit Direktzugriffspeichern
WO1998043154A2 (en) * 1997-03-25 1998-10-01 Seiko Epson Corporation Method and apparatus for efficient memory-read operations with a vga-compliant video display adaptor
EP0898264A2 (de) 1997-07-04 1999-02-24 Sharp Kabushiki Kaisha Steuergerät für einen Videoanzeigespeicher
US6311239B1 (en) * 1998-10-29 2001-10-30 Cypress Semiconductor Corp. Architecture, circuitry and method for transmitting n-bit wide data over m-bit wide media

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007124200A (ja) * 2005-10-27 2007-05-17 Nittan Co Ltd 圧電振動板の取付構造

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0029517A2 (de) * 1979-11-23 1981-06-03 International Business Machines Corporation Datenverarbeitungsgerät mit Schreib-in-Pufferspeicher-Verfahren
JPS60117327A (ja) * 1983-11-30 1985-06-24 Fuji Xerox Co Ltd ディスプレイ装置
EP0150453A2 (de) * 1984-01-12 1985-08-07 Ascii Corporation Steuersystem zur Übertragung von Daten zwischen logischen Speicherbereichen
GB2159308A (en) * 1984-05-23 1985-11-27 Univ Leland Stanford Junior High speed memory system

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0029517A2 (de) * 1979-11-23 1981-06-03 International Business Machines Corporation Datenverarbeitungsgerät mit Schreib-in-Pufferspeicher-Verfahren
JPS60117327A (ja) * 1983-11-30 1985-06-24 Fuji Xerox Co Ltd ディスプレイ装置
EP0150453A2 (de) * 1984-01-12 1985-08-07 Ascii Corporation Steuersystem zur Übertragung von Daten zwischen logischen Speicherbereichen
GB2159308A (en) * 1984-05-23 1985-11-27 Univ Leland Stanford Junior High speed memory system

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN, vol. 9, no. 273 (P-401), 30th October 1985; & JP-A-60 117 327 (FUJI XEROX K.K.) 24-06-1985 *

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0447229A2 (de) * 1990-03-16 1991-09-18 Hewlett-Packard Company Logische und arithmetische Verarbeitungseinheit zur graphischen Rechnereinheit
EP0447229A3 (en) * 1990-03-16 1993-02-24 Hewlett-Packard Company Arithmetic and logic processing unit for computer graphics system
EP0696023A3 (de) * 1994-07-18 1998-02-04 Sun Microsystems, Inc. Schnittstellensteuerung für Rasterpuffer mit Direktzugriffspeichern
WO1998043154A2 (en) * 1997-03-25 1998-10-01 Seiko Epson Corporation Method and apparatus for efficient memory-read operations with a vga-compliant video display adaptor
WO1998043154A3 (en) * 1997-03-25 1998-11-05 Seiko Epson Corp Method and apparatus for efficient memory-read operations with a vga-compliant video display adaptor
EP0898264A2 (de) 1997-07-04 1999-02-24 Sharp Kabushiki Kaisha Steuergerät für einen Videoanzeigespeicher
EP0898264A3 (de) * 1997-07-04 2000-03-29 Sharp Kabushiki Kaisha Steuergerät für einen Videoanzeigespeicher
US6278467B1 (en) 1997-07-04 2001-08-21 Sharp Kabushiki Kaisha Display memory control apparatus
US6311239B1 (en) * 1998-10-29 2001-10-30 Cypress Semiconductor Corp. Architecture, circuitry and method for transmitting n-bit wide data over m-bit wide media

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EP0228745A3 (de) 1990-03-28
JPS62183487A (ja) 1987-08-11

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