EP0216595A2 - Chiffrage de données - Google Patents

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Publication number
EP0216595A2
EP0216595A2 EP86307139A EP86307139A EP0216595A2 EP 0216595 A2 EP0216595 A2 EP 0216595A2 EP 86307139 A EP86307139 A EP 86307139A EP 86307139 A EP86307139 A EP 86307139A EP 0216595 A2 EP0216595 A2 EP 0216595A2
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EP
European Patent Office
Prior art keywords
register
data
fed
registers
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP86307139A
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German (de)
English (en)
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EP0216595A3 (fr
Inventor
William Edward Brierley
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Allard Way Holdings Ltd
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GEC Avionics Ltd
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Filing date
Publication date
Application filed by GEC Avionics Ltd filed Critical GEC Avionics Ltd
Publication of EP0216595A2 publication Critical patent/EP0216595A2/fr
Publication of EP0216595A3 publication Critical patent/EP0216595A3/fr
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04K—SECRET COMMUNICATION; JAMMING OF COMMUNICATION
    • H04K1/00—Secret communication
    • H04K1/06—Secret communication by transmitting the information or elements thereof at unnatural speeds or in jumbled order or backwards

Definitions

  • This invention concerns data encryption, and relates in particular to the encryption of analogue data, such as speech, for transmission over a narrow band channel, and to the received signal's subsequent de-cryption to reconstitute the data in its original form.
  • analogue data such as speech
  • Signals transmitted over any sort of "broadcast” system can in general be picked up by anyone with the correct sort of receiver properly tuned in.
  • the signals may be desirable for the signals to be intelligeable only to the intended, and thus authorised, recipient, and to ensure this it is common to "scramble", or encrypt, the data before transmission, so that only the recipient who can approprately “unscramble", or decrypt, the signal will be able to see the data in its original plain form.
  • Such a data tranception system is said to be a "secure" system, in that the data involved is secure against eavesdroppers.
  • levels of security there are different levels of security - some encryption methods are so simple (and cheap) they can be recognised, and the appropriate de-cryption technique worked out and applied within a few minutes, while others are so complex (and expensive) they may take hours, days or even years to crack.
  • the type of encryption employed is chosen to fit the security level required.
  • the data clocked out represents a frequency-shifted version of the data that was clocked in. It is this frequency shifting that encrypts - and subsequently decrypts - the data.
  • the shifting may be up or down and that in fact it will alternate from one to the other.
  • the invention relates to the encryption, and subsequent decryption, of data, specifically narrowband analogue data typified by speech (the human voice contains almost all its output in the band fron 300 Hz to 3000Hz); purely for convenience, hereinafter the invention is described mainly in terms of its application to the encryption/decryption of speech.
  • the present invention suggests a novel system that is at heart extremely simple (and thus cheap) but can be elaborated to almost any degree of complexity. It can, therefore, be of value whether the situation requires a low or a high level of security.
  • the invention provides a data encryption/decryption method, in which: first and second registers are associated with encryption and a third and 'fourth with decryption, plain-form data is transferred sequentially through the four analogue shift registers such that data element is clocked at different clocking rates and for each register data which is fed in at one clocking rate is then fed out at another; and data is fed into a third register at the same clocking rate as it was fed out of the second register, and is fed out of the third register at the same clocking rate as it was fed into the second register; and data is fed into the fourth register at the same clocking rate as it was out of the first register and is fed out of the fourth register at the same clocking rate as it was fed into the first register, whereby, by virtue of the resulting frequency shifting, the data transferred between the second and third registers is encrypted, but when fed out of the fourth register is decrypted, and in plain form.
  • the invention provides a data encryption/decryption method in which a first register is associated with encryption and a second and a third register are associated with decryption; plain form data is fed into the first register at a series of clock rates and then fed out of the first register at a different series of clock rates and fed into the second register at the same series of clock rates it was fed out of the first register at, when the second register is full the data being fed out of the first register is fed into the third register at the same series of clock rates it was clocked out of the first register at and the data in the second register is fed out at the same series of clock rates it was fed into the first register at, when the third register is full the data being fed out of the first register is fed into the second register at the same series of clock rates it was fed out of the first register at and the data in the third register is fed out at the same series of clock rates it was fed into the first register at, and this cycle of use of the second and third registers is repeated; the series of clock rates supplied to the registers being such that;
  • analogue data encryption/decryption equipment which includes: four shift registers arranged in a sequence; tranception means whereby the output of the second register can be supplied to the input of the third register, input means for feeding plain-form data to the first register; output means for feeding plain-form data from the fourth register; clock pulse means for each register, for giving a sequence of different clock signals to the registers to control the transfer of their contents therethrough; and synchronisation means enabling the clock pulse means for each register to be synchronised one with the other, such that, when plain form data is transferred sequentially through the four registers at four different clocking rates (a) for each register, data which is fed in at one clocking rate is then fed out at another, and (b) data is fed into the third register at the same clocking rate as it was fed put of the second register, and is fed out of the third register at the same clocking rate as it was fed into the second register, (c) data is fed into the fourth register at the same clocking rate as it was fed out of the
  • the invention provides data encryption/decryption equipment which includes: a first shift register associated with encryption and a second and a third shift register associated with decryption; tranception means whereby the output of the first register can be supplied to the inputs of the second or third registers; input means for feeding plain form data to the first register; output means for feeding plain form data from the fourth register; clock pulse means for each register for giving a sequence of different clock signals to the registers to control the transfer of their contents therethrough; synchronisation means enabling the clock pulse means for each register to be synchronised one with another; and switching means enabling sections of the output of the first register to be supplied alternately to the inputs of the second and third registers, each section being one register full of data, arranged such that, when plain form data is transferred through the register at a plurality of different clocking rates, for each register data which is fed in at one clocking rate is fed out at another, data is fed into the second register at the same rate it was fed out of the first, data is fed out of the second register at
  • the data to be transferred by the inventive method - the input data - is described as plain-form data, to distinguish it from the encrypted data actually transferred between the two locations. It may, in fact, be "plain-form", and not encoded in any way except that necessary for its actual transferral through the system (as, say, voice sound is converted into electrical pulses, and then electromagnetic pulses, and back again to sound, for transception in any radio system), and indeed it is thought to be the main use of the inventive method that uncoded voice sound can be simply and cheaply scrambled into intelligeable form, and then unscrambled. It is not impossible, however, that the input data could already be encoded/encrypted, in which case "plain-form" has merely the aforementioned distinguishing meaning.
  • the data is transferred sequentially through four analogue shift registers - it is input to one, transferred (“clocked”) through that one and out, and then it is input to a second, transferred through this other and out.
  • the encrypted date is then transmitted to a second location where it is input to a third shift register, clocked through it, then input to a fourth register, transferred through it and out.
  • the data is input to the first register in plain form, is output from the second register - and input to the third register - in encrypted form (as will be explained below, the encrypted form is merely a frequency-shifted version of the plain form), and is output by the fourth register in plain form.
  • the first and second registers are at the transmitting location
  • the third and fourth registers are at the receiving location
  • the data transferred between the two locations is encrypted.
  • An analogue shift register is an electronic device having a sequence of elements, or cells, in each of which may be stored an electrical charge the value of which may be any within some continuous range. This sequence of cells is a register, and because the contents can represent - be analogous to - any value (within some range) it is an analogue register.
  • each cell may be shifted - clocked - to the sequentially next cell under the control of transfer clock pulses suitably delivered to the device (so the register is a shift register), and by doing this an electrical signal/value presented to the first cell may be transferred into that cell, then shifted to the next cell, . « and finally transferred to, and out of, the last cell.
  • the process is very like pouring water from one bucket to the next in a chain of buckets (indeed, one form of such a device is actually known as a "bucket brigade device"); water - the signal - is poured into the first bucket, and thence to the next, and the next....and so on till it reaches, and is poured out of, the last bucket.
  • any signal fed into the cell sequence is delayed - over a signal bypassing the sequence - by the time it takes to transfer it through and out of the cells.
  • this transfer time is a function of the clock frequency. The lower the frequency - the lower the rate of clock pulses driving the transfer from one cell to the next - the longer it all takes.
  • an analogue signal is presented to - and input to - an analogue shift register, and if, as it is input, so it is transferred on and through the register at a rate at or greater than the minimum required by the Nyquist rule (sampling rates must be at least twice the frequency of the input signal's highest frequency component), then the output signal will consist of a series of pulses, or bits, that faithfully define - and in effect are - the original input signal together with a clock frequency component added thereto. By filtering off this clock component there may be reconstituted the original input signal, albeit in delayed form.
  • the data that is fed into the third register is so fed in at the same rate as it was fed out of the second register
  • the data that is fed out of the third register is so fed out at the same rate it was fed in to the second register
  • the data that is fed into the fourth register is so fed in at the same rate as it was fed out of the first register
  • the data that is fed out of the fourth register is so fed out at the same rate as it was fed into the first register.
  • the data passing between the two sets of registers is frequency shifted, and thus encrypted.
  • the shift alternates between being an up shift and being a down shift and the amount of up or down shifting is not constant. It is perhaps this constant variation in direction and amount of frequency shifting that renders the method of the invention particularly effective, especially with voice data, where the main energy lies at the lower end of the frequency range (300 to 1000Hz, say) but the intelligence - the "formants" - lies mostly at the upper end of the range (2000 to 3000 Hz, say).
  • this merely requires that, sent either alongside or buried within the coded data, there is a master timing signal that enables the fourth register's timing system to synchronise with the first register's system and the third register's timing system to synchronise with the second register's system.
  • a master timing signal that enables the fourth register's timing system to synchronise with the first register's system and the third register's timing system to synchronise with the second register's system.
  • each pair of two registers will have its own, nominally independent, clock - the heart of the timing system - that is crystal-controlled to keep very accurate time.
  • This clock signal can then be used to derive the needed different timing signals for each register of the pair.
  • clocks such as these tend to "drift" off frequency as time goes on, so there will be some way of re-triggering the clock cycle from an external source.
  • the first output is a dc pulse which is produced on lock up, and is fed to the decryption clock generator as a coarse reset.
  • the clock reference generator is crystal controlled, and its output is fed via a gate to the decryption clock generator.
  • a tone generator derived from an output of the clock generator is set to the same as that at the transmitter. This is compared with the second output of the phase locked tone decoded by means of a phase sensitive rectifier. If the two signals are not in phase, the rectifier output will consist of a series of pulses whose width will be a function of relative phase.
  • the output is shaped and connected to the gate at the input of the clock generator. As a result a pulse or pulses will be "blanked" at the clock generator input.
  • the tone at the receiver will now slip until it is in phase with the incoming signal, when the phase sensitive detection output disappears. Providing the signals remain in phase, no further blanking occurs.
  • a dc signal can be derived from the PSR to adjust the fundamental crystal frequency for ultra fine adjustment.
  • the transmitted tone frequency can be varied to indicate "Time of day” at the transmitter.
  • This method provides a means of synchronisation which does not indicate encryption information.
  • the invention employs four analogue shift registers in sequence. This can result in acceptable low level security, but for higher levels the resulting encryption is inadequate.
  • Another way of improving the security of the encrypted data would be to change the clocking rate, that is, change other than the alternation between two rates in the known system.
  • change the clocking rate will alter the time taken by data to pass through the system.
  • data will be either overwritten - resulting in loss of data, or blank areas will appear in the signal.
  • This problem can be overcome by arranging the clock frequencies supplied to the encrypting register so that the time taken to clock in some set amount of data is a constant. We shall call this time period the frame time.
  • the simplest such amount to choose is one encrypting register full of data.
  • the signal will effectively be processed as a string of sections of signal, each of these sections of signal being of the frame length T.
  • Each section is fed into the encrypting register at a series of different clock rates and then fed out of the register at a different series of clock rates.
  • Each of the series of clock rates being chosen so that in frame time T the total number of clock pulses supplied to the register is equal to the number of cells in the register.
  • Each of these sections of signal is encrypted by a number of different frequency shifts because it is read into the register at a series of clock rates and then read out of the register at a different series of clock rates (the number of different clock rates, the order of the clock rates and the clock rates may all be altered). Because the time taken for data representing each section of signal to pass through the register is a constant, problems of overwriting and blank areas in the signal are avoided.
  • a frame time of the signal 58.368 msec could be chosen and one frame length of signal could be fed into the register at four different clock rates as follows:
  • the signal section is thus encrypted because each 1024 bit section of it is read in and out of the register at different rates, but the time taken to read the signal section in is the same as the time taken to read the signal out. As the section is read out of the register the next signal section is read in and it is later read out at a third sequence of four clock rates.
  • the signal is decrypted by reading it into a decrypting register at the same sequence of clock rates it was read out of the encrypting register and then reading it out of a decrypting register at the same sequence of clock rates it was read into the encrypting register. Because this requires one signal section to be read out of decryption at one rate and the next section to be read into decryption simultaneously at another rate, it will, in fact, be necessary to use two registers to decrypt the signal, the two decrypting registers decrypting alternate signal sections.
  • Such a system is simplest, and provides the highest degree of encryption, when the encrypting and decrypting registers are of equal size. It would however, be possible to use encrypting and decrypting registers of different sizes. If a system with different sized encrypting and decrypting registers were used, the number of clock pulses supplied in the fixed frame time must not be larger than the capacity of the smallest register.
  • the length of the encrypting and decrypting registers could be altered. This could not be done while a signal was being transmitted, because it would cause loss of data or the introduction of blank sections into the output signal. However, this could be done in the course of a speech message by altering the register's lengths during pauses.
  • the signal to be encrypted could, of course, be pre-encoded or encrypted for additional security.
  • the analogue data - a speech signal can be separated into two bands, lower and upper, and fed to two separate sets of registers operating independently.
  • high and low pass filters would separate the two bands before injecting them into two corresponding separate sets of registers.
  • Yet another embodiment enables the speech time sequence to be transformed. If two sets of encrypting registers are connected in series and a signal applied for a time which would fill all the registers, the two sets can then be transposed, and transmitted in reverse order. On reception in two sets of decrypting registers, the contents are again transposed before being clocked out.
  • This method can be combined with any other; the number of registers employed determines the amount of transpositon. Obviously, more registers increases the overall delay. However, transposition would also reduce the relative clock change necessary, and the individual frames could be shorter.
  • the sequence of Figure 1 represents the transferral of a simple sine wave signal F through a 16-cell analogue shift register (101). At time TO all the cells 1-16 are empty; the signal F is presented to the register's input end (the left as viewed) on the input line (102). If the register receives a clock pulse (at time T 1 , not shown in the Figure) then a charge representing the value of the signal at that time is placed in the first cell. A second pulse (at time T 2 , also not shown) causes the contents of cell 1 to be transferred to cell 2 and cell 1 itself is then filled with a fresh charge representing the new value of the signal presented thereto at that time.
  • the view at time T 4 shows the situation after three such pulses (in a complete series of i pulses). By time T 4 , the original cell contents have been successively transferred, via cells 2 and 3, to cell 4, and cells 3, 2 and 1 hold, in that order, the charges representing the value of the signal presented to cell 1 at times T 3 , T 2 and T l respectively.
  • the general situation is meaning that the output frequency is related to the input frequency by a factor that is the ratio of the output to input clocking rates.
  • Figure 3 shows a schematic diagram for a simple form of circuit according to the invention.
  • this encrypted signal is received and clocked into line 3 at clock rate CR 4 .
  • the signal is clocked out of line 3 at clock rate CR 3 and into line 4 at clock rate CR 2 .
  • the encrypted speech is quite unintelligeable, appearing almost similar to band inversion, but with a "garble” effect.
  • a tone is transmitted either continously (and subsequently filtered out at the receiver) or at the start of transmission.
  • the tone is derived by shaping an output from the encrypt clock generating system and modifying to a (possibly) triangular form, or that suitable for the characteristics of the system.
  • the signal is not encrypted. For systems with large group delays the frequency should be fairly low, typically 200Hz.
  • the encrypted output from the receiver is fed to a tone decoder/phase-locked loop. This generates two outputs.
  • the first output is a dc pulse which is produced on lock-up. This is fed to the decryption clock generator as a coarse reset.
  • the clock reference generator is crystal controlled, its output fed via a gate to the decryption clock generator.
  • a tone generator derived from an output of the clock generator is set to the same frequency as that at the transmitter. This is compared with the second output of the phase-locked tone decoder by means of a phase sensitive rectifier. If the two signals are not in phase, the rectifier output will consist of a series of pulses whose width will be a function of relative phase. The output is shaped and connected to the gate at the input of the clock generator. As a result a pulse or pulses will be "blanked" at the clock generator input. The tone at the receiver will now slip until it is phase with the incoming signal, when the phase sensitive detection output disappears. Providing the signals remain in phase no further blanking occurs.
  • a dc signal can be derived from the PSR to adjust the fundamental crystal frequency for ultra fine adjustment.
  • an analogue speech encoder/decoder includes an encrypting system 8 and a decrypting system 9.
  • This encrypted signal is then supplied to a transmitter 17 which transmits it.
  • the transmitted signal is received by a receiver 18 which supplies it to the input of the decryption system 19.
  • the decryption system 19 includes two shift registers 19A and 19B. Shift registers 19A and 19B are clocked at clock rates derived from a lMHz reference frequency generated by a frequency source 20 by variable dividers 21A and 21B respectively.
  • the variable dividers 21A and 21B are controlled by a code selector 22 which is in turn controlled by a pseudo-random code generator 23.
  • Two switches 24 and 30 are arranged so that at any time one of register 19A and 19B is connected to an input of decrypter 9 and the other is connected to an output of decrypter 9.
  • pseudo-random sequence generators 15 and 23 producing the same pseudo-random sequence and being synchronised, the necessary synchronisation can be easily arranged and so need not be described in detail, so that the numbers supplied to the code selector 14 and to the code selector 22 along line 25A are the same.
  • the code selectors 14 and 22 have the same clock pulse sequences stored at equivalent addresses and use the same algorythm to derive addresses from the numbers provided.
  • the algorythms can be changed depending on the time, who the recipient of the message is, or in any other predetermined manner, such a procedure is simple and ned not be discussed here.
  • counter 26 After 4096 clock pulses, counter 26 signals switches 24 and 30 along line 31. In response to this signal, switches 24 and 30 change position so that shift register 19A is connected to the output of the decrypting system 9, and shift register 19B is connected to the input.
  • Counter 26 also signals the pseudo-random code generator 23 along line 29, in response to this signal the pseudo-random code generator 23 steps to its next setting and provides this number to the code selector 22 along a line 25B, it also provides the number two steps before this number in the pseudo-random code sequence to the code selector 22 along the line 25A.
  • the code selector 22 uses these two numbers to find two memory addresses and obtains two series of clock rates.
  • the series of clock rates found using the present number from the pseudo-random code generator 23, which will be the same as the series being used to clock encrypting register 11, are used by code selector 22 to clock the signal received by the receiver 18 into the shift register 19B.
  • the series of clock rates found using the two steps back number from the pseudo-random generator code generator 23, which will be the same as the series which was used to read the data now in shift register 19A out of shift register 11, are used by code selector 22 to clock out the data in register 19A to an output 32 of the decrypting unit 9.
  • the counter 26 separately counts the number of clock pulses going to registers 19A and 19B and signals the code selector along lines 27A and 27B respectively every 1024 pulses on the appropriate line. Every 4096 pulses the counter signals the code selector 22 on line 28. Note that since all code series used produce 4096 pulses in 58.368 msec. the counts of pulses to both registers will reach 4096 simultaneously.
  • the code selector 22 receives a signal on line 27A it sets variable divider 21A to produce the next clock frequency in the series used to clock the register 19A, and similarly when it receives a signal on line 27B, it sets variable divider 21B to produce the next clock frequency in the series used to clock the register 19B.
  • register 19A is empty and register 19B is full, the switches 24 and 30 are changed to connect register 19A to read in data and register 19B to read out data and the pseudo random sequence generator 23 is stepped.
  • Encrypyted data from encrypting register 11 is then fed into register 19A while the data in register 19B is read out in decrypted form. This cycle of use of the two registers 19A and 19B then continues with the lines alternately reading in and reading out data and providing a continuous decrypted signal at output 32.
  • the system could be made still more secure by arranging the encrypting and decrypting shift registers to be of variable length. All the shift registers would have to change their length simultaneously of course. Such a change could not be made while data was being passed through the system without seriously degrading the output signal, but it could be carried out during silent parts of the signal, silences being common in speech.
  • a system with this facility would need a sensor in the encrypter to detect silences or blanks in the incoming signal and some means to inform the decrypter what the new register length was. It would also be necessary to alter the clock frequency series produced by selectors 14 and 22 to fit each new register length.
  • signal to be transmitted could be pre-encrypted and post decrypted by another similar encryption/decryption system, or indeed by any other type of encryption/decryption system.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Storage Device Security (AREA)
  • Two-Way Televisions, Distribution Of Moving Picture Or The Like (AREA)
EP86307139A 1985-09-17 1986-09-16 Chiffrage de données Withdrawn EP0216595A3 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB8522979 1985-09-17
GB8522979 1985-09-17

Publications (2)

Publication Number Publication Date
EP0216595A2 true EP0216595A2 (fr) 1987-04-01
EP0216595A3 EP0216595A3 (fr) 1988-10-26

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EP (1) EP0216595A3 (fr)
JP (1) JPS62111542A (fr)
GB (1) GB2180728A (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2711665A1 (fr) * 1993-10-25 1995-05-05 Atochem Elf Sa Liant d'adhésion du PVDF, son application comme matériau barrière et matériaux obtenus à partir de celui-ci.
CN101442741B (zh) * 1997-04-24 2011-04-13 株式会社Ntt都科摩 移动通信方法和移动通信系统

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4217469A (en) * 1977-03-15 1980-08-12 Emilio Martelli Coding and decoding apparatus for the protection of communication secrecy
EP0018869A1 (fr) * 1979-04-20 1980-11-12 Etablissement Public Télédiffusion de France Installation de cryptage et de décryptage d'un signal analogique par compressions et expansions temporelles
US4392021A (en) * 1980-07-28 1983-07-05 Technical Communications Corporation Secure facsimile transmission system using time-delay modulation
JPS59112740A (ja) * 1983-11-28 1984-06-29 Enii:Kk 秘話装置
EP0117276A2 (fr) * 1982-09-20 1984-09-05 Sanyo Electric Co., Ltd. Dispositif de communication secrète

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4217469A (en) * 1977-03-15 1980-08-12 Emilio Martelli Coding and decoding apparatus for the protection of communication secrecy
EP0018869A1 (fr) * 1979-04-20 1980-11-12 Etablissement Public Télédiffusion de France Installation de cryptage et de décryptage d'un signal analogique par compressions et expansions temporelles
US4392021A (en) * 1980-07-28 1983-07-05 Technical Communications Corporation Secure facsimile transmission system using time-delay modulation
EP0117276A2 (fr) * 1982-09-20 1984-09-05 Sanyo Electric Co., Ltd. Dispositif de communication secrète
JPS59112740A (ja) * 1983-11-28 1984-06-29 Enii:Kk 秘話装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN, vol. 8, no. 231 (E-274)[1668], 24th October 1984; & JP-A-59 112 740 (ENII K.K.) 29-06-1984 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2711665A1 (fr) * 1993-10-25 1995-05-05 Atochem Elf Sa Liant d'adhésion du PVDF, son application comme matériau barrière et matériaux obtenus à partir de celui-ci.
CN101442741B (zh) * 1997-04-24 2011-04-13 株式会社Ntt都科摩 移动通信方法和移动通信系统

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GB2180728A (en) 1987-04-01
JPS62111542A (ja) 1987-05-22
GB8622238D0 (en) 1986-10-22
EP0216595A3 (fr) 1988-10-26

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