EP0215028A1 - Controleur de microprogrammes - Google Patents

Controleur de microprogrammes

Info

Publication number
EP0215028A1
EP0215028A1 EP86901305A EP86901305A EP0215028A1 EP 0215028 A1 EP0215028 A1 EP 0215028A1 EP 86901305 A EP86901305 A EP 86901305A EP 86901305 A EP86901305 A EP 86901305A EP 0215028 A1 EP0215028 A1 EP 0215028A1
Authority
EP
European Patent Office
Prior art keywords
register
instruction
memory
multiplexer
arithmetic logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP86901305A
Other languages
German (de)
English (en)
Other versions
EP0215028A4 (fr
Inventor
David R. Brooks
Daniel S. O'sullivan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MAGGELAN Corp (AUSTRALIA) Pty Ltd
Original Assignee
MAGGELAN Corp (AUSTRALIA) Pty Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by MAGGELAN Corp (AUSTRALIA) Pty Ltd filed Critical MAGGELAN Corp (AUSTRALIA) Pty Ltd
Publication of EP0215028A1 publication Critical patent/EP0215028A1/fr
Publication of EP0215028A4 publication Critical patent/EP0215028A4/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/26—Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements
    • G06F9/262—Arrangements for next microinstruction selection
    • G06F9/264—Microinstruction selection based on results of processing
    • G06F9/267—Microinstruction selection based on results of processing by instruction selection on output of storage

Definitions

  • the present invention relates to microprogram con ⁇ trollers including a memory to store instructions at speci- fied addresses, a register to hold a current instruction and an arithmetic logic unit (ALU) : the ALU executing the current instruction and thereby manipulating external data as well as altering the choice of the following instruction and accessing the corresponding address in the memory.
  • ALU arithmetic logic unit
  • This device comprises a memory containing coded instructions, and a register, connected in loop arrangement. The simplest arrangement is shown in Fig. 1.
  • the register R holds the current micro ⁇ instruction, which is presented to an Arithmetic/Logic Unit (ALU), that executes the instruction, manipulating external data as required.
  • An additional field in the micro- instruction represents the memory address of the next instruction to be executed.
  • this "next address” can be modified by the ALU outputs, providing a "conditional jump” feature.
  • Further prior art systems known to applicant are disclosed in Australian patent specification nos. 535105 and 538215 in the name of Control Data Corporation. The disclosures therein require the use of separate address registers and support circuitry, buses and the like for each memory bank.
  • a microprogram controller including a memory to store instructions at specified addresses, a register to hold a current instruc- tion including the address in the memory of the following instruction an arithmetic logic unit to execute the current instruction and thereby manipulating external data as well as altering the choice of following instruction; the improvement comprising dividing the memory into two banks and presenting the output of each memory, each said output being a possible following instruction,, to a first multiplexer which is connected to the register, and providing a second multiplexer to simultaneously with the execution of the current instruction receive as input any number of various conditions (including "1" and "0") one at a time, developed by the arithmetic logic unit and to develop a binary output to determine which of the following instructions at the
  • Figure 3 shows a block diagram of a micropro- grammer made in accordance with the invention.
  • FIG. 4 is a block diagram of a modified micro ⁇ program controller made in accordance with the invention.
  • the circular dashed arrow in Fig. 1 indicates the time sequence of the various operations. The total delay around this path limits the maximum speed of the machine. Since the delays in memory and the ALU represent by far the largest component of this delay, and in practical systems are often approximately equal, the scheme of Fig. 2 may be used to double the speed of the machine, by allowing these functions to proceed in parallel (see the two arrows in Fig. 2).
  • the current instruction and the address of its successor are held in the two registers Rl and R2. Simultaneously, the memory presents the following instruction at the input of Rl, while the address of its successor (i.e.
  • Fig. 3 The scheme according to the invention is shown in greater detail in Fig. 3.
  • the memory is here split into two banks (A and B), each of half of the original size (the total size will be dictated by program requirements), and register R2 of Fig. 2 is replaced by the multiplexer Ml, which can present the output of either memory bank to the register R.
  • the two paralleled paths are as before, denoted by circular dashed arrows.
  • the current instruction is output from R, and the
  • ALU commences to calculate the desired results.
  • Various con ⁇ ditions of possible interest (zero, negative, etc.) are offered as inputs to the secondary multiplexer M2, together with the constant values 0 and 1.
  • M2 selects one of these inputs, as specified by the instruction, and develops the binary output "SWITCH".
  • the address field of the current instruction has accessed both memory banks simultaneously, yielding two possible successor instructions. Note that the slow processes, i.e ALU function and memory access, proceed simultaneously.
  • the signal "SWITCH”, acting on multiplexer Ml determines which of the two possible successor instructions is actually loaded into R, and next executed.
  • the current instruction has modified its immediate successor, and simple programming methods may be used (as in Fig. 1).
  • a one-instruction "loop" is developed by coding the instruction's successor address to point to itself. As long as the looping condition obtains, the instruction (in one bank of memory) is repeatedly executed, when the condition fails, the alternative instruction is executed instead and the program proceeds.
  • Normal instructions i.e. those with no condi ⁇ tional effects, merely direct M2 to select one of the literal inputs 0 and 1, so explicitly directing the flow of control into Bank A or B as required.
  • Multi-way Branches Modification A limited ability to perform multi-way branches, based on values computed by the ALU, is frequently desirable. Such a feature can readily be added to the architecture of Fig. 3, yielding that of Fig. 4, by parti ⁇ tioning the multiplexer Ml, into two sections, handling the current instruction and next address fields respectively.
  • the current instruction field .operates as described above, ' as does most of the next address field.
  • a portion of -the address field is provided with an additional input channel ("BRANCH" in Fig. 4) supplied from a register previously loaded by the ALU.
  • BRANCH additional input channel
  • Literal Outputs Modification Another infrequently used, but nonetheless valuable feature is the ability for the microprogram to supply literal values to the ALU at certain times. This feature may be obtained by addition of the LITERAL register (Fig. 4). On every machine cycle, the current value in one memory bank (in this example memory Bank B) may be loaded into this register, which can be read by the ALU when required. This implies that instructions to load meaningful data into the literal register must themselves reside in Bank A, since the corresponding Bank B location contains literal data, not an instruction. Since no penalty attaches to branching from one bank to another, this is not a problem. Once loaded, the value in the literal register is simply another ALU input, to be accessed when required.

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)
  • Debugging And Monitoring (AREA)

Abstract

Un contrôleur de microprogrammes possède une mémoire pour stocker des instructions à des adresses spécifiées, un registre (R) de maintien d'une instruction courante comprenant l'adresse dans la mémoire de l'instruction suivante, une unité logique arithmétique (ALU) pour exécuter l'instruction courante et ainsi manipuler les données extérieures et modifier le choix de l'instruction suivante. La mémoire est divisée en deux bancs (A, B) et la sortie (chaque sortie étant une instruction suivante possible) de chaque banc de mémoire est présentée à un premier multiplexeur (M1) qui est connecté au registre (R), et un second multiplexeur (M2) pour recevoir comme entrée, simultanément à l'exécution de l'instruction courante, tout nombre de conditions diverses (y compris ''1'' et ''0'') un à la fois, développé par l'unité logique arithmétique (ALU) et pour développer une sortie binaire de manière à déterminer laquelle des instructions suivantes au niveau du premier multiplexeur (M1) est chargée dans le registre (R) et doit être la suivante à exécuter. La majorité des fonctions de saut conditionnelles sont, en fait des décisions à deux possibilités, c'est-à-dire SI (quelque chose) ALORS FAIRE (ceci) AUTREMENT FAIRE (cela). La nouvelle architecture est conçue pour optimiser ce type de décision. Un registre LITTERAL est ajouté pour permettre aux microprogrammes d'alimenter l'unité logique arithmétique (ALU) en valeurs littérales à certains moments.
EP19860901305 1985-02-20 1986-02-19 Controleur de microprogrammes. Withdrawn EP0215028A4 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
AUPG938385 1985-02-20
AU9383/85 1985-02-20

Publications (2)

Publication Number Publication Date
EP0215028A1 true EP0215028A1 (fr) 1987-03-25
EP0215028A4 EP0215028A4 (fr) 1987-07-23

Family

ID=3770948

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19860901305 Withdrawn EP0215028A4 (fr) 1985-02-20 1986-02-19 Controleur de microprogrammes.

Country Status (4)

Country Link
EP (1) EP0215028A4 (fr)
JP (1) JPS62501940A (fr)
AU (1) AU582424B2 (fr)
WO (1) WO1986005015A1 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5119484A (en) * 1987-02-24 1992-06-02 Digital Equipment Corporation Selections between alternate control word and current instruction generated control word for alu in respond to alu output and current instruction
EP0302926B1 (fr) * 1987-02-24 1993-07-14 Digital Equipment Corporation Circuit de generation de signaux de commande pour unite arithmetique et logique pour un processeur numerique
JPH04328634A (ja) * 1991-04-26 1992-11-17 Nec Corp マイクロプログラム制御装置
EP0522513A2 (fr) * 1991-07-09 1993-01-13 Hughes Aircraft Company Unité de commande à grande vitesse pour programme à microcode parallèle
US6629262B1 (en) * 1999-09-30 2003-09-30 Toshiba Tec Kabushiki Kaisha Multiplexed storage controlling device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3570006A (en) * 1968-01-02 1971-03-09 Honeywell Inc Multiple branch technique
US3909797A (en) * 1973-12-13 1975-09-30 Honeywell Inf Systems Data processing system utilizing control store unit and push down stack for nested subroutines
EP0107952A2 (fr) * 1982-10-18 1984-05-09 Nec Corporation Dispositif de traitement d'information et son système de commande d'instruction
EP0142562A1 (fr) * 1983-01-14 1985-05-29 Hitachi, Ltd. Systeme de pipeline pour unite de commande de microprogramme

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5410219B2 (fr) * 1973-12-07 1979-05-02
US4336602A (en) * 1979-09-24 1982-06-22 Control Data Corporation Network for generating modified microcode addresses
US4459666A (en) * 1979-09-24 1984-07-10 Control Data Corporation Plural microcode control memory
DE3009121C2 (de) * 1980-03-10 1982-02-18 Siemens AG, 1000 Berlin und 8000 München Mikroprogramm-Steuereinrichtung

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3570006A (en) * 1968-01-02 1971-03-09 Honeywell Inc Multiple branch technique
US3909797A (en) * 1973-12-13 1975-09-30 Honeywell Inf Systems Data processing system utilizing control store unit and push down stack for nested subroutines
EP0107952A2 (fr) * 1982-10-18 1984-05-09 Nec Corporation Dispositif de traitement d'information et son système de commande d'instruction
EP0142562A1 (fr) * 1983-01-14 1985-05-29 Hitachi, Ltd. Systeme de pipeline pour unite de commande de microprogramme

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
MICROPROCESSING AND MICROPROGRAMMING, vol. 14, no. 3/4, October-November 1984, pages 211-214, Amsterdam, NL; E. MANDADO et al.: "New developments in fast microprogrammable control units" *
See also references of WO8605015A1 *

Also Published As

Publication number Publication date
AU5459986A (en) 1986-09-10
JPS62501940A (ja) 1987-07-30
WO1986005015A1 (fr) 1986-08-28
AU582424B2 (en) 1989-03-23
EP0215028A4 (fr) 1987-07-23

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Inventor name: BROOKS, DAVID, R.