EP0209530A1

EP0209530A1 - Multiprocessor memory access system

Info

Publication number: EP0209530A1
Application number: EP19860900059
Authority: EP
Inventors: Klaus Gotschlich; Gerhard Lotterbach; Egbert Perenthaler; Jan Faas Van Woudenberg; Udo Zucker
Original assignee: Robert Bosch GmbH
Current assignee: Robert Bosch GmbH
Priority date: 1985-01-28
Filing date: 1985-12-14
Publication date: 1987-01-28
Also published as: AU574884B2; JPS62501656A; WO1986004434A1; BR8507171A; AU5236086A; DE3502721A1

Abstract

Système multiprocesseur avec un multiplexeur (3) commun et une mémoire (4) commune, travaillant de manière asynchrone. Pour cela, le multiplexeur débloque selon la demande du processeur (1, 2) un transcepteur correspondant (7, 8) pour la donnée et une mémoire adresse (5, 6) pour l'adresse. Un codeur de priorité (9) garantit qu'un seul processeur à la fois a accès à la mémoire commune.Multiprocessor system with a common multiplexer (3) and a common memory (4), working asynchronously. For this, the multiplexer unlocks according to the request of the processor (1, 2) a corresponding transceiver (7, 8) for the data and an address memory (5, 6) for the address. A priority encoder (9) ensures that only one processor at a time has access to the common memory.

Description

Multiprocessor memory access system

State of the art

The invention is based on a multiprocessor system according to the preamble of the main claim.

A multiprocessor system is already known from US Pat. No. 4,164,787, in which two processors are connected to a multiplexer in such a way that the multiplexer in each case switches the entire address and data bus of a processor to a common memory. The multiplexer is regularly switched synchronously with a clock generator, so that a time-division multiplex of constant switching frequency results for the access.

The disadvantage of this multiprocessor system is the fixed synchronism, which does not allow a processor to continuously access the memory for longer times than half a clock period of the clock. Complex procedures in the programs of the processors are therefore necessary, for example via interrupt controls, in order to ensure that a longer program is worked through correctly. Furthermore, hardware circuits are necessary to inform the respective processor that the next the multiplexer will switch. The fixed switching frequency effectively reduces the service life of the memory's idress and data bus, since after switching, no access is possible on the bus lines during the settling times of the signals.

Advantages of the invention

The multiprocessor system according to the invention with the characterizing features of the main claim has the advantage that an undisturbed access of a processor to the common memory is possible, which is only interrupted by an access request by a processor of higher priority. In this way, lengthy procedures of a processor can be carried out continuously. The asynchronous coupling of the processors via the shared memory enables fast data exchange between the processors, since the multiplexer is not supplied with a fixed clock frequency. It can switch to memory immediately after a data transfer is completed so that the next processor can read the stored date. This coupling, which is adapted to the requirements of the processors, increases the overall throughput and the performance of the multiprocessor system according to the invention considerably.

Particularly advantageous embodiments of the multiprocessor system according to the invention are specified by the subclaims. The priority assignment to the individual processors is carried out in a particularly simple manner if at least the memory access signals (read, write, chip select) or the multiplexer selection signals of the processors for the common memory are fed to the priority encoder. These signals provide a sufficient and particularly simple basis for the selection logic of the priority encoder. A typing Locking for the low-priority processors offers special security when two processors want to access the memory and the multiplexer at the same time and the signals - especially on the address lines of the shared memory - have not yet settled. This prevents undefined write operations in the memory. For the circuitry complexity of the multiprocessor system according to the invention, it is particularly advantageous if the connection between the processors and the address bus of the common memory is made via an address memory that can be released by the multiplexer and, moreover, if the connection between the processors and the data bus of the shared memory are guided via transceivers that can be released by the multiplexer. This considerably reduces the number of lines required and reduces the system's susceptibility to faults. The circuitry complexity for the multiplexer is also reduced, since only the enable lines for address memory and transceiver have to be switched to assign a processor.

drawing

An embodiment of the invention is shown in the drawing and explained in more detail in the following description. The sole figure shows a multiprocessor system with two processors, which is used as a control device in a motor vehicle for controlling the injection.

Description of the embodiment

The figure shows two microprocessors 1, 2, of which the first microprocessor 1 represents the master processor, the second microprocessor 2 the slave processes sor. The processors 1, 2 are each connected to a multiplexer 3 and a common memory 4. The processor 1 is connected via an address memory 5 and the processor 2 via an address memory 6 to the address bus 4 1 of the memory 4. The processor 1 is connected to the data bus 42 of the memory 4 via a transceiver 7 and the processor 2 via a transceiver 8. A priority encoder 9 connects the processor 1 and the processor 2 to the multiplexer 3. A write lock 10 is inserted between the processor 2 and the multiplexer 3.

The master processor 1 is connected with a port P1 to a bus 51, which leads to the address memory 4 and the transceiver 7. The address memory 5 is activated via a line 53 by a signal at an output ALE1 (address latch enable). For this purpose, the slave processor 2 is connected completely symmetrically with a port P2 to a bus 61, which leads to the address memory 6 and the transceiver 8. The address memory 6 is activated via a line 63 by a signal at an output ALE2. The outputs of the address memories 5, 6 are connected via an address bus 41 to the address input A of the common memory 4. The associated data are transmitted via a data bus 42, which is connected between the transceivers 7, 8 and the common memory 4. The write signal WR1 and the read signal RD1 of the master processor 1 are routed to the multiplexer 3. The read signal RD2 of the slave processor

2 is also routed to the multiplexer 3, while the write signal WR2 is routed to the write lock 10, which in turn is a write signal WR2 'to the multiplexer

3 leads. The multiplexer selection signals MS1 of the master processor 1 and MS2 of the slave processor 2 are routed to the priority encoder 9, which activates the multiplexer 3 via a line 91 and the write lock 10 and an input BUSY of the slave processor 2 via a line 92 speaks. The multiplexer 3 controls the transceiver 7 or 8 via a line 71 or 81 and the address memory 5 or 6 via a line 52 or 62. Furthermore, the memory 4 is controlled by the multiplexer 3 via a line 43.

This two-processor system is used in a control unit for a motor vehicle, in which the master processor 1 receives operating data 11 from the internal combustion engine. The master processor 1 controls the ignition of the internal combustion engine from the rotational speed n, the load L and the temperature T and calculates default data for the injection. The slave processor 2 is used to control an injection device 12, wherein it separately and sequentially measures the required injection quantities at the correct injection times for each cylinder of the internal combustion engine. For this purpose, he receives operating data 13 from the internal combustion engine, e.g. the delivery pressure of the petrol pump.

The coupling between master processor 1 and slave processor 2 via the common memory 4 serves to transmit the control specifications and reciprocal transmission of operating data. The coupling is designed so that the master processor 1 can access the common memory 4 as if the slave processor 2 were not present at all. The slave processor 2, on the other hand, is interrupted when the shared memory 4 is accessed, or access is not even made possible when the master processor 1 accesses.

When a data is transferred from the master processor 1 to the common memory 4, the multiplexer 3 is first activated by a signal MS1 via the priority encoder 9 and the address of the memory location is placed on the port P1. After address memory 5 is released via line 52 by setting the signal ALE1, the address is loaded into the address memory 5 and held there by withdrawing the signal ALE1. The date is then applied to port P1 and the transceiver 7 is activated by multiplexer 3 via line 71. The data is sent from port P1 to transceiver 7, the direction of transmission of which is determined by signal RD1. The memory 4 is now released for writing by a signal on line 43. After the addressing process in the memory 4 has ended, the multiplexer 3 releases the transceiver 7, so that the data present at the port P1 can be written into the associated address in the memory 4. The reading process by the master processor 1 takes place in a manner equivalent to the writing process.

When the master processor 1 is activated by the signal MS1 multiplexer 3 to access the memory 4, the priority encoder 9 is addressed first. This forms a signal for the write lock 10, which immediately interrupts write access by the slave processor 2 to the multiplexer 3 or blocks a future access request. For this purpose, this signal is routed to a BUSY input of slave processor 2. This input is queried by the slave processor 2 after each access to the shared memory 4. If there is a signal from the priority encoder 9, the access is repeated as soon as the write lock 10 is released again.

If the master processor 1 is not active, the slave processor 2 can freely access the memory 4, the functional sequence in the address memory 6 and in the transceiver 8 being completely identical to the functional sequence in the address memory 5 and in the transceiver 7 when the master processor 1 accesses it. However, if the processor 4 is accessed while the memory 4 is being accessed, active, the priority encoder 9 is immediately activated by the signal MS1 and the write lock 10 is switched on. At the same time, the multiplexer 3 withdraws the releases for the address memory 6 and the transceiver 8, so that their inputs and outputs to the buses 4 1, 42 of the common memory 4 become high-resistance. The signal at the BUSY input tells the slave processor 2 in time that no information is lost. During the access by the master processor 1, the slave processor 2 repeats its interrupted access until the BUSY signal is withdrawn.

The invention is of course not limited to the exemplary embodiment chosen here. In the same way, more than two processors can be coupled via a common memory. Then each processor is assigned an address memory and a transceiver, which are controlled by a common multiplexer. A priority encoder then blocks the lower priority processors from accessing the shared memory when a higher priority processor accesses them. Furthermore, it depends on the type of modules used, which control signals are present, whether there are separate write and read signals from the processors, whether there is a common clock of the processors, so that work synchronously but perform asynchronous access to the common memory. It is also possible to connect processors of different types in the manner according to the invention via a common memory. Multiplexers and priority encoders can be constructed in discrete logic, which is assigned to each processor in terms of hardware and can also be implemented in software there. By exchanging control bytes, the processors can be mutually checked with one another. The multiprocessor system according to the invention can be simplified even further by using modules suitable for this purpose. In particular, the address memories can be omitted if the shared memory already has an address memory.

Claims

Expectations

1. Multiprocessor system, in particular control device for a motor vehicle, with at least two processors (1, 2), with a common memory (k) and with a common multiplexer (3) to enable a processor to access the common memory (4), characterized that access of a processor (2) to the shared memory (4) is interrupted or prevented when a. Processor (1) with higher priority accesses the shared memory (4).

2. Multi-processor system according to claim 1, characterized in that the priority assignment to the processors (1, 2) is carried out by a common priority encoder (9) to which at least the multiplexer selection signals (MS1, MS2) are supplied.

3. Multiprocessor system according to claim 1, characterized in that the priority encoder (9) at least the memory access signals of the processors (1, 2) are supplied.

4th Multiprocessor system according to one of the preceding claims, characterized in that a write lock (10) interrupts or prevents access by a processor (2) to the common multiplexer (3) when a processor (1) with higher priority accesses the common multiplexer (3) .

5. Multiprocessor system according to one of the preceding claims, characterized in that a processor (1, 2) writes the addresses in an address memory (5, 6) when accessing the common memory (4) and that the multiplexer (3) transfers the addresses from the address memory (5, 6) to the shared memory (4) releases (52, 62).

6. Multiprocessor system according to one of the preceding claims, characterized in that a processor (1, 2) at one. Access to the common memory (4) sends or receives the data via a transceiver (7, 8) and that the multiplexer (3) releases the transceiver (7, 8) (71, 81).

7. Control device for an internal combustion engine with a multiprocessor system according to one of the preceding claims, characterized in that the processor (1) receives the highest priority operating data (11) of the internal combustion engine, that a processor (2) low priority controls the internal combustion engine, preferably on Sprit zz eit s and injection quantities and then controls injectors (12) of the internal combustion engine, and that the processor (2) low priority receives default data for control via the common memory (4) from the processor (1) highest priority.

8. Control device according to claim 7, characterized in that the processor (2) receives lower priority operating data (13) of the internal combustion engine and the processor (1) transmits highest priority via the common memory (4).