EP0203125A1 - Dispositif d'elimination du scintillement entre les lignes. - Google Patents

Dispositif d'elimination du scintillement entre les lignes.

Info

Publication number
EP0203125A1
EP0203125A1 EP85905814A EP85905814A EP0203125A1 EP 0203125 A1 EP0203125 A1 EP 0203125A1 EP 85905814 A EP85905814 A EP 85905814A EP 85905814 A EP85905814 A EP 85905814A EP 0203125 A1 EP0203125 A1 EP 0203125A1
Authority
EP
European Patent Office
Prior art keywords
additional
amplifier
winding
additional deflection
coincidence
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP85905814A
Other languages
German (de)
English (en)
Other versions
EP0203125B1 (fr
Inventor
Gunter Gleim
Uwe Hartmann
Udo Mai
Fritz Ohnemus
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Deutsche Thomson Brandt GmbH
Original Assignee
Deutsche Thomson Brandt GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Deutsche Thomson Brandt GmbH filed Critical Deutsche Thomson Brandt GmbH
Priority to AT85905814T priority Critical patent/ATE55024T1/de
Publication of EP0203125A1 publication Critical patent/EP0203125A1/fr
Application granted granted Critical
Publication of EP0203125B1 publication Critical patent/EP0203125B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G1/00—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data
    • G09G1/04—Deflection circuits ; Constructional details not otherwise provided for

Definitions

  • the invention relates to a device for eliminating the intermittent lenflimmer when displaying graphic characters on a picture display screen, for example a television screen, together with a television picture.
  • the television signal broadcast according to the television standard is reproduced according to the interlaced method.
  • the purpose of this is to increase the flicker frequency in such a way that it is practically imperceptible.
  • the interlaced method a television picture is generated in that two successively written fields with a number of k plus 1/2 lines each are reproduced, the fields being interleaved like a comb by alternately writing the even-numbered lines and the odd-numbered lines. This increases the frame rate for a full screen.
  • this interlacing method has a major disadvantage, because the so-called interlaced flicker appears in a stack especially when standing Images, especially graphic drawings, are to be reproduced. Intermediate line flickering is particularly pronounced in horizontal lines. It is therefore known to switch off the interlacing when playing such characters by writing two fields one above the other. As a result, the inter-line flicker characterized by the vertical unrest of the character shown is no longer visible (DE-AS 29 49 020).
  • the invention has for its object to eliminate the interline flicker for the display of faded-in graphical characters without deteriorating the quality of a television signal received at the same time. This object is achieved by the invention specified in the patent claim. Further embodiments of the invention result from the subclaims.
  • the invention has the advantage that the interlacing for the television signal and thus the quality of the entire image is now retained even in the horizontal direction during the simultaneous reproduction of a television signal and a graphic character.
  • Figure 1 shows the circuit arrangement of the invention
  • Figure 2 shows the arrangement of the invention in a television receiver.
  • the Btx decoder supplies, for example, a fade-out signal that serves to blank out the underlying television signal during the character insertion in order to increase the contrast of the character.
  • This fade-out signal is ANDed in conjunction with the half-image detection signal.
  • the fade-out signal FB (fast-blanking) is based on an NFN Put transistor 1, the collector of which is connected via a load resistor 2 to the operating voltage source UB.
  • the emitter of transistor 1 is connected to ground via a resistor 3.
  • the field detection signal HK is applied to the emitter via a series resistor 4, which only switches the transistor 1 conductive for the duration of one field.
  • the base of a further PNP transistor 5 is connected to the collector of the transistor 1, the emitter of which is connected to the operating voltage source UB via the resistor 6 and an additional deflection coil pair is connected in the collector circuit which is arranged in the vicinity of the vertical main deflection winding on the picture tube neck such that the current flowing through this causes the additional vertical shift of the electron beam.
  • the described additional deflection generator switches off the interlacing only for the duration of the displayed character. He must therefore be able to switch the video frequency on and off.
  • the switchover time is of the order of 200 ms.
  • the main deflection coil is therefore unsuitable for switching off the interlacing because of its large inductance and the winding capacity.
  • the existing deflection amplifier is also not able to generate the required rapid changes in the current.
  • a deflection generator with a limit frequency of 4.5 MHz is therefore required.
  • the required deflection power can be applied.
  • the time constant L / R must be small because of the high switching speed. It is very cost-effective to use a scule printed on a foil, which is placed around the tube shark. It is essential that the transistors of the deflection generator are not saturated range are controlled so that the switching process is not delayed due to stored charge carriers. The operating point of the transistors of the additional deflection generator is selected accordingly. Because of the low deflection power, small transistors are sufficient.
  • the deflection generator is expediently arranged on the mounting plate 8 of the television picture tube 9, as shown in FIG. It is essential that the feed line 10 to the additional deflection coil 7 is very short in order to keep the feed inductance small. From the pair of steering coils is located on the tube neck of the picture tube 9 below the steering unit 12, which is partially cut open for the detection of the deflection coil 7. A plug connection 11 connects the circuit of the deflection generator with the signal voltage and operating voltage sources located on the device chassis.

Landscapes

  • Engineering & Computer Science (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Remote Sensing (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Details Of Television Scanning (AREA)

Abstract

Un dispositif permet de reproduire sans scintillements des signaux mélangés de décodeurs VT et/ou BTX pendant la reproduction de signaux de télévision (exploitation mixte). Ceci est obtenu par une compensation du champ de balayage de fréquence vidéo dans le sens vertical effectué par un amplificateur connectable supplémentaire de balayage de fréquence vidéo, qui alimente un enroulement de balayage supplémentaire à inductivité réduite.
EP85905814A 1984-11-16 1985-11-16 Dispositif d'elimination du scintillement entre les lignes Expired - Lifetime EP0203125B1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AT85905814T ATE55024T1 (de) 1984-11-16 1985-11-16 Einrichtung zur beseitigung des zwischenzeilenflimmerns.

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE3441905 1984-11-16
DE19843441905 DE3441905A1 (de) 1984-11-16 1984-11-16 Einrichtung zur beseitigung des zwischenzeilenflimmerns

Publications (2)

Publication Number Publication Date
EP0203125A1 true EP0203125A1 (fr) 1986-12-03
EP0203125B1 EP0203125B1 (fr) 1990-07-25

Family

ID=6250456

Family Applications (1)

Application Number Title Priority Date Filing Date
EP85905814A Expired - Lifetime EP0203125B1 (fr) 1984-11-16 1985-11-16 Dispositif d'elimination du scintillement entre les lignes

Country Status (4)

Country Link
EP (1) EP0203125B1 (fr)
JP (1) JPS62501464A (fr)
DE (2) DE3441905A1 (fr)
WO (1) WO1986003046A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DK159354C (da) * 1987-08-26 1991-03-11 Bang & Olufsen As Fjernsynsmodtager med midler til undertrykkelse aflinieflicker

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2233703B1 (fr) * 1973-06-13 1976-04-30 Cit Alcatel
ZA806148B (en) * 1979-10-15 1982-05-26 Philips Nv Picture display device arranged for displaying a mixed picture signal as an interlaced television picture
NL8002410A (nl) * 1979-10-15 1981-04-21 Philips Nv Beeldweergeefinrichting ingericht voor het als een geinterlinieerd televisie-beeld weergeven van een gemengd beeldsignaal.
EP0053207B1 (fr) * 1980-11-28 1984-08-15 International Business Machines Corporation Dispositif de réduction du scintillement d'un dispositif d'affichage à tube cathodique à balayage à trame
US4415889A (en) * 1980-12-18 1983-11-15 Rca Corporation Raster-scanned CRT display system with improved positional resolution for digitally encoded graphics
JPS5854394A (ja) * 1981-09-28 1983-03-31 ソニー株式会社 包絡線信号制御回路

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO8603046A1 *

Also Published As

Publication number Publication date
WO1986003046A1 (fr) 1986-05-22
DE3441905A1 (de) 1986-05-28
JPS62501464A (ja) 1987-06-11
DE3578909D1 (de) 1990-08-30
EP0203125B1 (fr) 1990-07-25

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