EP0201599A1 - Fabrication de dispositifs semi-conducteurs a entailles. - Google Patents

Fabrication de dispositifs semi-conducteurs a entailles.

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Publication number
EP0201599A1
EP0201599A1 EP86900681A EP86900681A EP0201599A1 EP 0201599 A1 EP0201599 A1 EP 0201599A1 EP 86900681 A EP86900681 A EP 86900681A EP 86900681 A EP86900681 A EP 86900681A EP 0201599 A1 EP0201599 A1 EP 0201599A1
Authority
EP
European Patent Office
Prior art keywords
oxide layer
groove
native oxide
mask
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP86900681A
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German (de)
English (en)
Other versions
EP0201599B1 (fr
Inventor
William Cross Dautremont-Smith
Daniel Paul Wilt
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
American Telephone and Telegraph Co Inc
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Filing date
Publication date
Application filed by American Telephone and Telegraph Co Inc filed Critical American Telephone and Telegraph Co Inc
Publication of EP0201599A1 publication Critical patent/EP0201599A1/fr
Application granted granted Critical
Publication of EP0201599B1 publication Critical patent/EP0201599B1/fr
Expired legal-status Critical Current

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    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
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Definitions

  • This invention relates to the manufacture of semiconductor devices using etch masks and processing for forming grooves in semiconductor material.
  • Grooves are etched in semiconductor material for a variety of applications.
  • V-grooves are etched in silicon substrates to form guides for aligning arrays of optical fibers.
  • V-grooves are also etched into Group III-V compound semiconductors in the fabrication of various buried heterostructure (BH) lasers.
  • BH buried heterostructure
  • V- groove 24 bifurcates a blocking p-n junction in an InP substrate, and liquid phase epitaxy (LPE) is used to grow a double heterostructure (DH) of InP-InGaAsP-InP layers in the V-groove.
  • LPE liquid phase epitaxy
  • the InGaAsP active layer 12 of the CSBH laser has the shape of a crescent, and the cross-sectional area of that layer must be accurately controlled in order to insure, inter alia, fundamental transverse mode, low threshold operation.
  • These desiderata are, in turn, determined by the shape of the V-groove and the position of the active layer therein.
  • fundamental transverse mode operation up to optical output powers of 10 m /facet requires the width of the active layer to be 2.5 ym.
  • the grooves preferably are aligned parallel to the [011] direction on the (100) surface, in order that the side walls of the groove are (111 )B crystallographic planes.
  • the (111 )B planes prevent n-InP buffer layer growth on the groove wall, thus eliminating an undesirable leakage current path around the active layer.
  • the shape of the V-groove is a function of numerous parameters: (1) the particular semiconductor material, (2) the etchant and etching conditions, (3) the crystallographic orientation of the surface being etched, (4) the orientation of the etch mask, (5) the nature of the etch mask material, (6) the extent to which the etchant undercuts the mask, and so forth.
  • the groove oftentimes does not have the precise shape of a V at all, which for CSBH lasers renders it exceedingly difficult to control the dimensions of the critical active layer.
  • FIGS. 2-4 illustrate the problem of etching a groove aligned parallel to the [011] direction on the (100) surface of InP. When essentially no undercutting of the etch mask occurs, as shown in FIG.
  • the bottom of the groove has the desired V-shape with oblique (111 )B walls, but the top of the groove disadvantageously has vertical (01T) walls.
  • the groove has the desired (111 )B sidewalls, but the bottom of the groove is flat [a (100) plane] rather than pointed and the groove is much wider.
  • the groove has the proper V-shape with a pointed bottom and only (111 )B side walls.
  • the extent of undercutting can be controlled by interposing a thin native oxide layer between the etch mask and the semiconductor body to be etched.
  • V-grooves with (111 )B side walls and pointed bottoms can be etched parallel to the [011] direction in (100) surfaces of InP by controlling the undercutting of the etch mask to be approximately one third of the etch depth.
  • the undercutting is controlled by the thickness and growth conditions of the native oxide layer.
  • FIG. 1 is a schematic isometric view of a CSBH laser fabricated in accordance with one embodiment of our invention
  • FIGS. 2-4 show schematically various grooves etched in the [011] direction in the (100) surface of a Group III-V compound semiconductor, such as InP, as a function of the extent of mask undercutting; and
  • FIG. 5 shows schematically a composite etch mask for etching a V-groove in accordance with one embodiment of this invention.
  • the semiconductor light emitting device shown in FIG. 1 may be used as a laser or as an edge- emitting LED.
  • the device W_ includes- an active region 12 in which the recombination of electrons and holes causes radiation to be emitted at a wavelength characteristic of the bandgap of the semiconductor material of the active region (e.g., about 1.0-1.65 ym for InGaAsP depending on the specific composition of the alloy).
  • the radiation is directed generally along axis 14 and is primarily stimulated emission in the case of a laser and primarily spontaneous emission in the case of an LED.
  • This recombination radiation is generated by forward-biasing a p-n junction which causes minority carriers to be injected into the active region.
  • Source 16 illustratively depicted as a battery in series with a current-limiting resistor, supplies the forward bias voltage and, in addition, provides pumping current at a level commensurate with the desired optical output power. In a laser, the pumping current exceeds the lasing current threshold.
  • the device includes means for constraining the pumping current to flow in a relatively narrow channel through the active region 12.
  • this constraining means comprises a bifurcated, blocking p-n junction 21 (marked with x*s for clarity) formed at the interface between n-InP layer 26 and p-InP layer 20.
  • the constraining means may comprise a high resistivity Fe-doped MOCVD InP layer substituted for p-InP layer 20.
  • the active region 12 has the shape of a stripe which lies in the rectangular opening of the bifurcated layer 20. Note, in the case of a surface emitting LED the layer 20, rather than being bifurcated, -might take the shape of an annulus surrounding a cylindrical or mesa-like active region.
  • a groove is etched through that layer into substrate 22.
  • this etching technique entails the use of a composite etch mask, shown in FIG. 5, comprising a thin . (e.g., 2.0 nm) native oxide layer 23 formed on the top of layer 20, a (100)-oriented InP surface, and a Si0 2 layer 25 plasma-deposited onto layer 23.
  • the mask is patterned using standard photolithography and etching so that a plurality of mask openings is formed parallel to the [011] direction, and V-grooves 24 with only (111 )B-oriented side walls are formed by subjecting the masked wafer to HCl-rich etchants (only one V-groove 24 is shown for simplicity) . Further details of this V-groove forming process are discussed hereinafter.
  • n-InP first cladding layer 26 (the central portion of which fills at least the bottom portion of groove 24); an unintentionally doped InGaAsP layer 28; a p- InP second cladding layer 30; and a p-InGaAs (or p-InGaAsP) contact facilitating layer 32.
  • Layer 28. includes crescent- shaped active region 12 which, in practice, becomes separated from the remainder of layer 28 because epitaxial growth does not take place along the top edges of the groove 24.
  • the active layer is ' vertically positioned within the thickness of layer 20 in order to reduce leakage current.
  • Source 16 is connected across electrodes 34 and 36.
  • a broad-area contact is depicted by layer 32 and electrode 34, it also is possible to delineate a stripe geometry contact; i.e., the contact-facilitating layer 32 would be etched to form a stripe, and the stripe- shaped opening of a dielectric layer would be positioned within this stripe. A broad area electrode would then be formed over the top of the device.
  • a contact configuration of this type reduces device capacitance and hence increases high speed performance.
  • the device of FIG. 1 when used as a laser, also includes means for providing optical feedback of the stimulated emission, typically a pair of separated, parallel, cleaved facets 38 and 40 which form an optical cavity resonator.
  • the optical axis of the resonator and the elongated direction of the stripe-shaped active region 12 are generally parallel to one another.
  • Other feedback techniques are also suitable, however, including well-known distributed feedback gratings, for example.
  • V-groove Etching The following examples are provided by way of illustration only. Specific parameters, compositions, materials and the like are not to be construed as limiting the scope of the invention unless otherwise stated.
  • V-grooves were etched in masked, ( 100)-oriented InP wafers using freshly prepared HC1:H3P04 solution at room temperature without agitation. Room temperature is the preferred temperature for forming smooth-walled grooves with this etchant.
  • the etching solution comprised 3 parts by volume of 37% aqueous HC1 and 1 part by volume of 85% aqueous H3PO4. Etching was also performed using an mixture of lower HC1 content.
  • VPE vapor phase epitaxy
  • Etch masks of thickness 120-300 nm were deposited by the following processes. After organic solvent cleaning, all wafers were etched in 10.1 H 2 0:HF by volume, from which they were withdrawn virtually completely de-wetted, verifying native oxide removal. After being blown dry with N 2 , they were transferred to the oxide growth environment. VPE and MOCVD grown material was, in addition, etched for 1-5 minutes at room temperature in 10:1:1 H 2 S0 4 :H2 ⁇ 2:H 2 0 by volume prior to the dilute HF native oxide removal, in order to remove a surface layer which adversely affected mask adhesion during groove etching.
  • Cd-diffused InP was etched for at least 16 minutes in the same 10:1:1 etchant in order to remove a 0.2 ⁇ m surface layer containing excess, non-electrically- active Cd, as well as to fine-tune the p-n junction depth to the optimum value to minimize leakage current in the subsequently grown lasers.
  • Plasma oxidation at 13.56 MHz of InP wafers resting on a grounded table was performed at 250°C in pure N 2 0 or in either 2% or 0.51% N 2 0 in Ar at low power density ("0.05 Wcm ) and for times of the order of a few seconds.
  • Thermal growths within the plasma deposition chamber were carried out at substrate table temperatures up to 395°C and pressures up to 79.993 Pa (600 Torr) of 2 0 for times of the order of 10 minutes.
  • Atmospheric pressure thermal growths in air and N 2 0 were at 320°C to 375°C in an evacuable tube furnace for times also of the order of 10 minutes. In these cases the thickness of the thermally grown native oxide was self- limiting as a function of temperature.
  • the Si0 2 etch mask was photolithographically patterned to open up 2 to 3 ⁇ m wide windows aligned parallel to the [011] crystal direction.
  • etchants will produce V-profile grooves in the perpendicular [01T] direction without need for mask undercut, but these grooves are not suitable for subsequent LPE growth.
  • HC1:H3P04 etching was performed after photoresist removal, organic solvent cleaning, and a brief etch in 10:1:1 H 2 S0 4 :H 2 0 2 :H 2 0 by volume. After etching, sections were cleaved perpendicularly to the windows and the channel cross-sections examined in an SEM at x5K and x10K magnification with the Si ⁇ 2 mask in place.
  • Example 1 Plasma Native Oxide on LEC InP
  • the preferred profile of FIG. 5 was achieved in accordance with this invention by interposing a native oxide layer 23 about 2.0 nm + 0.2 nm thick between the mask 25 and the InP.
  • the native oxide was grown by Ar:N 2 0 plasma exposure for about 8 seconds at 250°C immediately prior to the plasma deposition of the Si ⁇ 2 mask 25.
  • the ratio of etch depth to undercut was 2.7.
  • D/u 3.0 Such a profile has also been obtained with sputtered Si0 2 masks deposited in both 5.2% and- 21% O2 in Ar sputtering atmospheres.
  • the substrate was rotated into the plasma beneath the Si ⁇ 2 target, it was exposed for a few seconds to the oxygen-containing plasma, thus forming a native oxide just before the Si0 2 deposition began.
  • the native oxide layer was again confirmed as being responsible for controlling the amount of undercutting and producing the desired V-groove profile of FIG. 5.
  • profiles of the type shown in FIG. 2 were produced when no native oxide layer was grown, and profiles of the type shown in FIG. 3 were produced whe .
  • t e native oxide layer was too thick (e.g., 3.4 nm) .
  • FIG. 5 was etched into VPE (100)-oriented InP through a 2.0 ⁇ m Si0 2 mask opening using a 25 sec etch in 3:1 HC1:H P0 4 .
  • An undercut of about 1.1 ⁇ m was produced by a plasma-grown native oxide layer about 2.0 nm thick.
  • Plasma oxidation conditions were 5.0 sec exposure to 0.050 Wc "2 of RF power at 13.56 MHz in 59.995 Pa (450 mTorr) of Ar:0.51% N 2 0 at 250°C.
  • Example 3 Plasma Native Oxide on MOCVD InP
  • Example 4 Thermal Native Oxide on VGF InP This example utilized Cd-diffused ( 100)-oriented
  • VGF InP VGF InP.
  • thermal oxidation was performed in the Si ⁇ 2 plasma deposition chamber at 380°C in about 0.5 atm. of dry N 2 0 for 10 minutes, at which time the native oxide had reached its self-limiting thickness of about 2.0 nm.
  • Example 5 Thermal Native Oxide on LEC InP
  • the Si0 layer was patterned using standard photolithography and plasma etching. Then the V-groove was etched in 3:1 HC1:H3P0 4 by volume at room temperature for about 25 sec.

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Abstract

Fabrication de dispositifs semi-conducteurs en utilisant des masques et des techniques de gravure pour former des entailles dans le matériau semi-conducteur. Des entailles en V sont pratiquées dans les semi-conducteurs composites du groupe III-V en utilisant un masque composite comprenant une mince couche d'oxyde naturel (par ex. 23) sur le semi-conducteur (par ex. 20) et un masque de gravure diélectrique (par ex. 25) sur l'oxyde naturel. Est décrite en détail l'application de cette technique à la gravure d'entailles en V dans l'InP pour la fabrication de lasers CSBH InP/InGaAsP.
EP86900681A 1984-06-15 1985-05-16 Fabrication de dispositifs semi-conducteurs a entailles Expired EP0201599B1 (fr)

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US06/621,080 US4595454A (en) 1984-06-15 1984-06-15 Fabrication of grooved semiconductor devices
US621080 1984-06-15

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JPS61502509A (ja) 1986-10-30
DE3573191D1 (en) 1989-10-26
WO1986001367A2 (fr) 1986-03-13
WO1986001367A3 (fr) 1986-07-17
EP0201599B1 (fr) 1989-09-20
US4595454A (en) 1986-06-17
CA1225465A (fr) 1987-08-11

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