WO1986001367A2 - The fabrication of grooved semiconductor devices - Google Patents

The fabrication of grooved semiconductor devices Download PDF

Info

Publication number
WO1986001367A2
WO1986001367A2 PCT/US1985/000918 US8500918W WO8601367A2 WO 1986001367 A2 WO1986001367 A2 WO 1986001367A2 US 8500918 W US8500918 W US 8500918W WO 8601367 A2 WO8601367 A2 WO 8601367A2
Authority
WO
WIPO (PCT)
Prior art keywords
oxide layer
native oxide
groove
mask
layer
Prior art date
Application number
PCT/US1985/000918
Other languages
French (fr)
Other versions
WO1986001367A3 (en
Inventor
William Crossley Dautremont-Smith
Daniel Paul Wilt
Original Assignee
American Telephone & Telegraph Company
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by American Telephone & Telegraph Company filed Critical American Telephone & Telegraph Company
Priority to JP86500738A priority Critical patent/JPS61502509A/en
Priority to DE8686900681T priority patent/DE3573191D1/en
Publication of WO1986001367A2 publication Critical patent/WO1986001367A2/en
Publication of WO1986001367A3 publication Critical patent/WO1986001367A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02241—III-V semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02252—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by plasma treatment, e.g. plasma oxidation of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02266—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30612—Etching of AIIIBV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30612—Etching of AIIIBV compounds
    • H01L21/30617—Anisotropic liquid etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604—Deposition from a gas or vapour
    • H01L21/31608—Deposition of SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/3165—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation
    • H01L21/31654—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/3165—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation
    • H01L21/31654—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself
    • H01L21/31658—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe

Definitions

  • This invention relates to the manufacture of semiconductor devices using etch masks and processing for forming grooves in semiconductor material.
  • Grooves are etched in semiconductor material for a variety of applications.
  • V-grooves are etched in silicon substrates to form guides for aligning arrays of optical fibers.
  • V-grooves are also etched into Group III-V compound semiconductors in the fabrication of various buried heterostructure (BH) lasers.
  • BH buried heterostructure
  • V- groove 24 bifurcates a blocking p-n junction in an InP substrate, and liquid phase epitaxy (LPE) is used to grow a double heterostructure (DH) of InP-InGaAsP-InP layers in the V-groove.
  • LPE liquid phase epitaxy
  • the InGaAsP active layer 12 of the CSBH laser has the shape of a crescent, and the cross-sectional area of that layer must be accurately controlled in order to insure, inter alia, fundamental transverse mode, low threshold operation.
  • These desiderata are, in turn, determined by the shape of the V-groove and the position of the active layer therein.
  • fundamental transverse mode operation up to optical output powers of 10 m /facet requires the width of the active layer to be 2.5 ym.
  • the grooves preferably are aligned parallel to the [011] direction on the (100) surface, in order that the side walls of the groove are (111 )B crystallographic planes.
  • the (111 )B planes prevent n-InP buffer layer growth on the groove wall, thus eliminating an undesirable leakage current path around the active layer.
  • the shape of the V-groove is a function of numerous parameters: (1) the particular semiconductor material, (2) the etchant and etching conditions, (3) the crystallographic orientation of the surface being etched, (4) the orientation of the etch mask, (5) the nature of the etch mask material, (6) the extent to which the etchant undercuts the mask, and so forth.
  • the groove oftentimes does not have the precise shape of a V at all, which for CSBH lasers renders it exceedingly difficult to control the dimensions of the critical active layer.
  • FIGS. 2-4 illustrate the problem of etching a groove aligned parallel to the [011] direction on the (100) surface of InP. When essentially no undercutting of the etch mask occurs, as shown in FIG.
  • the bottom of the groove has the desired V-shape with oblique (111 )B walls, but the top of the groove disadvantageously has vertical (01T) walls.
  • the groove has the desired (111 )B sidewalls, but the bottom of the groove is flat [a (100) plane] rather than pointed and the groove is much wider.
  • the groove has the proper V-shape with a pointed bottom and only (111 )B side walls.
  • the extent of undercutting can be controlled by interposing a thin native oxide layer between the etch mask and the semiconductor body to be etched.
  • V-grooves with (111 )B side walls and pointed bottoms can be etched parallel to the [011] direction in (100) surfaces of InP by controlling the undercutting of the etch mask to be approximately one third of the etch depth.
  • the undercutting is controlled by the thickness and growth conditions of the native oxide layer.
  • FIG. 1 is a schematic isometric view of a CSBH laser fabricated in accordance with one embodiment of our invention
  • FIGS. 2-4 show schematically various grooves etched in the [011] direction in the (100) surface of a Group III-V compound semiconductor, such as InP, as a function of the extent of mask undercutting; and
  • FIG. 5 shows schematically a composite etch mask for etching a V-groove in accordance with one embodiment of this invention.
  • the semiconductor light emitting device shown in FIG. 1 may be used as a laser or as an edge- emitting LED.
  • the device W_ includes- an active region 12 in which the recombination of electrons and holes causes radiation to be emitted at a wavelength characteristic of the bandgap of the semiconductor material of the active region (e.g., about 1.0-1.65 ym for InGaAsP depending on the specific composition of the alloy).
  • the radiation is directed generally along axis 14 and is primarily stimulated emission in the case of a laser and primarily spontaneous emission in the case of an LED.
  • This recombination radiation is generated by forward-biasing a p-n junction which causes minority carriers to be injected into the active region.
  • Source 16 illustratively depicted as a battery in series with a current-limiting resistor, supplies the forward bias voltage and, in addition, provides pumping current at a level commensurate with the desired optical output power. In a laser, the pumping current exceeds the lasing current threshold.
  • the device includes means for constraining the pumping current to flow in a relatively narrow channel through the active region 12.
  • this constraining means comprises a bifurcated, blocking p-n junction 21 (marked with x*s for clarity) formed at the interface between n-InP layer 26 and p-InP layer 20.
  • the constraining means may comprise a high resistivity Fe-doped MOCVD InP layer substituted for p-InP layer 20.
  • the active region 12 has the shape of a stripe which lies in the rectangular opening of the bifurcated layer 20. Note, in the case of a surface emitting LED the layer 20, rather than being bifurcated, -might take the shape of an annulus surrounding a cylindrical or mesa-like active region.
  • a groove is etched through that layer into substrate 22.
  • this etching technique entails the use of a composite etch mask, shown in FIG. 5, comprising a thin . (e.g., 2.0 nm) native oxide layer 23 formed on the top of layer 20, a (100)-oriented InP surface, and a Si0 2 layer 25 plasma-deposited onto layer 23.
  • the mask is patterned using standard photolithography and etching so that a plurality of mask openings is formed parallel to the [011] direction, and V-grooves 24 with only (111 )B-oriented side walls are formed by subjecting the masked wafer to HCl-rich etchants (only one V-groove 24 is shown for simplicity) . Further details of this V-groove forming process are discussed hereinafter.
  • n-InP first cladding layer 26 (the central portion of which fills at least the bottom portion of groove 24); an unintentionally doped InGaAsP layer 28; a p- InP second cladding layer 30; and a p-InGaAs (or p-InGaAsP) contact facilitating layer 32.
  • Layer 28. includes crescent- shaped active region 12 which, in practice, becomes separated from the remainder of layer 28 because epitaxial growth does not take place along the top edges of the groove 24.
  • the active layer is ' vertically positioned within the thickness of layer 20 in order to reduce leakage current.
  • Source 16 is connected across electrodes 34 and 36.
  • a broad-area contact is depicted by layer 32 and electrode 34, it also is possible to delineate a stripe geometry contact; i.e., the contact-facilitating layer 32 would be etched to form a stripe, and the stripe- shaped opening of a dielectric layer would be positioned within this stripe. A broad area electrode would then be formed over the top of the device.
  • a contact configuration of this type reduces device capacitance and hence increases high speed performance.
  • the device of FIG. 1 when used as a laser, also includes means for providing optical feedback of the stimulated emission, typically a pair of separated, parallel, cleaved facets 38 and 40 which form an optical cavity resonator.
  • the optical axis of the resonator and the elongated direction of the stripe-shaped active region 12 are generally parallel to one another.
  • Other feedback techniques are also suitable, however, including well-known distributed feedback gratings, for example.
  • V-groove Etching The following examples are provided by way of illustration only. Specific parameters, compositions, materials and the like are not to be construed as limiting the scope of the invention unless otherwise stated.
  • V-grooves were etched in masked, ( 100)-oriented InP wafers using freshly prepared HC1:H3P04 solution at room temperature without agitation. Room temperature is the preferred temperature for forming smooth-walled grooves with this etchant.
  • the etching solution comprised 3 parts by volume of 37% aqueous HC1 and 1 part by volume of 85% aqueous H3PO4. Etching was also performed using an mixture of lower HC1 content.
  • VPE vapor phase epitaxy
  • Etch masks of thickness 120-300 nm were deposited by the following processes. After organic solvent cleaning, all wafers were etched in 10.1 H 2 0:HF by volume, from which they were withdrawn virtually completely de-wetted, verifying native oxide removal. After being blown dry with N 2 , they were transferred to the oxide growth environment. VPE and MOCVD grown material was, in addition, etched for 1-5 minutes at room temperature in 10:1:1 H 2 S0 4 :H2 ⁇ 2:H 2 0 by volume prior to the dilute HF native oxide removal, in order to remove a surface layer which adversely affected mask adhesion during groove etching.
  • Cd-diffused InP was etched for at least 16 minutes in the same 10:1:1 etchant in order to remove a 0.2 ⁇ m surface layer containing excess, non-electrically- active Cd, as well as to fine-tune the p-n junction depth to the optimum value to minimize leakage current in the subsequently grown lasers.
  • Plasma oxidation at 13.56 MHz of InP wafers resting on a grounded table was performed at 250°C in pure N 2 0 or in either 2% or 0.51% N 2 0 in Ar at low power density ("0.05 Wcm ) and for times of the order of a few seconds.
  • Thermal growths within the plasma deposition chamber were carried out at substrate table temperatures up to 395°C and pressures up to 79.993 Pa (600 Torr) of 2 0 for times of the order of 10 minutes.
  • Atmospheric pressure thermal growths in air and N 2 0 were at 320°C to 375°C in an evacuable tube furnace for times also of the order of 10 minutes. In these cases the thickness of the thermally grown native oxide was self- limiting as a function of temperature.
  • the Si0 2 etch mask was photolithographically patterned to open up 2 to 3 ⁇ m wide windows aligned parallel to the [011] crystal direction.
  • etchants will produce V-profile grooves in the perpendicular [01T] direction without need for mask undercut, but these grooves are not suitable for subsequent LPE growth.
  • HC1:H3P04 etching was performed after photoresist removal, organic solvent cleaning, and a brief etch in 10:1:1 H 2 S0 4 :H 2 0 2 :H 2 0 by volume. After etching, sections were cleaved perpendicularly to the windows and the channel cross-sections examined in an SEM at x5K and x10K magnification with the Si ⁇ 2 mask in place.
  • Example 1 Plasma Native Oxide on LEC InP
  • the preferred profile of FIG. 5 was achieved in accordance with this invention by interposing a native oxide layer 23 about 2.0 nm + 0.2 nm thick between the mask 25 and the InP.
  • the native oxide was grown by Ar:N 2 0 plasma exposure for about 8 seconds at 250°C immediately prior to the plasma deposition of the Si ⁇ 2 mask 25.
  • the ratio of etch depth to undercut was 2.7.
  • D/u 3.0 Such a profile has also been obtained with sputtered Si0 2 masks deposited in both 5.2% and- 21% O2 in Ar sputtering atmospheres.
  • the substrate was rotated into the plasma beneath the Si ⁇ 2 target, it was exposed for a few seconds to the oxygen-containing plasma, thus forming a native oxide just before the Si0 2 deposition began.
  • the native oxide layer was again confirmed as being responsible for controlling the amount of undercutting and producing the desired V-groove profile of FIG. 5.
  • profiles of the type shown in FIG. 2 were produced when no native oxide layer was grown, and profiles of the type shown in FIG. 3 were produced whe .
  • t e native oxide layer was too thick (e.g., 3.4 nm) .
  • FIG. 5 was etched into VPE (100)-oriented InP through a 2.0 ⁇ m Si0 2 mask opening using a 25 sec etch in 3:1 HC1:H P0 4 .
  • An undercut of about 1.1 ⁇ m was produced by a plasma-grown native oxide layer about 2.0 nm thick.
  • Plasma oxidation conditions were 5.0 sec exposure to 0.050 Wc "2 of RF power at 13.56 MHz in 59.995 Pa (450 mTorr) of Ar:0.51% N 2 0 at 250°C.
  • Example 3 Plasma Native Oxide on MOCVD InP
  • Example 4 Thermal Native Oxide on VGF InP This example utilized Cd-diffused ( 100)-oriented
  • VGF InP VGF InP.
  • thermal oxidation was performed in the Si ⁇ 2 plasma deposition chamber at 380°C in about 0.5 atm. of dry N 2 0 for 10 minutes, at which time the native oxide had reached its self-limiting thickness of about 2.0 nm.
  • Example 5 Thermal Native Oxide on LEC InP
  • the Si0 layer was patterned using standard photolithography and plasma etching. Then the V-groove was etched in 3:1 HC1:H3P0 4 by volume at room temperature for about 25 sec.

Abstract

Manufacture of semiconductor devices using etch masks and processing for forming grooves in semiconductor material. V-grooves are etched in Group III-V compound semiconductors using a composite mask comprising a thin native oxide layer (e.g. 23) on the semiconductor (e.g. 20) and a dielectric etch mask (e.g. 25) on the native oxide. Described in detail is the application of this technique to etching V-grooves in InP for the fabrication of CSBH InP/InGaAsP lasers.

Description

THE FABRICATION OF GROOVED SEMICONDUCTOR DEVICES
Background of the Invention
This invention relates to the manufacture of semiconductor devices using etch masks and processing for forming grooves in semiconductor material.
Grooves are etched in semiconductor material for a variety of applications. In one case, V-grooves are etched in silicon substrates to form guides for aligning arrays of optical fibers. On the other hand, V-grooves are also etched into Group III-V compound semiconductors in the fabrication of various buried heterostructure (BH) lasers. For example, in one design of the channeled substrate buried heterostructure (CSBH) laser, as shown in FIG. 1, V- groove 24 bifurcates a blocking p-n junction in an InP substrate, and liquid phase epitaxy (LPE) is used to grow a double heterostructure (DH) of InP-InGaAsP-InP layers in the V-groove. The InGaAsP active layer 12 of the CSBH laser has the shape of a crescent, and the cross-sectional area of that layer must be accurately controlled in order to insure, inter alia, fundamental transverse mode, low threshold operation. These desiderata are, in turn, determined by the shape of the V-groove and the position of the active layer therein. For example, fundamental transverse mode operation up to optical output powers of 10 m /facet requires the width of the active layer to be 2.5 ym. To achieve this dimension epitaxial growth in a sharp- bottom groove is necessary. In addition, the grooves preferably are aligned parallel to the [011] direction on the (100) surface, in order that the side walls of the groove are (111 )B crystallographic planes. The (111 )B planes prevent n-InP buffer layer growth on the groove wall, thus eliminating an undesirable leakage current path around the active layer.
The shape of the V-groove is a function of numerous parameters: (1) the particular semiconductor material, (2) the etchant and etching conditions, (3) the crystallographic orientation of the surface being etched, (4) the orientation of the etch mask, (5) the nature of the etch mask material, (6) the extent to which the etchant undercuts the mask, and so forth. Indeed, the groove oftentimes does not have the precise shape of a V at all, which for CSBH lasers renders it exceedingly difficult to control the dimensions of the critical active layer. FIGS. 2-4 illustrate the problem of etching a groove aligned parallel to the [011] direction on the (100) surface of InP. When essentially no undercutting of the etch mask occurs, as shown in FIG. 2, the bottom of the groove has the desired V-shape with oblique (111 )B walls, but the top of the groove disadvantageously has vertical (01T) walls. In contrast, for the same size mask opening * and etching depth D, when excessive undercutting occurs as shown in FIG. 3, the groove has the desired (111 )B sidewalls, but the bottom of the groove is flat [a (100) plane] rather than pointed and the groove is much wider. On the other hand, if undercutting is carefully controlled, as shown in FIG. 4, the groove has the proper V-shape with a pointed bottom and only (111 )B side walls. Summary of the Invention
When etching a groove into Group III-V compound semiconductors, the extent of undercutting can be controlled by interposing a thin native oxide layer between the etch mask and the semiconductor body to be etched. In addition, V-grooves with (111 )B side walls and pointed bottoms can be etched parallel to the [011] direction in (100) surfaces of InP by controlling the undercutting of the etch mask to be approximately one third of the etch depth. The undercutting, in turn, is controlled by the thickness and growth conditions of the native oxide layer. This process has been successfully employed in the manufacture of CSBH InP/InGaAsP lasers and by virtue of its good reproducibility has increased device yield. It is applicable as well, however, to other semiconductor devices which require the controlled etching of grooves to delineate active regions, current flow paths, and the like.
Brief Description of the Drawing This invention, together with its various features and advantages, can be readily understood from the following more detailed description taken in conjunction with the accompanying drawing, in which the figures are not drawn to scale in interests of clarity: FIG. 1 is a schematic isometric view of a CSBH laser fabricated in accordance with one embodiment of our invention;
FIGS. 2-4 show schematically various grooves etched in the [011] direction in the (100) surface of a Group III-V compound semiconductor, such as InP, as a function of the extent of mask undercutting; and
FIG. 5 shows schematically a composite etch mask for etching a V-groove in accordance with one embodiment of this invention. Detailed Description
For pedagogical purposes, this invention will be described initially with reference to the fabrication of CSBH light emitting devices.
CSBH Devices Thus, the semiconductor light emitting device shown in FIG. 1 may be used as a laser or as an edge- emitting LED. In either case, the device W_ includes- an active region 12 in which the recombination of electrons and holes causes radiation to be emitted at a wavelength characteristic of the bandgap of the semiconductor material of the active region (e.g., about 1.0-1.65 ym for InGaAsP depending on the specific composition of the alloy). The radiation is directed generally along axis 14 and is primarily stimulated emission in the case of a laser and primarily spontaneous emission in the case of an LED. This recombination radiation is generated by forward-biasing a p-n junction which causes minority carriers to be injected into the active region. Source 16, illustratively depicted as a battery in series with a current-limiting resistor, supplies the forward bias voltage and, in addition, provides pumping current at a level commensurate with the desired optical output power. In a laser, the pumping current exceeds the lasing current threshold.
In general, the device includes means for constraining the pumping current to flow in a relatively narrow channel through the active region 12. As illustrated, this constraining means comprises a bifurcated, blocking p-n junction 21 (marked with x*s for clarity) formed at the interface between n-InP layer 26 and p-InP layer 20. Alternatively, the constraining means may comprise a high resistivity Fe-doped MOCVD InP layer substituted for p-InP layer 20. In either case, the active region 12 has the shape of a stripe which lies in the rectangular opening of the bifurcated layer 20. Note, in the case of a surface emitting LED the layer 20, rather than being bifurcated, -might take the shape of an annulus surrounding a cylindrical or mesa-like active region.
In order to bifurcate layer 20 a groove is etched through that layer into substrate 22.
In accordance with one embodiment of this invention, this etching technique entails the use of a composite etch mask, shown in FIG. 5, comprising a thin . (e.g., 2.0 nm) native oxide layer 23 formed on the top of layer 20, a (100)-oriented InP surface, and a Si02 layer 25 plasma-deposited onto layer 23. The mask is patterned using standard photolithography and etching so that a plurality of mask openings is formed parallel to the [011] direction, and V-grooves 24 with only (111 )B-oriented side walls are formed by subjecting the masked wafer to HCl-rich etchants (only one V-groove 24 is shown for simplicity) . Further details of this V-groove forming process are discussed hereinafter.
The following essentially lattice-matched epitaxial layers are then grown by LPE on the etched wafer: an n-InP first cladding layer 26 (the central portion of which fills at least the bottom portion of groove 24); an unintentionally doped InGaAsP layer 28; a p- InP second cladding layer 30; and a p-InGaAs (or p-InGaAsP) contact facilitating layer 32. Layer 28. includes crescent- shaped active region 12 which, in practice, becomes separated from the remainder of layer 28 because epitaxial growth does not take place along the top edges of the groove 24. Preferably, the active layer is' vertically positioned within the thickness of layer 20 in order to reduce leakage current.
Electrical contact is made to the device via metal electrodes 34 and 36 on layer 32 and substrate 22, respectively. Source 16 is connected across electrodes 34 and 36.
Although a broad-area contact is depicted by layer 32 and electrode 34, it also is possible to delineate a stripe geometry contact; i.e., the contact-facilitating layer 32 would be etched to form a stripe, and the stripe- shaped opening of a dielectric layer would be positioned within this stripe. A broad area electrode would then be formed over the top of the device. A contact configuration of this type reduces device capacitance and hence increases high speed performance.
The device of FIG. 1, when used as a laser, also includes means for providing optical feedback of the stimulated emission, typically a pair of separated, parallel, cleaved facets 38 and 40 which form an optical cavity resonator. The optical axis of the resonator and the elongated direction of the stripe-shaped active region 12 are generally parallel to one another. Other feedback techniques are also suitable, however, including well-known distributed feedback gratings, for example. As mentioned previously, we will now describe in some detail the process for etching the V-groove 24 in accordance with our invention. V-groove Etching The following examples are provided by way of illustration only. Specific parameters, compositions, materials and the like are not to be construed as limiting the scope of the invention unless otherwise stated.
V-grooves were etched in masked, ( 100)-oriented InP wafers using freshly prepared HC1:H3P04 solution at room temperature without agitation. Room temperature is the preferred temperature for forming smooth-walled grooves with this etchant. The etching solution comprised 3 parts by volume of 37% aqueous HC1 and 1 part by volume of 85% aqueous H3PO4. Etching was also performed using an
Figure imgf000008_0001
mixture of lower HC1 content.
Five types of InP were used: S-doped, n-type
18 —3 (8 x 10 cm ) liquid encapsulated Czochralski
(LEC) substrates; Zn-doped, p-type
18 —3 (1 x 10 cm ) vapor phase epitaxy (VPE) grown- layers; Fe-doped, semi-insulating, metallo-organic chemical vapor deposited (S.I. MOCVD) layers; Fe-implanted, S.I. layers; and Cd-diffused p-type layers. The latter three were formed in or grown on InP substrates grown by a vertical gradient freeze (VGF) process. VPE layers (~2 μm thick) were grown on S-doped LEC substrates in well-known hydride transport reactors under a variety of growth conditions (gas phase supersaturation, diethyl zinc or elemental zinc doping source, and post-growth cool down in an H2 or H2/PH ambient) . MOCVD layers about
2 ym thick were grown at 700°C using (Me)3ln.P(Me)3 and PH3 as In and P sources, respectively, with ferrocene-based or iron pentacarbonyl-based compounds as the Fe dopant source. Cd diffusions were performed in a well-known leaky boat at 650°C from a Cd3P2/P4 source to a depth of "3 y .
Etch masks of thickness 120-300 nm were deposited by the following processes. After organic solvent cleaning, all wafers were etched in 10.1 H20:HF by volume, from which they were withdrawn virtually completely de-wetted, verifying native oxide removal. After being blown dry with N2, they were transferred to the oxide growth environment. VPE and MOCVD grown material was, in addition, etched for 1-5 minutes at room temperature in 10:1:1 H2S04:H2θ2:H20 by volume prior to the dilute HF native oxide removal, in order to remove a surface layer which adversely affected mask adhesion during groove etching. Cd-diffused InP was etched for at least 16 minutes in the same 10:1:1 etchant in order to remove a 0.2 μm surface layer containing excess, non-electrically- active Cd, as well as to fine-tune the p-n junction depth to the optimum value to minimize leakage current in the subsequently grown lasers.
After native oxide removal, air exposure time was usually <_ 6 minutes, although in one case it was varied from 2 to 15 minutes. One group of wafers was transferred directly to the vacuum chamber of a plasma deposition system, a well-known parallel plate, radial flow reactor. Of these wafers, some received plasma-deposited Siθ2 (or SiNχ in some cases) directly, whereas others underwent either plasma-enhanced _or purely thermal native oxide growth prior to Si02 deposition. A second group of wafers underwent native oxide growth externally from the plasma deposition chamber. Growths were performed thermally in air or in high purity 02 or N2O at atmospheric pressure, or wet chemically in warm H2O2. A third group of wafers received RF-sputtered
_2 Siθ2, which was deposited at 1.1 Wcm from a
Siθ2 target in Ar:θ2 sputtering atmospheres of 0, 5.2 and 21% 02 content.
Plasma oxidation at 13.56 MHz of InP wafers resting on a grounded table was performed at 250°C in pure N20 or in either 2% or 0.51% N20 in Ar at low power density ("0.05 Wcm ) and for times of the order of a few seconds. Thermal growths within the plasma deposition chamber were carried out at substrate table temperatures up to 395°C and pressures up to 79.993 Pa (600 Torr) of 20 for times of the order of 10 minutes. Atmospheric pressure thermal growths in air and N20 were at 320°C to 375°C in an evacuable tube furnace for times also of the order of 10 minutes. In these cases the thickness of the thermally grown native oxide was self- limiting as a function of temperature. The thickness of the native oxide, grown on a monitor wafer in a dummy grow.th without subsequent Si02 deposition, was measured ellipsometrically, assuming a refractive index (at 633 nm) of 1.75. Grown thicknesses in the range 1.8 to 3.6 nm were measured in this manner. Rutherford backscattering under channeling conditions has previously shown that under conditions of no intentional native oxide growth the InP/dielectric interface is of submonolayer thickness. The Si02 etch mask was photolithographically patterned to open up 2 to 3 μm wide windows aligned parallel to the [011] crystal direction. Several etchants will produce V-profile grooves in the perpendicular [01T] direction without need for mask undercut, but these grooves are not suitable for subsequent LPE growth. HC1:H3P04 etching was performed after photoresist removal, organic solvent cleaning, and a brief etch in 10:1:1 H2S04:H202:H20 by volume. After etching, sections were cleaved perpendicularly to the windows and the channel cross-sections examined in an SEM at x5K and x10K magnification with the Siθ2 mask in place.
When, however, etching was performed in 1 :1 HC1:H3P04 through the above Si02 mask (without interfacial native oxide), a profile similar to FIG. 2 was obtained but with a longer vertical wall component. In order to avoid such a vertical wall component, an increased amount of mask undercutting is necessary, corresponding to a larger groove width for a given mask opening. Hence, use of this etchant with reduced concentration of HC1 is not desirable.
Example 1 : Plasma Native Oxide on LEC InP
LEC ( 100)-oriented InP was etched through a 2.0 ym«wide Si02 mask opening for 20 sec in 3:1 HC1:H3P04 by volume.
The preferred profile of FIG. 5 was achieved in accordance with this invention by interposing a native oxide layer 23 about 2.0 nm + 0.2 nm thick between the mask 25 and the InP. The native oxide was grown by Ar:N20 plasma exposure for about 8 seconds at 250°C immediately prior to the plasma deposition of the Siθ2 mask 25. The extent of mask undercutting was u = 1.1.μm, in conjunction with an etch depth of D = 3.0 μm. The ratio of etch depth to undercut was 2.7. In fact, to eliminate the vertical wall component of FIG. 2, D/u 3.0. Such a profile has also been obtained with sputtered Si02 masks deposited in both 5.2% and- 21% O2 in Ar sputtering atmospheres. As the substrate was rotated into the plasma beneath the Siθ2 target, it was exposed for a few seconds to the oxygen-containing plasma, thus forming a native oxide just before the Si02 deposition began. However, if no oxygen is used in the sputtering atmosphere, no mask undercutting occurs. Thus, the native oxide layer was again confirmed as being responsible for controlling the amount of undercutting and producing the desired V-groove profile of FIG. 5.
In contrast, profiles of the type shown in FIG. 2 were produced when no native oxide layer was grown, and profiles of the type shown in FIG. 3 were produced whe . t e native oxide layer was too thick (e.g., 3.4 nm) .
The following explanation of this etching effect is theorized based on the different etching rates of the various crystallographic planes of InP: the (100) plane etches rapidly, the (111 )B plane etches slowly, and the (01T) plane essentially does not etch at all. In the absence of the native oxide layer, etching is halted at the (01T) planes extending down from the mask edges. The effect of the native oxide, which is soluble in the HC1:H3P04 etchant, is to provide a dynamically increasing mask opening. As a small amount of native oxide dissolves beneath the mask edge, a small amount of the fast-etching (100) plane becomes exposed, and downward etching begins in that region. Continuation of this process produces the observable mask undercutting. The rate of dissolution of the thin native oxide layer, controlled either by its solubility (which is determined by its growth conditions) or by its thickness (which determines the lateral rate of supply of fresh etchant, or removal of etch products, along the interface), determines the rate of exposure of fresh (100) surface". In turn, this rate relative to the etch rate of the (100) plane, and its rate relative to the (111 )B plane, determines the final etched profile. Example 2: Plasma Native Oxide on VPE InP A 3.0 μm deep V-groove of the type shown in
FIG. 5 was etched into VPE (100)-oriented InP through a 2.0 μm Si02 mask opening using a 25 sec etch in 3:1 HC1:H P04. An undercut of about 1.1 μm was produced by a plasma-grown native oxide layer about 2.0 nm thick. Plasma oxidation conditions were 5.0 sec exposure to 0.050 Wc "2 of RF power at 13.56 MHz in 59.995 Pa (450 mTorr) of Ar:0.51% N20 at 250°C. Example 3: Plasma Native Oxide on MOCVD InP
The same 5.0 sec plasma exposure described in Example 2 also produced an appropriate thickness of native oxide layer on S.I. MOCVD (100)-oriented InP and beneath a plasma-deposited Si02 etch mask. In conjunction with an etch time of 20 sec for a 2.0 μm mask opening and a 3.0 μ deep groove, compared to the 25 sec etch time needed for VPE InP, this native oxide layer produced a V-groove of the type shown in FIG. 5. Note, however, the preferred conditions for this MOCVD material are described in Example 4. Example 4: Thermal Native Oxide on VGF InP This example utilized Cd-diffused ( 100)-oriented
VGF InP. Prior to the Siθ2 deposition thermal oxidation was performed in the Siθ2 plasma deposition chamber at 380°C in about 0.5 atm. of dry N20 for 10 minutes, at which time the native oxide had reached its self-limiting thickness of about 2.0 nm. Etching in 3:1 HC1:H3P04 by volume for about 20-25 seconds produced the desired V- groove profile of FIG. 5 for a w = 2.0 μ and D = 3.0 μm. Example 5: Thermal Native Oxide on LEC InP
Using the conditions of Example 4, except that thermal oxidation took place at 395°C, vertical walls about 0.9 μm long, as shown in FIG. 2, were produced on LEC InP. But thermal oxidation in N20 at only 365°C at
1 atm. produced the desired profile of FIG. 5 when the native oxide growth was performed external to the plasma deposition chamber, entailing a few minutes of atmospheric exposure of the thermally oxidized surface prior to Siθ2 deposition. A similar effect has also been obtained by thermal oxidation in air at the further reduced temperature of 320°C, where the presence of H2O enhances the oxidation rate. From these observations, it is conjectured that hydration of the native oxide layer increases its ability to undercut the Si02 mask. Note, however, the desired V-groove etching of LEC InP can be achieved by forming the native oxide layer either by plasma oxidation (described above) or by thermal oxidation in pure
02 instead of N20. Example 6: Thermal Native Oxide on VGF InP
In the fabrication of InP/InGaAsP CSBH lasers of the type shown in FIG. 1 , the following process has been employed to etch V-grooves which are 3.0 μ deep and have the profile of FIG. 5. On a (100)-oriented InP layer 20 formed by Cd diffusion in VGF InP, a ~2.0 nm thick thermal native oxide layer 23 was grown in a static atmosphere of dry N20 at about 0.5 atm. at 360°C for 10 minutes. The chamber was actually a parallel plate, radial flow plasma reactor. The thickness of the native oxide layer was self-limiting. Temperatures in the range of 350-390°C are suitable, however, depending on other parameters (e.g., the purity of the N20). After pumping out the chamber, about 120 nm of Si02 was plasma-deposited at 360°C (not critical) in a flow of N20 plus 2% silane in Ar.
The Si0 layer was patterned using standard photolithography and plasma etching. Then the V-groove was etched in 3:1 HC1:H3P04 by volume at room temperature for about 25 sec.
It is to be understood that the above-described arrangements are merely illustrative of the many possible specific embodiments which can be devised to represent application of the principles of the invention. Numerous and varied other arrangements can be devised in accordance with these principles by those skilled in the art without departing from the spirit and scope of the invention. In particular, although specific examples are given above for etching V-grooves in various kinds of InP, it will be appreciated that the technique is also applicable to other Group III-V semiconductor compounds, especially those which are In-based (e.g., InGaAs, InGaAsP).

Claims

Claims
1. A method of fabricating a device, which includes etching a groove in a surface of a body of a Group III-V compound semiconductor material, CHARACTERIZED BY
(a) forming a thin native oxide layer on said surface, said oxide layer being soluble in the etchant used to form said groove,
. (b) forming on said oxide layer a dielectric layer which is essentially impervious to said etchant,
(c) patterning said dielectric layer to form openings therein, said
(d) exposing said body and said layers to said etchant to form said groove. 2. The method according to claim 1,
CHARACTERIZED IN THAT said surface is a (100) crystallographic plane, said openings are elongated and extend parallel to the [011] direction, and said groove has the shape of a V having side walls which are only (111 )B crystallographic planes.
3. . The method according to claim 2, CHARACTERIZED IN THAT said material includes In and P. 4. The method according to claim 3,
CHARACTERIZED IN THAT said etchant comprises a solution of HC1 and
H3P04,
The method according to claim 1 or 2 or 3 or 4,
CHARACTERIZED IN THAT in step (d), said etchant undercuts said dielectric layer by a distance u.' sa d groove is etched to a depth D, and the thickness of said native oxide layer is such that D/u < 3.0.
6. The method according to claim 1 or 2 or 3 or 4,
CHARACTERIZED IN THAT in step (a), said native oxide layer is formed by plasma oxidation at an elevated temperature (1 ) in an atmosphere of N20 and Ar or
(2) in an atmosphere of O2 and Ar.
7. The method according to claim 1 or 2 or 3 or 4,
CHARACTERIZED IN THAT in step (a), said native oxi'de layer is formed by thermal oxidation (1) in an atmosphere of 2O at an elevated temperature or (2) in an atmosphere of o2.
8. The method according to claim 7, CHARACTERIZED IN THAT in step (a), said oxide layer is grown in an atmosphere of dry N2O at a pressure of about 0.5 atm., a temperature in the range of about 350-390°C, and for a time of the order to 10 minutes. 9. The method according to claim 8,
CHARACTERIZED IN THAT in step (b), said Siθ2 mask is deposited in the same chamber as said native oxide layer to a thickness greater than 100 nm using N2 plus a dilute mixture of silane in Ar at a temperature of a new hundred degrees C.
10. The method according to claim 1 or 2 or 3 or 4,
CHARACTERIZED IN THAT - in step (a), said native oxide layer is grown to a thickness of 2.0 nm + 0.2 nm.
11. The method according to claim 1 or 2 or 3 or 4,
CHARACTERIZED IN THAT in step (b), said dielectric layer is formed by plasma deposition of Siθ2«
12. The method according to claim 1, CHARACTERIZED BY
(a) thermally growing a native oxide layer about 2.0 nm + 0.2 nm thick on a ( 100)-oriented surface of an InP body,
(b) plasma depositing a Siθ2 mask on said native oxide layer,
(c) patterning said mask to form elongated openings which extend parallel to the (011) direction,
(d) exposing said body and said layers to an etchant comprising a solution of about 3:1 ΗC1 and H3P04 at essentially room temperature for a time which is effective to undercut said mask by a distance u which is more than about one third the depth of said groove.
PCT/US1985/000918 1984-06-15 1985-05-16 The fabrication of grooved semiconductor devices WO1986001367A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP86500738A JPS61502509A (en) 1984-06-15 1985-05-16 Fabrication of grooved semiconductor devices
DE8686900681T DE3573191D1 (en) 1984-06-15 1985-05-16 The fabrication of grooved semiconductor devices

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US621,080 1984-06-15
US06/621,080 US4595454A (en) 1984-06-15 1984-06-15 Fabrication of grooved semiconductor devices

Publications (2)

Publication Number Publication Date
WO1986001367A2 true WO1986001367A2 (en) 1986-03-13
WO1986001367A3 WO1986001367A3 (en) 1986-07-17

Family

ID=24488631

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1985/000918 WO1986001367A2 (en) 1984-06-15 1985-05-16 The fabrication of grooved semiconductor devices

Country Status (6)

Country Link
US (1) US4595454A (en)
EP (1) EP0201599B1 (en)
JP (1) JPS61502509A (en)
CA (1) CA1225465A (en)
DE (1) DE3573191D1 (en)
WO (1) WO1986001367A2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2271215B (en) * 1992-09-16 1996-09-25 Mitsubishi Electric Corp Semiconductor laser diode and production method thereof,and semiconductor laser diode array

Families Citing this family (46)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4999315A (en) * 1984-06-15 1991-03-12 At&T Bell Laboratories Method of controlling dopant incorporation in high resistivity In-based compound Group III-V epitaxial layers
US4888624A (en) * 1984-06-15 1989-12-19 American Telephone And Telegraph Company, At&T Bell Laboratories Semiconductor devices employing high resistivity in-based compound group III-IV epitaxial layer for current confinement
JPS61171136A (en) * 1985-01-25 1986-08-01 Toshiba Corp Mesa etching method for semiconductor crystal
US4694311A (en) * 1985-05-22 1987-09-15 Trw Inc. Planar light-emitting diode
JPH0716077B2 (en) * 1985-10-11 1995-02-22 三菱電機株式会社 Method of manufacturing semiconductor laser device
US4839307A (en) * 1986-05-14 1989-06-13 Omron Tateisi Electronics Co. Method of manufacturing a stripe-shaped heterojunction laser with unique current confinement
JPS62283686A (en) * 1986-05-31 1987-12-09 Mitsubishi Electric Corp Manufacture of semiconductor laser
GB8622767D0 (en) * 1986-09-22 1986-10-29 British Telecomm Semiconductor structures
US4701995A (en) * 1986-10-29 1987-10-27 American Telephone And Telegraph Company, At&T Bell Laboratories Method of making a nonplanar buried-heterostructure distributed-feedback laser
JPH01220492A (en) * 1988-02-26 1989-09-04 Mitsubishi Electric Corp Semiconductor laser device and manufacture thereof
US4885056A (en) * 1988-09-02 1989-12-05 Motorola Inc. Method of reducing defects on semiconductor wafers
US4980314A (en) * 1989-06-06 1990-12-25 At&T Bell Laboratories Vapor processing of a substrate
US5100836A (en) * 1989-08-16 1992-03-31 At&T Bell Laboratories Method of making a semiconductor device
US5036023A (en) * 1989-08-16 1991-07-30 At&T Bell Laboratories Rapid thermal processing method of making a semiconductor device
US4938841A (en) * 1989-10-31 1990-07-03 Bell Communications Research, Inc. Two-level lithographic mask for producing tapered depth
US5092957A (en) * 1989-11-24 1992-03-03 The United States Of America As Represented By The United States Department Of Energy Carrier-lifetime-controlled selective etching process for semiconductors using photochemical etching
US5484507A (en) * 1993-12-01 1996-01-16 Ford Motor Company Self compensating process for aligning an aperture with crystal planes in a substrate
US5420953A (en) * 1994-02-17 1995-05-30 The Whitaker Corporation Optoelectronic integration of holograms using (110) oriented silicon on (100) oriented silicon waferboard
US5468338A (en) * 1994-07-22 1995-11-21 At&T Ipm Corp. Methods for selectively wet etching substrates
DE4432410B4 (en) * 1994-08-31 2007-06-21 ADC Telecommunications, Inc., Eden Prairie Optoelectronic multi-wavelength device
US5601687A (en) * 1995-09-11 1997-02-11 The United States Of America As Represented By The Secretary Of The Air Force Mask design
FR2744225B1 (en) * 1996-01-25 1998-05-07 Menigaux Louis PROCESS FOR THE PRODUCTION OF A 45 DEGREE INCLINED PLAN ON A 3-5 CRYSTAL COMPONENT AND OPTICAL COMPONENT
US6007951A (en) * 1997-12-19 1999-12-28 The Whitaker Corporation Method for precise crystallographic semiconductor wafer alignment orientation
US5960024A (en) 1998-03-30 1999-09-28 Bandwidth Unlimited, Inc. Vertical optical cavities produced with selective area epitaxy
US6487231B1 (en) 1998-04-14 2002-11-26 Bandwidth 9, Inc. Vertical cavity apparatus with tunnel junction
US6487230B1 (en) 1998-04-14 2002-11-26 Bandwidth 9, Inc Vertical cavity apparatus with tunnel junction
US6535541B1 (en) 1998-04-14 2003-03-18 Bandwidth 9, Inc Vertical cavity apparatus with tunnel junction
US5991326A (en) 1998-04-14 1999-11-23 Bandwidth9, Inc. Lattice-relaxed verticle optical cavities
US6493373B1 (en) 1998-04-14 2002-12-10 Bandwidth 9, Inc. Vertical cavity apparatus with tunnel junction
US6493371B1 (en) 1998-04-14 2002-12-10 Bandwidth9, Inc. Vertical cavity apparatus with tunnel junction
US6760357B1 (en) 1998-04-14 2004-07-06 Bandwidth9 Vertical cavity apparatus with tunnel junction
US6493372B1 (en) 1998-04-14 2002-12-10 Bandwidth 9, Inc. Vertical cavity apparatus with tunnel junction
US6380027B2 (en) 1999-01-04 2002-04-30 International Business Machines Corporation Dual tox trench dram structures and process using V-groove
US6226425B1 (en) 1999-02-24 2001-05-01 Bandwidth9 Flexible optical multiplexer
US6275513B1 (en) 1999-06-04 2001-08-14 Bandwidth 9 Hermetically sealed semiconductor laser device
US6233263B1 (en) 1999-06-04 2001-05-15 Bandwidth9 Monitoring and control assembly for wavelength stabilized optical system
US6551936B2 (en) * 2000-12-29 2003-04-22 Bookham Technology Plc Method of etching patterns into epitaxial material
DE10127580B4 (en) * 2001-05-29 2006-04-27 Infineon Technologies Ag In situ mask technology for the production of III-V semiconductor devices
US6599843B2 (en) 2001-05-29 2003-07-29 Infineon Technologies Ag In-situ mask technique for producing III-V semiconductor components
US7968273B2 (en) 2004-06-08 2011-06-28 Nanosys, Inc. Methods and devices for forming nanostructure monolayers and devices including such monolayers
US7776758B2 (en) 2004-06-08 2010-08-17 Nanosys, Inc. Methods and devices for forming nanostructure monolayers and devices including such monolayers
US20090136785A1 (en) * 2007-01-03 2009-05-28 Nanosys, Inc. Methods for nanopatterning and production of magnetic nanostructures
WO2008085813A2 (en) * 2007-01-03 2008-07-17 Nanosys, Inc, Et Al. Methods for nanopatterning and production of nanostructures
KR20110074724A (en) * 2007-12-14 2011-07-01 나노시스, 인크. Methods for formation of substrate elements
US8540889B1 (en) 2008-11-19 2013-09-24 Nanosys, Inc. Methods of generating liquidphobic surfaces
FR2977710A1 (en) * 2011-07-06 2013-01-11 Soitec Silicon On Insulator PROCESS FOR DETERMINING THE CRYSTALLINE QUALITY OF A III-V SEMICONDUCTOR LAYER

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2200533A1 (en) * 1972-09-25 1974-04-19 Western Electric Co
US3980508A (en) * 1973-10-02 1976-09-14 Mitsubishi Denki Kabushiki Kaisha Process of producing semiconductor device

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58147122A (en) * 1982-02-26 1983-09-01 Fujitsu Ltd Dry etching method for compound semiconductor
JPS6041232A (en) * 1983-08-17 1985-03-04 Fujitsu Ltd Manufacture of semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2200533A1 (en) * 1972-09-25 1974-04-19 Western Electric Co
US3980508A (en) * 1973-10-02 1976-09-14 Mitsubishi Denki Kabushiki Kaisha Process of producing semiconductor device

Non-Patent Citations (5)

* Cited by examiner, † Cited by third party
Title
Applied Physics Letters, Volume 42, No. 7, April 1983, New York, (US) J.F. WAGER et al.: "Estimation of the Band Gap of InPo4", pages 589-591, see page 589, column 1, paragraph 1 - page 590, column 1, paragraph 1 *
Fujitsu-Scientific and Technical Journal, Volume 18, No. 3, September 1982, Kawasaky (JP) Y. NISHITANI et al.: "InGaAsP LPE Growth on InP and its Applications to DH Lasers", pages 419-436, see page 432, paragraph 2 - page 433, paragraph 1; figure 17 *
Journal of the Electrochemical Society, Volume 113, No. 9, September 1966, Princeton, (US) D.W. SHAW: "Enhanced GaAs Etch Rates near the Edges of a Protective Mask", pages 958-966 *
Journal of the Electrochemical Society, Volume 130, No. 9, September 1983, Manchester, (US) L.A. COLDREN et al.: "On the Formation of Planar-Etched Facets in GaInAsP/InP double Heterostructures", pages 1918-1926, see page 1919, column 1, paragraph 1 - page 1922, column 1, paragraph 2 *
Thin Solid Films, Volume 95, No. 4, September 1982, Lausanne, (CH) J.F. WAGER et al.: "Oxidation of InP in a Plasma-Enhanced Chemicsl Vapor Deposition Reactor", pages 343-350, see page 343, Abstract; page 344, paragraph 2 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2271215B (en) * 1992-09-16 1996-09-25 Mitsubishi Electric Corp Semiconductor laser diode and production method thereof,and semiconductor laser diode array
US5608749A (en) * 1992-09-16 1997-03-04 Mitsubishi Denki Kabushiki Kaisha Semiconductor laser diode and semiconductor laser diode array including plated heat sink (PHS) electrode

Also Published As

Publication number Publication date
CA1225465A (en) 1987-08-11
US4595454A (en) 1986-06-17
DE3573191D1 (en) 1989-10-26
JPS61502509A (en) 1986-10-30
EP0201599A1 (en) 1986-11-20
EP0201599B1 (en) 1989-09-20
WO1986001367A3 (en) 1986-07-17

Similar Documents

Publication Publication Date Title
EP0201599B1 (en) The fabrication of grooved semiconductor devices
US4566171A (en) Elimination of mask undercutting in the fabrication of InP/InGaAsP BH devices
US4888624A (en) Semiconductor devices employing high resistivity in-based compound group III-IV epitaxial layer for current confinement
US5390205A (en) Semiconductor laser
EP0433051B1 (en) A semiconductor laser device and a method of producing the same
GB2271466A (en) Etching semicondudtor wafers
US5093278A (en) Method of manufacturing a semiconductor laser
US5360754A (en) Method for the making heteroepitaxial thin layers and electronic devices
US4999315A (en) Method of controlling dopant incorporation in high resistivity In-based compound Group III-V epitaxial layers
US5470785A (en) Method of manufacturing buried heterostructure semiconductor laser
US4661961A (en) Buried heterostructure devices with unique contact-facilitating layers
US4764246A (en) Buried undercut mesa-like waveguide and method of making same
EP1719003A1 (en) Buried heterostructure device fabricated by single step mocvd
US4725112A (en) Buried undercut mesa-like waveguide
US5748659A (en) Semiconductor laser device
US5335241A (en) Buried stripe type semiconductor laser device
Okuda et al. GaInAsP/InP surface emitting injection laser with buried heterostructures
Itoh et al. Embedded-stripe GaAs-GaAlAs double-heterostructure lasers with polycrystalline GaAsP layers-I: Lasers with cleaved mirrors
CA1282874C (en) Semiconductor devices employing high resistivity in p-based epitaxial layer forcurrent confinement
EP1233492B1 (en) Compound semiconductor laser manufacturing method
EP0306225B1 (en) Method of producing a semiconductor laser
Feldman et al. Liquid phase epitaxial growth of InGaAsP and InP on mesa-patterned InP substrates
GB2299709A (en) Method for producing a semiconductor device
Abe et al. FABRICATION OF SUBMICRON GRATINGS FOR 1.5 μm InGaAsP/InP DISTRIBUTED FEEDBACK LASERS BY REACTIVE ION ETCHING USING C2H6/H2
JPH0277184A (en) Manufacture of semiconductor laser

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 1986900681

Country of ref document: EP

AK Designated states

Kind code of ref document: A2

Designated state(s): JP

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): AT BE CH DE FR GB IT LU NL SE

AK Designated states

Kind code of ref document: A3

Designated state(s): JP

AL Designated countries for regional patents

Kind code of ref document: A3

Designated state(s): AT BE CH DE FR GB IT LU NL SE

WWP Wipo information: published in national office

Ref document number: 1986900681

Country of ref document: EP

WWG Wipo information: grant in national office

Ref document number: 1986900681

Country of ref document: EP