EP0200795B1 - Circuit de génération d'un signal vidéo représentant une valeur de mesure - Google Patents

Circuit de génération d'un signal vidéo représentant une valeur de mesure Download PDF

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Publication number
EP0200795B1
EP0200795B1 EP85105223A EP85105223A EP0200795B1 EP 0200795 B1 EP0200795 B1 EP 0200795B1 EP 85105223 A EP85105223 A EP 85105223A EP 85105223 A EP85105223 A EP 85105223A EP 0200795 B1 EP0200795 B1 EP 0200795B1
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EP
European Patent Office
Prior art keywords
signal
circuit
video
vertical
counter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
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EP85105223A
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German (de)
English (en)
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EP0200795A1 (fr
Inventor
Werner Liebel
Peter Antesberger
Peter Einberger
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GLONNER ELECTRONIC GmbH
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GLONNER ELECTRONIC GmbH
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Priority to EP85105223A priority Critical patent/EP0200795B1/fr
Priority to DE8585105223T priority patent/DE3565020D1/de
Priority to US06/855,179 priority patent/US4700227A/en
Priority to JP61093522A priority patent/JPS61253472A/ja
Priority to CA000507905A priority patent/CA1248649A/fr
Publication of EP0200795A1 publication Critical patent/EP0200795A1/fr
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Publication of EP0200795B1 publication Critical patent/EP0200795B1/fr
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G1/00—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data
    • G09G1/06—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows
    • G09G1/14—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows the beam tracing a pattern independent of the information to be displayed, this latter determining the parts of the pattern rendered respectively visible and invisible
    • G09G1/16—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows the beam tracing a pattern independent of the information to be displayed, this latter determining the parts of the pattern rendered respectively visible and invisible the pattern of rectangular co-ordinates extending over the whole area of the screen, i.e. television type raster
    • G09G1/162—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows the beam tracing a pattern independent of the information to be displayed, this latter determining the parts of the pattern rendered respectively visible and invisible the pattern of rectangular co-ordinates extending over the whole area of the screen, i.e. television type raster for displaying digital inputs as analog magnitudes, e.g. curves, bar graphs, coordinate axes, singly or in combination with alpha-numeric characters

Definitions

  • the present invention relates to a circuit for generating a video signal representing a measurement signal according to the preamble of claim 1.
  • US-A-3 686 862 already shows a circuit for generating a video signal representing a measurement signal for driving a screen display device with a video memory circuit with random access, in which at an address which corresponds to the x-deflection of the write beam of the cathode ray picture tube, individual , discrete y values are stored.
  • the known circuit also has a horizontal address control circuit which reads out this video memory in synchronization with the horizontal deflection of the cathode ray.
  • the known video signal generating circuit includes a circuit for generating a digital vertical signal representing the current vertical position of the video signal to be generated.
  • a digital interpolation circuit is connected to the output of the video memory circuit and generates an intermediate value from the y-deflection values stored under two adjacent addresses corresponding to two adjacent x-deflections of the cathode beam by interpolation, which is assigned to an x-intermediate value.
  • This y-digital data obtained by interpolation is fed together with the y-data read out from the video memory circuit to the digital comparator circuit, which compares this data in accordance with the output digital signals of the vertical signal circuit. If the digital signal generated by the vertical signal circuit, which usually has the form of a data word, matches the y data value read out from the video memory circuit or the y intermediate data value obtained from the interpolation circuit, a video signal is switched on and off.
  • the video signal generated by means of such a circuit shows a step-shaped measurement signal, the step size of which depends on the number of interpolated intermediate values that are calculated by the interpolation circuit.
  • a large number of intermediate values generated by the interpolation circuit would be necessary for a strong increase in the resolution.
  • the achievable resolution is set relatively narrow limits, so that in practical applications only the generation of one intermediate point is possible .
  • US-A-4 068 310 also shows a circuit for generating a video signal representing a measurement signal, which operates with a video memory circuit with random access.
  • This known circuit also has a horizontal address control circuit, a vertical signal circuit for generating a vertical signal data representing the current vertical position of the video signal to be generated and a digital comparator with which the video signal is switched on and off.
  • a further comparator circuit is used to determine whether the distance between two successive y data values read from the video memory circuit is more than one image line apart. If this is the case, a data value lying between the two y values is generated in that with a delay which corresponds to half the sampling time between two successive x values of the image signal, the control of the Video signal is made.
  • this known circuit for generating a video signal representing a measurement signal only a staircase curve can be generated which roughly approximates the measurement signal to be displayed.
  • the present invention is based on the object of developing a circuit of the type mentioned in the preamble of claim 1 in such a way that an improved display of a measurement signal is possible with it.
  • the measurement signal present at the output of the video D / A converter is smoothed by the generation of each video image line, which results from the assignment of individual measurement signal points to the image grid before it is digitized to have.
  • the measurement signal is determined in the grid of the screen subdivision, i.e. the measurement signal e.g. assigned either to a certain left or a certain right screen point that comes closest to the optimal measurement signal display, but in contrast to such an assignment now generates a comparison signal at any point between two pixels within a line.
  • the improvement in the video measurement signal display achieved by the circuit according to the invention is particularly clear in the following example:
  • a measurement signal is to be displayed which contains an edge which is approximately vertical, that is to say, for example, has an incline of 10 screen lines in the vertical direction with a horizontal extension of only two screen points.
  • Such a steep flank could only be represented by means of the known circuit in such a way that the signal appears as a staircase consisting of two vertical lines, each with a length of five lines and a horizontal offset from one screen point.
  • the circuit according to the invention makes a screen display appear, in which, according to this example, the successive measurement signal points of successive screen lines only have an offset of one tenth of a screen point. Such a representation is perceived as a stepless, slightly inclined line.
  • the circuit according to the invention thus enables a clear signal for continuous, continuous signals improved quality of the screen display of the measurement signal.
  • a further increase in the quality of the screen display of measurement signals is achieved in that the comparison signal generated by the comparison circuit assumes a maximum value if the vertical signal matches the output signal of the video D / A converter, and that the comparison signal increases with the difference between the vertical signal and the output signal decreases steadily, and if the difference exceeds a limit value, it assumes the value which represents the absence of the point of the measurement signal in the currently generated line of the video signal.
  • the latter value is the white level for a black representation of a measurement signal on a white background, and the black level of the video signal for a white representation of the measurement signal against a black background.
  • the cut-off frequency of the low-pass filter circuit is preferably between one third and one tenth of the line frequency multiplied by the number of pixels per line, since in this case the shape of the measurement signal shown is improved practically without restriction of the measurement signal frequency range that can be represented. In other words, there is no need to present measurement signals whose period duration is shorter than, for example, three pixels, since such signals can no longer be represented as vibrations due to the grid being too coarse.
  • the cut-off frequency of the low-pass filter circuit is preferably set in the range between 1 and 10 MHz.
  • Easier to record short-term events e.g. Short pulses are achieved in that a comparison signal broadening circuit following an increase in the comparison signal with its output signal and a drop in the comparison signal only corresponding to a predetermined time constant with its output signal is connected to the output side of the comparison circuit.
  • a comparison signal broadening circuit following an increase in the comparison signal with its output signal and a drop in the comparison signal only corresponding to a predetermined time constant with its output signal is connected to the output side of the comparison circuit.
  • Such a detection of short-term events can be helpful, in particular in the medical field for displaying signals derived from a patient by means of transducers.
  • a processing of the measurement signal that is independent of the processing of the video signal is achieved in that a buffer circuit for measurement signal data formed from the measurement signal is connected to a data input of the video memory circuit, and in that the memory content of the buffer circuit is generated in the video memory after the generation of a video signal representing a field is storable.
  • This structure enables measurement signal data management, which can be largely decoupled from the video clock.
  • a synchronization of the periodic readout of the video signal memory with the video clock is achieved in that the horizontal address control circuit has a pixel clock generator which, in synchronism with the horizontal synchronization signal, generates a pulse signal with a line frequency multiplied by the number of pixels per line, the horizontal address control circuit generating the current address of a memory cell to be read out of the video memory circuit generating first counter, which is connected to this pixel clock generator, and the count value of which can be varied upon generation of each line starting from a start address as a function of the pulse signal of the pixel clock generator.
  • the start address of the first counter remains constant for at least one field.
  • the measurement signal is preferably reproduced in a representation moving quasi-continuously to the left edge of the screen.
  • the buffer circuit has a microcomputer which changes the current start address of the first counter by a predetermined start address difference compared to the start address of the first counter when generating the previous field before generating a video signal representing a field.
  • the second counter of the horizontal address control circuit which is also connected to the pixel clock generator and which, after the counter beginning with a second starting address, has a number of pulses of the pixel clock generator corresponding to the number of pixels of a picture line of a desired length, effects software adjustment of the respectively displayed screen line length generated.
  • This overflow signal preferably causes a logic circuit to be reset in synchronization with the pulses from the pixel clock generator, which logic circuit is set when the horizontal synchronization signal occurs, again preferably in synchronization with the pulses from the pixel clock generator.
  • the logic circuit controls the loading of the first and second counters with the first and second start addresses of the counters during their reset state.
  • a vertical signal of particularly high accuracy in relation to the number of lines is generated by the scarf device for generating the vertical signal, if it has a third counter, which counts the pulses of the horizontal synchronization signal and is reset by the vertical synchronization signal, the third counter driving a programmable read-only memory, the output of which is connected to the vertical D / A converter.
  • This configuration of the circuit for generating the vertical signal not only has the advantage of a high temporal and amplitude-related accuracy of the vertical signal, but also enables the time characteristic of the vertical signal to be easily adapted by suitable programming of the read-only memory.
  • the read-only memory is preferably programmed such that the circuit for generating the vertical signal outputs a sawtooth-shaped vertical signal with increasing count values of the third counter, which has a number of sawtooth-shaped ramps corresponding to the number of measurement signals that can be simultaneously displayed.
  • a specific line area of the screen is preferably assigned to each measurement signal to be displayed, to which a count value area of the third counter corresponds.
  • the output signal of the programmable read-only memory and thus the output signal of the downstream vertical D / A converter run through a quasi-continuous ramp. With such a vertical signal control, a plurality of measurement signals can be displayed.
  • a measuring transducer 1 generates a measuring signal which is fed to an analog-digital converter 2 (A / D converter 2).
  • the digital representation of the measurement signal is present on a data input bus of a microcomputer 3.
  • the microcomputer 3 periodically samples the digitized measurement signal and stores the measurement signal values in a read-write memory (RAM) 4.
  • a data output bus of the microcomputer 3 is connected to a data input of a video RAM 5.
  • Both the microcomputer 3 and the video RAM 5 are connected to a horizontal control or horizontal address control circuit 6, which controls the timing of the operation of the microcomputer 3 and the video RAM 5.
  • the data output signal of the video RAM 5 is fed to a digital-to-analog converter (D / A converter) 8, which has a hold circuit.
  • D / A converter digital-to-analog converter
  • the D / A converter 8 is connected to the input of a low-pass filter circuit 9, the output signal of which is fed to a first input of a differential amplifier 11.
  • a vertical controller 7 is connected to the video RAM 5 in order to control a desired memory area which is assigned to a measurement signal channel of a plurality of measurement signal channels.
  • the vertical controller 7, which is also referred to below as a circuit for generating a vertical signal is connected to a digital-to-analog converter (D / A converter) 10, which in turn is connected on the output side to a second input of the differential amplifier 11.
  • the differential amplifier 11 is connected to an intensity control circuit 12.
  • the intensity control circuit is a circuit with the transmission characteristic sketched in Fig. 1, i.e. generates a maximum output signal at a zero value of the input signal, the output signal steadily decreasing with increasing absolute value of the input signal, to the value on the output side above a positive or negative limit value for the input signal To assume zero.
  • the output signal of the intensity control circuit is for controlling a subsequent video signal modulator 13, which, for a black level and a white level schwar U U i WE is supplied ss.
  • the resulting output signal of the video signal modulator 13 is combined with a horizontal synchronization signal from a horizontal synchronization signal circuit 14 and with a vertical synchronization signal from a vertical synchronization signal circuit 15.
  • the signal resulting at the summation point is a complete video signal, which is used to control a subsequent video playback device 16.
  • FIG. 2 Reference numerals in FIG. 2, which correspond to those according to FIG. 1, denote the same or similar parts.
  • the reference symbol 17 and the reference symbol 17 ' denote two parallel data output buses of the video RAM 5 (not shown in FIG. 2), which in the preferred exemplary embodiment shown in FIG. 2 is designed as a dual-port video RAM 5.
  • Each data output bus of the dual-port video RAM 5 is connected to completely identical circuits described in more detail below. It can be seen in FIG. 2 that the upper right circuit part and the middle right circuit part are constructed completely identically. A one-off description of the upper right-hand circuit part is therefore sufficient, which also applies analogously to the middle right-hand circuit part, the elements of which are identified by the same, but apostrophic reference numerals.
  • the data output bus 17 is connected to a hold circuit 18, which has a clock input 19, which is connected to a pixel clock generator 100, which will be described in more detail below with reference to FIG. 3, and which generates the pixel clock signal PLC.
  • a digital-to-analog converter 8 is connected to the holding circuit 18 and generates an impressed current at its output 6 which corresponds to the data word present on the input side.
  • the output 6 of the D / A converter 8 is connected to the filter circuit 9, designated as a whole by the reference number 9, which dampens the harmonics of the output current of the D / A converter 8.
  • the D / A converter 8 has a predetermined internal resistance, which forms the termination of the filter circuit at its output 6.
  • a third counter 50 has an input 10 to which the horizontal synchronization signal is present and a reset input 11 to which the vertical synchronization signal is present.
  • the third counter 50 is used to determine the number of horizontal synchronization pulses that have occurred since the last vertical synchronization pulse.
  • the counter content of the third counter 50 corresponds to the number of the line of the screen of the video playback device 16 described by a currently generated video signal.
  • the third counter 50 is connected via an address bus 20 to a read-only memory circuit 51, which is referred to below as the vertical PROM 51 becomes.
  • the vertical PROM is programmed in such a way that with continuously increasing input addresses it generates a data output word that corresponds to a sawtooth curve with several quasi-continuous ramps.
  • a ramp of the output signal of the vertical PROM 51 is used to generate a comparison signal for one of a plurality of measurement signals, which are stored in the corresponding channel (here the upper channel) of the dual-port video RAM 5.
  • the vertical control 7 is connected to the video RAM 5.
  • the connection between the vertical control 7 and the video RAM 5 serves to address the measurement signal channel to be read in each case.
  • the vertical addressing of the video RAM is carried out in the exemplary embodiment shown in FIG. 2 by the channel addressing PROM 21, which is likewise connected to the address bus 20 on the input side.
  • the output side of the vertical PROM 51 is connected to the vertical D / A converter 10, which has the same structure as the video D / A converter 8.
  • the vertical D / A converter 10 also has an analog output with an impressed current source and a predetermined internal resistance, which closes the low-pass filter circuit 9 to the analog current output side of the vertical D / A converter 10.
  • the video D / A converter 8 works with its impressed output current via the low-pass filter circuit 9 against the internal resistance of the vertical D / A converter 10, which in turn with its impressed output current via the low-pass filter circuit 9 works against the internal resistance of the video D / A A-Wandiers 8 works.
  • a differential voltage signal is thus present at the node designated by reference numeral 22, which results from the current output signal of the low-pass filter circuit 9 against the internal resistance of the converter 10 and from the output current of the converter 10 against the internal resistance of the converter 8.
  • the differential signal is amplified in terms of voltage via a differential amplifier circuit 11 and applied to the input of an amplifier 23.
  • the amplifier 23 Depending on the polarity of the input signal, the amplifier 23 generates at one of its two outputs 6, 8 an output signal for controlling downstream amplification transistors 24, 25.
  • the transistors 24, 25 are connected to a positive supply voltage on the collector side and are connected to an electrode of a capacitor 26 on the emitter side. Each capacitor electrode is connected to a negative potential via a discharge resistor 27, 28.
  • the charge of the more negative electrode of the capacitor 26 determines the potential of the output node 31 via diodes 29, 30 connected to the electrodes of the capacitor 26 and an output node 31.
  • the capacitor-resistance circuit 26 to 30 forms, together with the transistors 24, 25, a circuit which is able to quickly follow a rapid rise in the input signal of the amplifier 23 on the input side, the absolute value of the output signal only having an RC time constant after the input signal has ceased to exist decreases, which is determined by the value of the capacitor 26 and the resistor 27, 28.
  • This circuit thus causes a desirable broadening of short input signal pulses in order to make them visible on a screen image.
  • the degree of amplification and the transmission property of the entire intensity control circuit 12 can be influenced by suitable switching of the field effect transistors 32 to 34.
  • the transmission characteristic of the overall circuit between node 22 and output node 31 is such that an input signal of zero level at node 22 leads to a maximum absolute value of the output signal, an increasing absolute value of the output voltage at node 22 reducing the absolute value of the output signal. If the differential voltage at point 22 exceeds a predetermined limit value, the absolute value of the output signal is zero.
  • This transmission property is indicated schematically in FIG. 1 at reference number 12.
  • the potential at the output node 31 controls a field effect transistor 13, which is connected to the output node and serves as a video signal modulator 13.
  • the upper field effect transistor 13 operating as a video signal modulator or the corresponding lower field effect transistor 13' is driven.
  • These field effect transistors 13, 13 ' are each at a common node and at a black potential.
  • the common node 35 is connected to a resistor 37 Output 36 of a white potential generating circuit 38 in connection.
  • the signal at the output 39 with black level corresponds to a point of the measurement signal appearing black within the currently written line of the video signal.
  • the circuits generally provided with the reference numerals 41 to 43 serve for the optional additional generation of a line, a grid or a time clock. These additional circuits 41 to 43 are controlled by an additional PROM 44, which is also connected to the address bus 20.
  • FIG. 2 shows the entire circuit following the video RAM 5 for generating a video signal representing a measurement signal, but the address control circuit of the video RAM 5, which is also not shown, is not shown.
  • reference numeral 100 generally designates a pixel clock generator.
  • the pixel clock generator 100 has a horizontal synchronization input 110, to which the horizontal synchronization signal is fed.
  • a flip-flop 112 is connected to this input via a negating gate circuit 111, to the output of which a further negating gate 113 and a time constant circuit 114 to 117 are connected.
  • the time constant circuit has two capacitors 114, 115 and two resistors 116, 117.
  • the pixel clock signal is taken from the output of this network negated again by the gate 118 at the node 119.
  • This pixel clock signal is fed to the first counter, which consists of counter modules 101 to 103, a second counter, which consists of counter modules 104 to 106, and a D flip-flop 107.
  • the first counter 101 to 103 delivers the address signals for the video RAM 5 at its outputs MA 0 to MA 9.
  • the second counter 104 to 106 serves to generate an overflow signal which is fed to the D input of the flip-flop 107 as soon as the number of pixel clock pulses determined by him corresponds to a desired video line length.
  • Both counters 101 to 103; 104 to 106 are connected to start address memory circuits 120, 121, which are also formed by corresponding parts of the memory element 120 ', 121'.
  • the start address memory shadings 120, 121 are connected via a start address bus 122 to the microcomputer 3 (see FIG. 1), which loads them with start addresses for the first and for the second counter, with appropriate control of their inputs CSV 0, CSV 1.
  • the start address memory circuit 120 is loaded with a value which has such a difference compared to the overflow value of the second counter 104 to 106 that the difference determines the number of pixel clock pulses which form a line of a desired length.
  • the start address for the first counter 101 to 103 stored in the first start address memory 121 represents the start address for reading out the video RAM 5 for a specific field. By incrementing this start address, the start address at which the readout of the video RAM 5 begins is also incremented so that the measurement signal is shifted on the screen with each field. The incrementing of the first start address thus generates a desirably running measurement signal on the screen.
  • the first flip-flop When the second counter, which indicates that the line length has been reached, and when a pixel clock supplied to the clock input of the first flip-flop 107 occurs, the first flip-flop is set. Its negated output is connected to the reset input of the second flip-flop 108, which is hereby set to “low”. This state of the second flip-flop 108 continues until a line synchronization signal or horizontal synchronization signal fed to it at its clock input is fed from the input 110.
  • the signal appearing at the output 123 of the flip-flop 108 can be referred to as a horizontal window which is opened at the beginning of each line and is closed when the second counter overflows, that is to say at the end of the line.
  • charging inputs 9, which are connected to the second flip-flop 108 at its output 123 are activated.
  • the circuit according to the invention not only can the image display quality for a measurement signal in a video system with the basic structure shown in FIG. 1 be improved, but it is also possible to use the circuit according to the invention in a system in which a measurement signal of some kind is stored on a storage medium , such as a magnetic tape memory, for example, is temporarily stored in pulse-code-modulated form and, if necessary, is transferred to the video memory circuit, which in turn is followed by a circuit that essentially follows the structure of the circuit of the exemplary embodiment according to FIG. 1 has.
  • a storage medium such as a magnetic tape memory
  • the measurement signal can be recorded in a pulse-code-modulated form on a video tape using a video recorder and at the reproduction can be converted into a binary digital signal, which is applied to the data input bus of the microcomputer 3.
  • the low-pass circuit which follows the video D / A converter does not have to have the configuration shown in FIG. 1, but can already be formed in that the output of the D / A converter itself has a frequency-limiting effect.
  • the inventive low pass structure can be by any means reali - be Siert, which leads to a cut-off frequency is in the order of magnitude of the pixel clock frequency to one-tenth of the pixel clock frequency.
  • the comparison circuit 11, 12 can also be designed as a digitally operating window comparator.
  • the system according to the invention is preferably used in the field of medical electronics. However, the system can be used wherever signals with a substantially continuous course are either to be displayed on a video display device or to be stored in the form of a video signal.

Claims (13)

1. Circuit (1 à 16) pour la génération d'un signal vidéo représentant une valeur de mesure, comprenant un circuit de mémoire vidéo numérique adressa- ble (5); un circuit de commande d'adresses horizontales (6) pour l'activation d'un contenu de mémoire du circuit de mémoire vidéo (5) associé à une adresse horizontale, avec une fréquence qui dépend de la fréquence de lignes du signal vidéo à générer; un circuit de stabilisation verticale (7, 10) pour la géneration d'un signal vertical représentant la position verticale momentanée du signal vidéo à générer; et un circuit comparateur (11, 12) qui génère un signal de comparaison qui représente un point du signal de mesure dans la ligne momentanément générée du signal vidéo lorsque le signal vertical concorde approximativement avec un signal dérivé du circuit de mémoire vidéo (5), caracterérisé en ce qu'entre le circuit de mémoire vidéo (5) et le circuit comparateur (11, 12) sont intercalés un convertisseur D/A vidéo (8) et un circuit de filtre passe-bas (9) qui génèrent le signal dérivé en raison du contenu de mémoire activé dans le circuit de mémoire vidéo (5).
2. Circuit selon la revendication 1, caractérisé en ce que le signal de comparaison généré par le circuit comparateur (11, 12) présente une valeur maximale lorsque le signal vertical concorde avec le signal de sortie du convertisseur D/A vidéo (8); qu'il diminue progressivement au fur et à mesure que la différence entre le signal vertical et le signal de sortie augmente; et que, lorsque cette différence dépasse une valeur limite, il prend la valeur qui repésente l'absence du point du signal de mesure dans la ligne momentanément générée du signal vidéo.
3. Circuit selon l'une des revendications 1 ou 2, caractérisé en ce que la fréquence de base du circuit de filtre passe-bas (9) se situe entre un tiers et un dixième de la fréquence de lignes multipliée par le nombre des points d'image par ligne.
4. Circuit selon l'une quelconque des revendications 1 à 3, caractérisé en ce que la fréquence limite du circuit de filtre passe-bas (9) se situe entre 1 et 10 MHz.
5. Circuit selon l'une quelconque des revendications 1 à 4, caractérisé en ce que le convertisseur D/A vidéo (8) comprend un circuit d'entretien relié à son entrée.
6. Circuit selon l'une quelconque des revendications 1 à 5, caractérisé en ce qu'à la sortie du circuit comparateur (11, 12) est connecté un circuit d'élargissement du signal de comparaison dont le signal de sortie répond rapidement à une montée du signal de comparaison et seulement en fonction d'une constante de temps prédéterminée, à une descente du signal de comparaison.
7. Circuit selon l'une quelconque des revendications 1 à 6, caractérisé en ce qu'un circuit de mémoire-tampon (3, 4) pour des données de signal de mesure formées à partir du signal de mesure est connecté à l'entrée de données du circuit de mémoire vidéo (5), et que le contenu de mémoire du circuit de mémoire-tampon (3, 4) peut respectivement être rangé dans la mémoire vidéo (5) après la génération d'un signal vidéo représentant une trame.
8. Circuit selon l'une quelconque des revendications 1 à 7, caractérisé en ce que le circuit de commande d'adresses horizontales (6) comprend un synchroniseur de pixels (100) qui, en synchronisme avec un signal de synchronisation horizontale, génère un signal d'impulsion avec une fréquence de lignes multipliée par le nombre des points d'image par ligne; et que le circuit de commande d'adresses horizontales (6) comprend un premier compteur (101 à 103) générant l'adresse momentanée d'une cellule de mémoire à activer du circuit de mémoire vidéo (5) qui est relié au synchroniseur de pixels (100) et dont la valeur de comptage peut être variée, lors de la génération de chaque ligne, en fonction du signal d'impulsion du synchroniseur de pixels (100), en commençant par une adresse de lancement respectivement invariable pour chaque trame.
9. Circuit selon la revendication 8, caractérisé en ce que le circuit de mémoire-tampon (3, 4) comprend un microordinateur (3) qui, avant la génération d'un signal vidéo représentant une trame, modifie respectivement l'adresse de lancement momentanée du premier compteur (101 à 103) d'une différence d'adresse de lancement prédéterminée par rapport à l'adresse de lancement du premier compteur (101 à 103) pour la génération du signal vidéo représentant la trame précécente.
10. Circuit selon l'une des revendications 8 ou 9, caractérisé en ce que le circuit de commande d'adresses horizontales (6) comprend un deuxième compteur (104 à 106) qui est relié au synchroniseur de pixels (100) et permet, après le comptage d'un nombre d'impulsions du synchroniseur de pixels (10) commençant avec une deuxième adresse de lancement et correspondant à un nombre de points d'image d'une ligne d'une longueur désirée, de générer un signal de dépassement; que le circuit de commande d'adresses horizontales (6) comprend un circuit logique (107, 108) lequel peut être activé par le signal de synchronisation horizontale et remis à zéro par le signal de dépassement du deuxième compteur et qui communique avec les premier et deuxième compteurs (101 à 103; 104 à 106); et que les premier et deuxième compteurs (101 à 103; 104 à 106) peuvent être chargés avec les adresses de lancement pendant l'état de remise à zéro du circuit logique (107, 108).
11. Circuit selon la revendication 10, caractérisé en ce que le circuit de stabilisation verticale (7, 10) comprend un troisième compteur (109) qui compte les impulsions du signal de synchronisation horizontale et qui est remis à zéro par le signal de synchronisation verticale; et que le circuit de stabilisation verticale (7, 10) comprend, en outre, une mémoire morte programmable (51, 51 reliée au troisième compteur (50) laquelle est connectée à un convertisseur D/A vertical (10, 10') qui génère le signal vertical.
12. Circuit selon la revendication 11, caractérisé en ce que le circuit de stabilisation verticale (7, 10) génère, avec des valeurs de comptage croissantes du troisième compteur (50), un signal vertical en dents de scie qui présente un nombre de rampes en dents de scie correspondant au nombre des signaux de mesure pouvant être représentés simultanément.
13. Circuit selon l'une quelconque des revendications 1 à 12, caractérisé en ce qu'il comprend deux circuits dont chacun est constitué par le circuit de stabilisation verticale (7, 10), le circuit de mémoire vidéo (5), le convertisseur D/A vidéo (8), le circuit de filtre passe-bas (9) et le circuit comparateur (11, 12).
EP85105223A 1985-04-29 1985-04-29 Circuit de génération d'un signal vidéo représentant une valeur de mesure Expired EP0200795B1 (fr)

Priority Applications (5)

Application Number Priority Date Filing Date Title
EP85105223A EP0200795B1 (fr) 1985-04-29 1985-04-29 Circuit de génération d'un signal vidéo représentant une valeur de mesure
DE8585105223T DE3565020D1 (en) 1985-04-29 1985-04-29 Circuit for generating a video signal representing a measured value
US06/855,179 US4700227A (en) 1985-04-29 1986-04-23 Circuit for producing a video signal representing a measuring signal
JP61093522A JPS61253472A (ja) 1985-04-29 1986-04-24 測定信号表示用ビデオ信号発生回路
CA000507905A CA1248649A (fr) 1985-04-29 1986-04-29 Circuit de lecture de signaux video de mesure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP85105223A EP0200795B1 (fr) 1985-04-29 1985-04-29 Circuit de génération d'un signal vidéo représentant une valeur de mesure

Publications (2)

Publication Number Publication Date
EP0200795A1 EP0200795A1 (fr) 1986-11-12
EP0200795B1 true EP0200795B1 (fr) 1988-09-14

Family

ID=8193473

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Application Number Title Priority Date Filing Date
EP85105223A Expired EP0200795B1 (fr) 1985-04-29 1985-04-29 Circuit de génération d'un signal vidéo représentant une valeur de mesure

Country Status (5)

Country Link
US (1) US4700227A (fr)
EP (1) EP0200795B1 (fr)
JP (1) JPS61253472A (fr)
CA (1) CA1248649A (fr)
DE (1) DE3565020D1 (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4772948A (en) * 1987-10-26 1988-09-20 Tektronix, Inc. Method of low cost self-test in a video display system system
US4780755A (en) * 1987-10-26 1988-10-25 Tektronix, Inc. Frame buffer self-test
AU4597393A (en) * 1992-07-22 1994-02-14 Allen Testproducts Division, Allen Group Inc. Method and apparatus for combining video images
US8593526B1 (en) * 2012-06-22 2013-11-26 Silicon Laboratories Inc. Apparatus for measuring noise in an analog signal

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3686662A (en) * 1970-11-12 1972-08-22 Int Standard Electric Corp Circuit arrangement for the presentation of waveforms on viewing screens utilizing raster deflection
US3875328A (en) * 1973-08-03 1975-04-01 Rca Corp Apparatus and method for measuring the signal to noise ratio for a periodic signal
US4068310A (en) * 1976-07-22 1978-01-10 The United States Of America As Represented By The Department Of Health, Education And Welfare Display enhancement technique for video moving trace display
DE2821024C3 (de) * 1978-05-12 1981-02-05 Institut Fuer Rundfunktechnik Gmbh, 8000 Muenchen Signalgenerator zur Synthese von Fernseh-Priifzeilensignalen
US4225940A (en) * 1978-10-02 1980-09-30 Tektronix, Inc. Oscilloscope system for acquiring, processing, and displaying information
US4326219A (en) * 1980-04-11 1982-04-20 Ampex Corporation Digital error measuring circuit for shading and registration errors in television cameras

Also Published As

Publication number Publication date
US4700227A (en) 1987-10-13
JPS61253472A (ja) 1986-11-11
DE3565020D1 (en) 1988-10-20
JPH0370231B2 (fr) 1991-11-06
EP0200795A1 (fr) 1986-11-12
CA1248649A (fr) 1989-01-10

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