EP0196310A1 - Controleur de circuits integres et telecircuits electroniques a broches - Google Patents

Controleur de circuits integres et telecircuits electroniques a broches

Info

Publication number
EP0196310A1
EP0196310A1 EP85904562A EP85904562A EP0196310A1 EP 0196310 A1 EP0196310 A1 EP 0196310A1 EP 85904562 A EP85904562 A EP 85904562A EP 85904562 A EP85904562 A EP 85904562A EP 0196310 A1 EP0196310 A1 EP 0196310A1
Authority
EP
European Patent Office
Prior art keywords
integrated circuit
forcing
fet
force
circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP85904562A
Other languages
German (de)
English (en)
Inventor
John L. Peterson
Mavin Swapp
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of EP0196310A1 publication Critical patent/EP0196310A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31924—Voltage or current aspects, e.g. driver, receiver

Definitions

  • the present invention relates, in general, to an electronic apparatus for use at the test head of an automated integrated circuit tester. More particularly, the invention relates to a low device count circuit which allows the forcing and measuring circuits of an automated integrated circuit tester to be located a relatively great distance from the test head.
  • remote FAM 22 via its force high voltage line and FET 35, can control the coupling of high range voltage forcing line 37 to high range force and measure line 27.
  • a gate of FET 36 is connected to a force low voltage line from remote FAM 22.
  • a drain of FET 36 is connected to low range force and measure line 28.
  • a of FET 36 is connected to low range voltage forcing line 38. Therefore, remote FAM 22, via its force low voltage line and FET 36, can control the coupling of low range voltage forcing line 38 to low range force and measure line 28.

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)

Abstract

Des circuits électroniques et de mesure se situent à distance de la tête de contrôle. Un circuit de comptage (20) de dispositif bas effectue la commutation rapide nécessaire au niveau de chaque broche (21). Les lignes de force et de mesure sont relativement longues, mais les débits de signaux sont assez bas pour être transmis avec précision. Les seuls signaux à débit élevé sont ceux transmis par des lignes couplées aux circuits de porte de commutateurs de TEC (25, 26, 30, 31, 35, 36) au niveau de la tête de contrôle. Il devient ainsi possible de procéder à des contrôles de broches multiples et à haute vitesse en utilisant des têtes de contrôle relativement petites et économiques.
EP85904562A 1984-10-01 1985-09-09 Controleur de circuits integres et telecircuits electroniques a broches Withdrawn EP0196310A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US65681084A 1984-10-01 1984-10-01
US656810 1984-10-01

Publications (1)

Publication Number Publication Date
EP0196310A1 true EP0196310A1 (fr) 1986-10-08

Family

ID=24634664

Family Applications (1)

Application Number Title Priority Date Filing Date
EP85904562A Withdrawn EP0196310A1 (fr) 1984-10-01 1985-09-09 Controleur de circuits integres et telecircuits electroniques a broches

Country Status (4)

Country Link
EP (1) EP0196310A1 (fr)
JP (1) JPS62500319A (fr)
KR (1) KR930000545B1 (fr)
WO (1) WO1986002167A1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4989209A (en) * 1989-03-24 1991-01-29 Motorola, Inc. Method and apparatus for testing high pin count integrated circuits
US7560947B2 (en) 2005-09-28 2009-07-14 Teradyne, Inc. Pin electronics driver

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3564408A (en) * 1968-08-12 1971-02-16 Bendix Corp Test device for an electrical circuit card
US4038599A (en) * 1974-12-30 1977-07-26 International Business Machines Corporation High density wafer contacting and test system
JPS53143144A (en) * 1977-05-20 1978-12-13 Nec Corp Test unit for logical function

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO8602167A1 *

Also Published As

Publication number Publication date
KR880700274A (ko) 1988-02-22
KR930000545B1 (ko) 1993-01-25
JPS62500319A (ja) 1987-02-05
WO1986002167A1 (fr) 1986-04-10

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Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 19860602

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): DE FR GB IT

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 19871001

RIN1 Information on inventor provided before grant (corrected)

Inventor name: PETERSON, JOHN, L.

Inventor name: SWAPP, MAVIN