EP0192139A3 - Dispositif de commande d'une mémoire tampon de trame - Google Patents

Dispositif de commande d'une mémoire tampon de trame Download PDF

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Publication number
EP0192139A3
EP0192139A3 EP86101598A EP86101598A EP0192139A3 EP 0192139 A3 EP0192139 A3 EP 0192139A3 EP 86101598 A EP86101598 A EP 86101598A EP 86101598 A EP86101598 A EP 86101598A EP 0192139 A3 EP0192139 A3 EP 0192139A3
Authority
EP
European Patent Office
Prior art keywords
frame buffer
buffer memory
memory controller
pixel
read
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP86101598A
Other languages
German (de)
English (en)
Other versions
EP0192139A2 (fr
Inventor
David L. Knierim
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tektronix Inc
Original Assignee
Tektronix Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tektronix Inc filed Critical Tektronix Inc
Publication of EP0192139A2 publication Critical patent/EP0192139A2/fr
Publication of EP0192139A3 publication Critical patent/EP0192139A3/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Digital Computer Display Output (AREA)
  • Image Input (AREA)
EP86101598A 1985-02-19 1986-02-07 Dispositif de commande d'une mémoire tampon de trame Withdrawn EP0192139A3 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US70298285A 1985-02-19 1985-02-19
US702982 1991-05-20

Publications (2)

Publication Number Publication Date
EP0192139A2 EP0192139A2 (fr) 1986-08-27
EP0192139A3 true EP0192139A3 (fr) 1990-04-25

Family

ID=24823451

Family Applications (1)

Application Number Title Priority Date Filing Date
EP86101598A Withdrawn EP0192139A3 (fr) 1985-02-19 1986-02-07 Dispositif de commande d'une mémoire tampon de trame

Country Status (3)

Country Link
EP (1) EP0192139A3 (fr)
JP (1) JPS61190387A (fr)
CA (1) CA1264496A (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4903217A (en) * 1987-02-12 1990-02-20 International Business Machines Corp. Frame buffer architecture capable of accessing a pixel aligned M by N array of pixels on the screen of an attached monitor
GB2203317B (en) * 1987-04-02 1991-04-03 Ibm Display system
JPH05282199A (ja) * 1992-03-30 1993-10-29 Sony Corp 画像メモリ装置
DE69422324T2 (de) * 1993-03-29 2000-07-27 Koninklijke Philips Electronics N.V., Eindhoven Speicherarchitektur mit Fenstern zum Bildkompilieren
EP0618560B1 (fr) * 1993-03-29 1999-12-29 Koninklijke Philips Electronics N.V. Architecture de mémoire à base de fenêtre par compilation d'images
CN109410828B (zh) * 2018-11-29 2020-12-08 宗仁科技(平潭)有限公司 Led点光源驱动方法、系统及控制器

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4092728A (en) * 1976-11-29 1978-05-30 Rca Corporation Parallel access memory system
WO1983003036A1 (fr) * 1982-02-24 1983-09-01 Lahti, Mauritz, Johan, Birger Systeme de telecommunications pour la transmission de donnees par l'intermediaire d'un central numerique

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58123138A (ja) * 1982-01-18 1983-07-22 Toshio Imao 表示用メモリ制御方式
JPS59232390A (ja) * 1983-06-16 1984-12-27 株式会社東芝 表示装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4092728A (en) * 1976-11-29 1978-05-30 Rca Corporation Parallel access memory system
US4150364A (en) * 1976-11-29 1979-04-17 Rca Corporation Parallel access memory system
WO1983003036A1 (fr) * 1982-02-24 1983-09-01 Lahti, Mauritz, Johan, Birger Systeme de telecommunications pour la transmission de donnees par l'intermediaire d'un central numerique

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
ELECTRONIC DESIGN, vol. 32, no. 14, July 1984, pages 135-142, Waseca, MN, Denville, NJ, US; H. ASSARPOUR: "Graphics controller chip raises video data rate, is simpler to program" *

Also Published As

Publication number Publication date
EP0192139A2 (fr) 1986-08-27
JPS61190387A (ja) 1986-08-25
CA1264496A (fr) 1990-01-16

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Inventor name: KNIERIM, DAVID L.