EP0192139A2 - Dispositif de commande d'une mémoire tampon de trame - Google Patents

Dispositif de commande d'une mémoire tampon de trame Download PDF

Info

Publication number
EP0192139A2
EP0192139A2 EP86101598A EP86101598A EP0192139A2 EP 0192139 A2 EP0192139 A2 EP 0192139A2 EP 86101598 A EP86101598 A EP 86101598A EP 86101598 A EP86101598 A EP 86101598A EP 0192139 A2 EP0192139 A2 EP 0192139A2
Authority
EP
European Patent Office
Prior art keywords
frame buffer
buffer memory
pixel
memory controller
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP86101598A
Other languages
German (de)
English (en)
Other versions
EP0192139A3 (fr
Inventor
David L. Knierim
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tektronix Inc
Original Assignee
Tektronix Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tektronix Inc filed Critical Tektronix Inc
Publication of EP0192139A2 publication Critical patent/EP0192139A2/fr
Publication of EP0192139A3 publication Critical patent/EP0192139A3/fr
Withdrawn legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory

Definitions

  • the present invention relates to frame buffer memory systems for raster displays, and more particularly to a frame buffer memory controller for allowing rapid picture updating while maintaining screen refresh data flow rate.
  • Raster scan, frame buffer displays have become increasingly popular as the price of semiconductor memory has decreased.
  • the image to be displayed is represented in a large memory that saves a digital representation of the intensity and/or color of each picture element, or pixel, on the screen.
  • By properly recording the data in the memory an arbitrary image can be displayed, making the display hardware insensitive to image content.
  • the frame buffer memory is equipped with hardware to generate a video signal to refresh the display and with a memory port to allow a host computer or display processor to change the frame buffer memory in order to change the image being displayed.
  • Interactive graphics applications require rapid changes to the displayed image, which in turn require rapid changes to the frame buffer memory.
  • the speed of the host processor and display processor is clearly important to high performance, so also are the properties of the memory system, such as update bandwidth, i.e., the rate at which the host processor or data processor may access each pixel.
  • update bandwidth i.e., the rate at which the host processor or data processor may access each pixel.
  • the implicit geometry of frame buffer memory access can affect this rate.
  • Conventional pixel memory systems arrange words of memory so that a single memory cycle provides access to sixteen, twenty, thirty-two, or some other fixed number of pixels in a horizontal scan line on a display.
  • Other systems use arrays of pixels, such as 4x4, 4x5, 8x8, etc. for each frame buffer word.
  • a conventional frame buffer memory writes pixels along a horizontal line very rapidly, but is slow for most other directions.
  • For a frame buffer memory with a 16 pixel wide by 1 pixel high word let the average time to do a memory write be T seconds (including the delay caused by interspersed display refresh reads). Then horizontal lines can be written at a rate as high as 16/T pixels per second. Since the beginning and end of the lines will generally not lie on word boundaries, the actual rate will be less than 16/T on average. Now consider a vertical line, or any line steeper than 45 degrees. Every pixel written will lie in a different word. The pixel rate is thus 1/T pixels per second. Averaging the pixel drawing rate over all vector angles and ignoring the end effects gives roughly 1.36/T pixels per second.
  • Frame buffer memories with words covering a rectangular array of pixels improve on the average pixel writing rate.
  • the pixel writing rate thus approaches 4/T )pixels per second.
  • What is desired is a means for speeding up the process of updating the image in frame buffer memory, i.e., increasing update bandwidth.
  • the present invention provides a Frame buffer memory controller which allows rapid Lmage updating while maintaining screen refresh data flow rate.
  • One frame buffer memory controller controls one or more pixel depth columns comprising one or more frame buffer memory chips per pixel.
  • Each frame buffer memory controller listens on a display processor bus for read, write or read-modify-write commands addressed to a pixel, or memory chip, under its control. Such commands, along with the associated addresses and data, are stored in a first-in, first-out (FIFO) buffer for execution during the first free memory cycle.
  • FIFO first-in, first-out
  • the frame buffer memory 20 has a plurality of memory devices 22, typically random access memories (RAM), each RAM corresponding to one plane of one pixel bit in a display or frame buffer, word as shown in Figs. 2A through 2D.
  • RAM random access memories
  • the number of RAMs 22 is lx16xn where n is the number of planes (number of bits per pixel).
  • a 1024x1024 raster display would require such RAMs to have a 64K capacity.
  • a frame buffer memory controller 24 serves as an interface with a display processor bus 26.
  • Each frame buffer memory controller 24 recognizes addresses from the display processor bus 26 which pertain to the RAMs 22 under its control.
  • the associated commands/data are then routed to the appropriate RAM 22 and location within that RAM corresponding to the particular display word via address bus 28 and/or data bus 30 from the frame buffer memory controller 24.
  • Data to be displayed is transferred via the frame buffer memory controller 24 to a digital-to-analog converter 32 for conversion to video data.
  • the example shown for Fig. 1 is illustrative of the configuration for a 16-pixel display word of 4-bits, or planes, per pixel. Inserted between the FBMCs 24 and DAC 32 may be a color map 33 for determining the color of each pixel.
  • Fig. 1 shows the pixel data for display refresh coming from the FBMCs 24.
  • video RAMs 22, such as the TMS 4161 by Texas Instruments Inc., Dallas, Texas, that have integral video shift registers, could be used equally well.
  • the color map 33 or other logic may be inserted in the pixel data path before the DAC 32.
  • the pixel data outputs of the FBMCs 24 are bussed together onto one set of wires (one wire per plane). Under this scheme each FBMC 24 drives the pixel data bus for one pixel clock, then tristates its outputs to allow the next FBMC to send its pixel data. This is practical for low resolution displays with slow pixel clocks.
  • each FBMC For higher resolution displays the pixel data outputs from each FBMC are not bussed, but are connected to video shift registers as in conventional frame buffer memories with one shift register per plane. Each shift register receives one bit, or as many bits as there are pixels in the display word controlled by the FBMC 24, from each FBMC. Other variations are possible, such as incorporating the shift registers within the FBMCs 24 so that the pixel data output from each FBMC shifts into the next one, with the final output connecting to the color map 33 or DAC 32.
  • the frame buffer memory controller 24 is shown in some detail in Fig. 3.
  • An address recognizer circuit 34 is connected to the display controller bus 26 to determine those operations directed to the pixels controlled by that particular frame buffer memory controller. The recognized address is stored in a portion 36 of a FIFO buffer 35 when an associated command is received.
  • Display refresh timing is provided by a video timing circuit 44 and the pixels are addressed sequentially via a refresh address counter 46.
  • An address multiplexer 48 passes the addresses from the refresh address counter 46 to the RAMs 22 during the refresh cycle, and passes the addresses from the first FIFO buffer 36 to the RAMs 22 for image changes during free memory cycles.
  • the address recognizer circuit 34 may be replaced by an external address decoder 37 on the display processor bus 26 which routes the command/data/addresses to the appropriate FBMCs 24.
  • the command/data information is stored in respective portions 50,52 of the FIFO buffer 35 along with the address information.
  • the appropriate RAM 22 is accessed according to the first-in address in the address buffer 36, and the associated command in the command buffer 50 is executed, data in the write buffer 52 being written into the RAM, or data being read from the RAM and either stored in the read buffer 54 for transfer to the display processor via the display bus 26 or for modification and rewrite into the RAM via a read-modify-write (RMW) logic circuit 56.
  • RMW read-modify-write
  • the frame buffer memory 20 can constantly receive commands/data via the display bus 26 from the display processor even while pixel data is being read from the memory units 22 to refresh the display screen.
  • the command/data information together with RAM address is stored in the FIFO buffer 35 and acted upon at the first free memory cycle.
  • the image on the display is rapidly updated since the information for each pixel can be transmitted to the frame buffer memory via the frame buffer memory controllers while the display screen is being refreshed.
  • performance is enhanced by the fact that all n FMBCs 24 can be writing pixels simultaneously even when the pixels being written are not on a single horizontal line.
  • a frame buffer memory 20 as shown in Fig. 1 can write pixels at a rate approaching 16/T per second. This speed improvement is obtained by dividing the frame buffer memory 20 into 16 separate pieces, one for each pixel in the frame buffer word. Each piece of the memory 20 has separate address and data lines controlled by a separate frame buffer memory controller 24. Thus memory accesses are no longer limited to fixed frame buffer words. At any moment each of the 16 FBMCs 24 may be writing a pixel to a different frame buffer word.
  • each frame buffer memory controller 24 has a FIFO buffer 35 for commands, address and data coming from the display processor in addition to the separate address and data lines to the RAMS 22 controlled by it.
  • This FIFO buffer 35 serves two purposes. First, it allows continued receiving of commands from the display processor while the frame buffer memory 20 is busy with display refresh reads. This advantage becomes negligible if video RAMs are used.
  • the second and more important purpose is to allow multiple display processor commands to address the same frame buffer memory controller 24 (same one of the 16 pieces of frame buffer memory 20) without waiting for each memory cycle to finish before sending the next command. On average the display processor commands will address each piece of the memory (each frame buffer memory controller 24) at an equal rate. Over short periods of time, however, one or a few FBMCs 24 may receive most of the commands.
  • the FIFO buffer 35 smoothes out this short term unevenness allowing all pieces of memory to keep busy most of the time.
  • the above example requires the FBMCs 24 to have a FIFO buffer 35 of length 3 or larger to run at the full 16/T rate.
  • stepper lines close to vertical
  • the required FIFO buffer size is larger.
  • some reasonable FIFO buffer size of 32 words per FBMC 24 Then long lines with slope much over 32 fill the FIFO buffer 35 of one FBMC 24, requiring the display processor to wait until some of the write commands have been executed before continuing.
  • Short vertical lines do not cause this problem unless several lines in succession address the same FBMC 24.
  • this fraction is very small, and can be made to approach zero by increasing the FIFO buffer size.
  • this example system yields roughly 13/T to 14/T pixels per second with its 32 word FIFO buffer 35.
  • a 20 pixel frame buffer word may be organized as 10 pixels wide by 2 pixels high with 5 FBMCs 24 each controlling a 2 by 2 pixel square within the word. This reduces the number of FBMCs 24 required from 20 to 5.
  • the present invention provides a frame buffer memory which improves image update bandwidth by using a frame buffer memory controller with a first-in, first-out buffer for each pixel, or small group of pixels, within a frame buffer word.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Image Input (AREA)
  • Digital Computer Display Output (AREA)
EP86101598A 1985-02-19 1986-02-07 Dispositif de commande d'une mémoire tampon de trame Withdrawn EP0192139A3 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US70298285A 1985-02-19 1985-02-19
US702982 1985-02-19

Publications (2)

Publication Number Publication Date
EP0192139A2 true EP0192139A2 (fr) 1986-08-27
EP0192139A3 EP0192139A3 (fr) 1990-04-25

Family

ID=24823451

Family Applications (1)

Application Number Title Priority Date Filing Date
EP86101598A Withdrawn EP0192139A3 (fr) 1985-02-19 1986-02-07 Dispositif de commande d'une mémoire tampon de trame

Country Status (3)

Country Link
EP (1) EP0192139A3 (fr)
JP (1) JPS61190387A (fr)
CA (1) CA1264496A (fr)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0279228A2 (fr) * 1987-02-12 1988-08-24 International Business Machines Corporation Mémoire d'image pour l'affichage vidéo à balayage de trame
EP0284905A2 (fr) * 1987-04-02 1988-10-05 International Business Machines Corporation Système d'affichage
EP0563855A2 (fr) * 1992-03-30 1993-10-06 Sony Corporation Dispositif de mémorisation d'image et dispositif d'affichage graphique
EP0618560A1 (fr) * 1993-03-29 1994-10-05 Koninklijke Philips Electronics N.V. Architecture de mémoire à base de fenêtre par compilation d'images
US5731811A (en) * 1993-03-29 1998-03-24 U.S. Philips Corporation Window-based memory architecture for image compilation
CN109410828A (zh) * 2018-11-29 2019-03-01 宗仁科技(平潭)有限公司 Led点光源驱动方法、系统及控制器

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4092728A (en) * 1976-11-29 1978-05-30 Rca Corporation Parallel access memory system
WO1983003036A1 (fr) * 1982-02-24 1983-09-01 Lahti, Mauritz, Johan, Birger Systeme de telecommunications pour la transmission de donnees par l'intermediaire d'un central numerique

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58123138A (ja) * 1982-01-18 1983-07-22 Toshio Imao 表示用メモリ制御方式
JPS59232390A (ja) * 1983-06-16 1984-12-27 株式会社東芝 表示装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4092728A (en) * 1976-11-29 1978-05-30 Rca Corporation Parallel access memory system
US4150364A (en) * 1976-11-29 1979-04-17 Rca Corporation Parallel access memory system
WO1983003036A1 (fr) * 1982-02-24 1983-09-01 Lahti, Mauritz, Johan, Birger Systeme de telecommunications pour la transmission de donnees par l'intermediaire d'un central numerique

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
ELECTRONIC DESIGN, vol. 32, no. 14, July 1984, pages 135-142, Waseca, MN, Denville, NJ, US; H. ASSARPOUR: "Graphics controller chip raises video data rate, is simpler to program" *

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0279228A2 (fr) * 1987-02-12 1988-08-24 International Business Machines Corporation Mémoire d'image pour l'affichage vidéo à balayage de trame
EP0279228A3 (fr) * 1987-02-12 1991-04-17 International Business Machines Corporation Mémoire d'image pour l'affichage vidéo à balayage de trame
EP0284905A2 (fr) * 1987-04-02 1988-10-05 International Business Machines Corporation Système d'affichage
EP0284905A3 (en) * 1987-04-02 1990-09-19 International Business Machines Corporation Display system
EP0563855A2 (fr) * 1992-03-30 1993-10-06 Sony Corporation Dispositif de mémorisation d'image et dispositif d'affichage graphique
EP0563855A3 (en) * 1992-03-30 1995-11-22 Sony Corp Picture storage apparatus and graphic engine apparatus
US5539873A (en) * 1992-03-30 1996-07-23 Sony Corporation Picture storage apparatus and graphic engine apparatus
EP0618560A1 (fr) * 1993-03-29 1994-10-05 Koninklijke Philips Electronics N.V. Architecture de mémoire à base de fenêtre par compilation d'images
US5731811A (en) * 1993-03-29 1998-03-24 U.S. Philips Corporation Window-based memory architecture for image compilation
CN109410828A (zh) * 2018-11-29 2019-03-01 宗仁科技(平潭)有限公司 Led点光源驱动方法、系统及控制器

Also Published As

Publication number Publication date
CA1264496A (fr) 1990-01-16
JPS61190387A (ja) 1986-08-25
EP0192139A3 (fr) 1990-04-25

Similar Documents

Publication Publication Date Title
US5109520A (en) Image frame buffer access speedup by providing multiple buffer controllers each containing command FIFO buffers
US4991110A (en) Graphics processor with staggered memory timing
EP0197413B1 (fr) Mémoire tampon de trame
EP0197412B1 (fr) Mémoire tampon d'image à accès variable
US4907086A (en) Method and apparatus for overlaying a displayable image with a second image
US5099331A (en) Apparatus for overlaying a displayed image with a second image
EP0279226B1 (fr) Interface pour l'affichage vidéo graphique à haute résolution
US4646270A (en) Video graphic dynamic RAM
EP0318259B1 (fr) Architecture de mémoire configurable par programme pour un système de traitement de données ayant des capacités graphiques
US5909225A (en) Frame buffer cache for graphics applications
US4745407A (en) Memory organization apparatus and method
US6825845B2 (en) Virtual frame buffer control system
EP0279225B1 (fr) Compteurs à configuration variable pour l'adressage dans les systèmes de visualisation graphiques
US5258843A (en) Method and apparatus for overlaying displayable information
EP0525749B1 (fr) Dispositif de commande de mémoire
EP0481534B1 (fr) Système vidéo
US5717904A (en) Apparatus and methods for automatically controlling block writes
US4912658A (en) Method and apparatus for addressing video RAMS and refreshing a video monitor with a variable resolution
EP0525986A2 (fr) Appareil à copie rapide entre des tampons de trame dans un système d'affichage à double mémoire-tampon
JPH07271970A (ja) ダイナミックランダムアクセスメモリ、ダイナミックランダムアクセスメモリのアクセス方法及びシステム
EP0192139A2 (fr) Dispositif de commande d'une mémoire tampon de trame
US4660155A (en) Single chip video system with separate clocks for memory controller, CRT controller
US4695838A (en) Plasma panel display selectively updatable on pel line basis
US4660156A (en) Video system with single memory space for instruction, program data and display data
US5504503A (en) High speed signal conversion method and device

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): DE FR GB NL

PUAL Search report despatched

Free format text: ORIGINAL CODE: 0009013

AK Designated contracting states

Kind code of ref document: A3

Designated state(s): DE FR GB NL

17P Request for examination filed

Effective date: 19900531

17Q First examination report despatched

Effective date: 19911105

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 19920901

RIN1 Information on inventor provided before grant (corrected)

Inventor name: KNIERIM, DAVID L.